2 * (C) Copyright 2000-2006
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 * written or collected and sometimes rewritten by
28 * Magnus Damm <damm@bitsmart.com>
30 * minor modifications by
31 * Wolfgang Denk <wd@denx.de>
37 #include <asm/cache.h>
40 #if !defined(CONFIG_405)
41 DECLARE_GLOBAL_DATA_PTR;
44 #if defined(CONFIG_BOARD_RESET)
45 void board_reset(void);
48 #if defined(CONFIG_440)
49 #define FREQ_EBC (sys_info.freqEPB)
51 #define FREQ_EBC (sys_info.freqPLB / sys_info.pllExtBusDiv)
54 #if defined(CONFIG_405GP) || \
55 defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
56 defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
60 int pci_async_enabled(void)
62 #if defined(CONFIG_405GP)
63 return (mfdcr(strap) & PSR_PCI_ASYNC_EN);
66 #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
67 defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
70 mfsdr(sdr_sdstp1, val);
71 return (val & SDR0_SDSTP1_PAME_MASK);
76 #if defined(CONFIG_PCI) && !defined(CONFIG_IOP480) && !defined(CONFIG_405)
77 int pci_arbiter_enabled(void)
79 #if defined(CONFIG_405GP)
80 return (mfdcr(strap) & PSR_PCI_ARBIT_EN);
83 #if defined(CONFIG_405EP)
84 return (mfdcr(cpc0_pci) & CPC0_PCI_ARBIT_EN);
87 #if defined(CONFIG_440GP)
88 return (mfdcr(cpc0_strp1) & CPC0_STRP1_PAE_MASK);
91 #if defined(CONFIG_440GX) || \
92 defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
93 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
94 defined(CONFIG_440SP) || defined(CONFIG_440SPE)
97 mfsdr(sdr_sdstp1, val);
98 return (val & SDR0_SDSTP1_PAE_MASK);
103 #if defined(CONFIG_405EP) || defined(CONFIG_440GX) || \
104 defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
105 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
106 defined(CONFIG_440SP) || defined(CONFIG_440SPE)
110 int i2c_bootrom_enabled(void)
112 #if defined(CONFIG_405EP)
113 return (mfdcr(cpc0_boot) & CPC0_BOOT_SEP);
117 mfsdr(sdr_sdcs, val);
118 return (val & SDR0_SDCS_SDD);
122 #if defined(CONFIG_440GX)
123 #define SDR0_PINSTP_SHIFT 29
124 static char *bootstrap_str[] = {
136 #if defined(CONFIG_440SP) || defined(CONFIG_440SPE)
137 #define SDR0_PINSTP_SHIFT 30
138 static char *bootstrap_str[] = {
146 #if defined(CONFIG_440EP) || defined(CONFIG_440GR)
147 #define SDR0_PINSTP_SHIFT 29
148 static char *bootstrap_str[] = {
160 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
161 #define SDR0_PINSTP_SHIFT 29
162 static char *bootstrap_str[] = {
174 #if defined(SDR0_PINSTP_SHIFT)
175 static int bootstrap_option(void)
179 mfsdr(sdr_pinstp, val);
180 return ((val & 0xe0000000) >> SDR0_PINSTP_SHIFT);
182 #endif /* SDR0_PINSTP_SHIFT */
186 #if defined(CONFIG_440)
187 static int do_chip_reset(unsigned long sys0, unsigned long sys1);
193 #if !defined(CONFIG_405) /* not used on Xilinx 405 FPGA implementations */
194 uint pvr = get_pvr();
195 ulong clock = gd->cpu_clk;
198 #if !defined(CONFIG_IOP480)
203 get_sys_info(&sys_info);
205 puts("AMCC PowerPC 4");
207 #if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_405EP)
210 #if defined(CONFIG_440)
228 case PVR_405GP_RE: /* 405GP rev E and 405CR rev C have same PVR */
242 case PVR_405CR_RC: /* 405GP rev E and 405CR rev C have same PVR */
255 #if defined(CONFIG_440)
258 /* See errata 1.12: CHIP_4 */
259 if ((mfdcr(cpc0_sys0) != mfdcr(cpc0_strp0)) ||
260 (mfdcr(cpc0_sys1) != mfdcr(cpc0_strp1)) ){
261 puts ( "\n\t CPC0_SYSx DCRs corrupted. "
262 "Resetting chip ...\n");
263 udelay( 1000 * 1000 ); /* Give time for serial buf to clear */
264 do_chip_reset ( mfdcr(cpc0_strp0),
294 case PVR_440EP_RB: /* 440EP rev B and 440GR rev A have same PVR */
298 case PVR_440EP_RC: /* 440EP rev C and 440GR rev B have same PVR */
301 #endif /* CONFIG_440EP */
304 case PVR_440GR_RA: /* 440EP rev B and 440GR rev A have same PVR */
308 case PVR_440GR_RB: /* 440EP rev C and 440GR rev B have same PVR */
311 #endif /* CONFIG_440GR */
312 #endif /* CONFIG_440 */
315 puts("EPx Rev. A - Security/Kasumi support");
319 puts("EPx Rev. A - No Security/Kasumi support");
323 puts("GRx Rev. A - Security/Kasumi support");
327 puts("GRx Rev. A - No Security/Kasumi support");
347 printf (" UNKNOWN (PVR=%08x)", pvr);
351 printf (" at %s MHz (PLB=%lu, OPB=%lu, EBC=%lu MHz)\n", strmhz(buf, clock),
352 sys_info.freqPLB / 1000000,
353 sys_info.freqPLB / sys_info.pllOpbDiv / 1000000,
356 #if defined(I2C_BOOTROM)
357 printf (" I2C boot EEPROM %sabled\n", i2c_bootrom_enabled() ? "en" : "dis");
358 #if defined(SDR0_PINSTP_SHIFT)
359 printf (" Bootstrap Option %c - ", (char)bootstrap_option() + 'A');
360 printf ("Boot ROM Location %s\n", bootstrap_str[bootstrap_option()]);
364 #if defined(CONFIG_PCI)
365 printf (" Internal PCI arbiter %sabled", pci_arbiter_enabled() ? "en" : "dis");
368 #if defined(PCI_ASYNC)
369 if (pci_async_enabled()) {
370 printf (", PCI async ext clock used");
372 printf (", PCI sync clock at %lu MHz",
373 sys_info.freqPLB / sys_info.pllPciDiv / 1000000);
377 #if defined(CONFIG_PCI)
381 #if defined(CONFIG_405EP)
382 printf (" 16 kB I-Cache 16 kB D-Cache");
383 #elif defined(CONFIG_440)
384 printf (" 32 kB I-Cache 32 kB D-Cache");
386 printf (" 16 kB I-Cache %d kB D-Cache",
387 ((pvr | 0x00000001) == PVR_405GPR_RB) ? 16 : 8);
389 #endif /* !defined(CONFIG_IOP480) */
391 #if defined(CONFIG_IOP480)
392 printf ("PLX IOP480 (PVR=%08x)", pvr);
393 printf (" at %s MHz:", strmhz(buf, clock));
394 printf (" %u kB I-Cache", 4);
395 printf (" %u kB D-Cache", 2);
398 #endif /* !defined(CONFIG_405) */
405 #if defined (CONFIG_440SPE)
406 int ppc440spe_revB() {
410 if (pvr == PVR_440SPe_RB)
417 /* ------------------------------------------------------------------------- */
419 int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
421 #if defined(CONFIG_BOARD_RESET)
425 * Initiate system reset in debug control register DBCR
427 mtspr(dbcr0, 0x30000000);
428 #endif /* defined(CONFIG_BOARD_RESET) */
433 #if defined(CONFIG_440)
434 static int do_chip_reset (unsigned long sys0, unsigned long sys1)
436 /* Changes to cpc0_sys0 and cpc0_sys1 require chip
439 mtdcr (cntrl0, mfdcr (cntrl0) | 0x80000000); /* Set SWE */
440 mtdcr (cpc0_sys0, sys0);
441 mtdcr (cpc0_sys1, sys1);
442 mtdcr (cntrl0, mfdcr (cntrl0) & ~0x80000000); /* Clr SWE */
443 mtspr (dbcr0, 0x20000000); /* Reset the chip */
451 * Get timebase clock frequency
453 unsigned long get_tbclk (void)
455 #if !defined(CONFIG_IOP480)
458 get_sys_info(&sys_info);
459 return (sys_info.freqProcessor);
467 #if defined(CONFIG_WATCHDOG)
471 int re_enable = disable_interrupts();
472 reset_4xx_watchdog();
473 if (re_enable) enable_interrupts();
477 reset_4xx_watchdog(void)
482 mtspr(tsr, 0x40000000);
484 #endif /* CONFIG_WATCHDOG */