2 * (C) Copyright 2006 - 2007
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * Copyright (c) 2005 Cisco Systems. All rights reserved.
6 * Roland Dreier <rolandd@cisco.com>
8 * See file CREDITS for list of people who contributed to this
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
23 /* define DEBUG for debugging output (obviously ;-)) */
28 #include <asm/processor.h>
29 #include <asm-ppc/io.h>
34 #if defined(CONFIG_440SPE) && defined(CONFIG_PCI)
36 #include <asm/4xx_pcie.h>
40 PTYPE_LEGACY_ENDPOINT = 0x1,
41 PTYPE_ROOT_PORT = 0x4,
48 static u8* pcie_get_base(struct pci_controller *hose, unsigned int devfn)
50 u8 *base = (u8*)hose->cfg_data;
52 /* use local configuration space for the first bus */
53 if (PCI_BUS(devfn) == 0) {
54 if (hose->cfg_data == (u8*)CFG_PCIE0_CFGBASE)
55 base = (u8*)CFG_PCIE0_XCFGBASE;
56 if (hose->cfg_data == (u8*)CFG_PCIE1_CFGBASE)
57 base = (u8*)CFG_PCIE1_XCFGBASE;
58 if (hose->cfg_data == (u8*)CFG_PCIE2_CFGBASE)
59 base = (u8*)CFG_PCIE2_XCFGBASE;
65 static void pcie_dmer_disable(void)
67 mtdcr (DCRN_PEGPL_CFG(DCRN_PCIE0_BASE),
68 mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE0_BASE)) | GPL_DMER_MASK_DISA);
69 mtdcr (DCRN_PEGPL_CFG(DCRN_PCIE1_BASE),
70 mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE1_BASE)) | GPL_DMER_MASK_DISA);
71 mtdcr (DCRN_PEGPL_CFG(DCRN_PCIE2_BASE),
72 mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE2_BASE)) | GPL_DMER_MASK_DISA);
75 static void pcie_dmer_enable(void)
77 mtdcr (DCRN_PEGPL_CFG (DCRN_PCIE0_BASE),
78 mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE0_BASE)) & ~GPL_DMER_MASK_DISA);
79 mtdcr (DCRN_PEGPL_CFG (DCRN_PCIE1_BASE),
80 mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE1_BASE)) & ~GPL_DMER_MASK_DISA);
81 mtdcr (DCRN_PEGPL_CFG (DCRN_PCIE2_BASE),
82 mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE2_BASE)) & ~GPL_DMER_MASK_DISA);
85 static int pcie_read_config(struct pci_controller *hose, unsigned int devfn,
86 int offset, int len, u32 *val) {
92 * Bus numbers are relative to hose->first_busno
94 devfn -= PCI_BDF(hose->first_busno, 0, 0);
97 * NOTICE: configuration space ranges are currenlty mapped only for
98 * the first 16 buses, so such limit must be imposed. In case more
99 * buses are required the TLB settings in board/amcc/<board>/init.S
100 * need to be altered accordingly (one bus takes 1 MB of memory space).
102 if (PCI_BUS(devfn) >= 16)
106 * Only single device/single function is supported for the primary and
107 * secondary buses of the 440SPe host bridge.
109 if ((!((PCI_FUNC(devfn) == 0) && (PCI_DEV(devfn) == 0))) &&
110 ((PCI_BUS(devfn) == 0) || (PCI_BUS(devfn) == 1)))
113 address = pcie_get_base(hose, devfn);
114 offset += devfn << 4;
117 * Reading from configuration space of non-existing device can
118 * generate transaction errors. For the read duration we suppress
119 * assertion of machine check exceptions to avoid those.
121 pcie_dmer_disable ();
125 *val = in_8(hose->cfg_data + offset);
128 *val = in_le16((u16 *)(hose->cfg_data + offset));
131 *val = in_le32((u32*)(hose->cfg_data + offset));
140 static int pcie_write_config(struct pci_controller *hose, unsigned int devfn,
141 int offset, int len, u32 val) {
146 * Bus numbers are relative to hose->first_busno
148 devfn -= PCI_BDF(hose->first_busno, 0, 0);
151 * Same constraints as in pcie_read_config().
153 if (PCI_BUS(devfn) >= 16)
156 if ((!((PCI_FUNC(devfn) == 0) && (PCI_DEV(devfn) == 0))) &&
157 ((PCI_BUS(devfn) == 0) || (PCI_BUS(devfn) == 1)))
160 address = pcie_get_base(hose, devfn);
161 offset += devfn << 4;
164 * Suppress MCK exceptions, similar to pcie_read_config()
166 pcie_dmer_disable ();
170 out_8(hose->cfg_data + offset, val);
173 out_le16((u16 *)(hose->cfg_data + offset), val);
176 out_le32((u32 *)(hose->cfg_data + offset), val);
185 int pcie_read_config_byte(struct pci_controller *hose,pci_dev_t dev,int offset,u8 *val)
190 rv = pcie_read_config(hose, dev, offset, 1, &v);
195 int pcie_read_config_word(struct pci_controller *hose,pci_dev_t dev,int offset,u16 *val)
200 rv = pcie_read_config(hose, dev, offset, 2, &v);
205 int pcie_read_config_dword(struct pci_controller *hose,pci_dev_t dev,int offset,u32 *val)
210 rv = pcie_read_config(hose, dev, offset, 3, &v);
215 int pcie_write_config_byte(struct pci_controller *hose,pci_dev_t dev,int offset,u8 val)
217 return pcie_write_config(hose,(u32)dev,offset,1,val);
220 int pcie_write_config_word(struct pci_controller *hose,pci_dev_t dev,int offset,u16 val)
222 return pcie_write_config(hose,(u32)dev,offset,2,(u32 )val);
225 int pcie_write_config_dword(struct pci_controller *hose,pci_dev_t dev,int offset,u32 val)
227 return pcie_write_config(hose,(u32)dev,offset,3,(u32 )val);
230 static void ppc4xx_setup_utl(u32 port) {
232 volatile void *utl_base = NULL;
239 mtdcr(DCRN_PEGPL_REGBAH(PCIE0), 0x0000000c);
240 mtdcr(DCRN_PEGPL_REGBAL(PCIE0), 0x20000000);
241 mtdcr(DCRN_PEGPL_REGMSK(PCIE0), 0x00007001);
242 mtdcr(DCRN_PEGPL_SPECIAL(PCIE0), 0x68782800);
246 mtdcr(DCRN_PEGPL_REGBAH(PCIE1), 0x0000000c);
247 mtdcr(DCRN_PEGPL_REGBAL(PCIE1), 0x20001000);
248 mtdcr(DCRN_PEGPL_REGMSK(PCIE1), 0x00007001);
249 mtdcr(DCRN_PEGPL_SPECIAL(PCIE1), 0x68782800);
253 mtdcr(DCRN_PEGPL_REGBAH(PCIE2), 0x0000000c);
254 mtdcr(DCRN_PEGPL_REGBAL(PCIE2), 0x20002000);
255 mtdcr(DCRN_PEGPL_REGMSK(PCIE2), 0x00007001);
256 mtdcr(DCRN_PEGPL_SPECIAL(PCIE2), 0x68782800);
259 utl_base = (unsigned int *)(CFG_PCIE_BASE + 0x1000 * port);
262 * Set buffer allocations and then assert VRB and TXE.
264 out_be32(utl_base + PEUTL_OUTTR, 0x08000000);
265 out_be32(utl_base + PEUTL_INTR, 0x02000000);
266 out_be32(utl_base + PEUTL_OPDBSZ, 0x10000000);
267 out_be32(utl_base + PEUTL_PBBSZ, 0x53000000);
268 out_be32(utl_base + PEUTL_IPHBSZ, 0x08000000);
269 out_be32(utl_base + PEUTL_IPDBSZ, 0x10000000);
270 out_be32(utl_base + PEUTL_RCIRQEN, 0x00f00000);
271 out_be32(utl_base + PEUTL_PCTL, 0x80800066);
274 static int check_error(void)
276 u32 valPE0, valPE1, valPE2;
279 /* SDR0_PEGPLLLCT1 reset */
280 if (!(valPE0 = SDR_READ(PESDR0_PLLLCT1) & 0x01000000)) {
281 printf("PCIE: SDR0_PEGPLLLCT1 reset error 0x%x\n", valPE0);
284 valPE0 = SDR_READ(PESDR0_RCSSET);
285 valPE1 = SDR_READ(PESDR1_RCSSET);
286 valPE2 = SDR_READ(PESDR2_RCSSET);
288 /* SDR0_PExRCSSET rstgu */
289 if (!(valPE0 & 0x01000000) ||
290 !(valPE1 & 0x01000000) ||
291 !(valPE2 & 0x01000000)) {
292 printf("PCIE: SDR0_PExRCSSET rstgu error\n");
296 /* SDR0_PExRCSSET rstdl */
297 if (!(valPE0 & 0x00010000) ||
298 !(valPE1 & 0x00010000) ||
299 !(valPE2 & 0x00010000)) {
300 printf("PCIE: SDR0_PExRCSSET rstdl error\n");
304 /* SDR0_PExRCSSET rstpyn */
305 if ((valPE0 & 0x00001000) ||
306 (valPE1 & 0x00001000) ||
307 (valPE2 & 0x00001000)) {
308 printf("PCIE: SDR0_PExRCSSET rstpyn error\n");
312 /* SDR0_PExRCSSET hldplb */
313 if ((valPE0 & 0x10000000) ||
314 (valPE1 & 0x10000000) ||
315 (valPE2 & 0x10000000)) {
316 printf("PCIE: SDR0_PExRCSSET hldplb error\n");
320 /* SDR0_PExRCSSET rdy */
321 if ((valPE0 & 0x00100000) ||
322 (valPE1 & 0x00100000) ||
323 (valPE2 & 0x00100000)) {
324 printf("PCIE: SDR0_PExRCSSET rdy error\n");
328 /* SDR0_PExRCSSET shutdown */
329 if ((valPE0 & 0x00000100) ||
330 (valPE1 & 0x00000100) ||
331 (valPE2 & 0x00000100)) {
332 printf("PCIE: SDR0_PExRCSSET shutdown error\n");
339 * Initialize PCI Express core
341 int ppc4xx_init_pcie(void)
345 /* Set PLL clock receiver to LVPECL */
346 SDR_WRITE(PESDR0_PLLLCT1, SDR_READ(PESDR0_PLLLCT1) | 1 << 28);
351 if (!(SDR_READ(PESDR0_PLLLCT2) & 0x10000))
353 printf("PCIE: PESDR_PLLCT2 resistance calibration failed (0x%08x)\n",
354 SDR_READ(PESDR0_PLLLCT2));
357 /* De-assert reset of PCIe PLL, wait for lock */
358 SDR_WRITE(PESDR0_PLLLCT1, SDR_READ(PESDR0_PLLLCT1) & ~(1 << 24));
362 if (!(SDR_READ(PESDR0_PLLLCT3) & 0x10000000)) {
369 printf("PCIE: VCO output not locked\n");
376 * Board-specific pcie initialization
377 * Platform code can reimplement ppc4xx_init_pcie_port_hw() if needed
381 * Initialize various parts of the PCI Express core for our port:
383 * - Set as a root port and enable max width
384 * (PXIE0 -> X8, PCIE1 and PCIE2 -> X4).
385 * - Set up UTL configuration.
386 * - Increase SERDES drive strength to levels suggested by AMCC.
387 * - De-assert RSTPYN, RSTDL and RSTGU.
389 * NOTICE for 440SPE revB chip: PESDRn_UTLSET2 is not set - we leave it
390 * with default setting 0x11310000. The register has new fields,
391 * PESDRn_UTLSET2[LKINE] in particular: clearing it leads to PCIE core
394 #if defined(CONFIG_440SPE)
395 int __ppc4xx_init_pcie_port_hw(int port, int rootport)
401 val = PTYPE_ROOT_PORT << 20;
402 utlset1 = 0x21222222;
404 val = PTYPE_LEGACY_ENDPOINT << 20;
405 utlset1 = 0x20222222;
409 val |= LNKW_X8 << 12;
411 val |= LNKW_X4 << 12;
413 SDR_WRITE(SDRN_PESDR_DLPSET(port), val);
414 SDR_WRITE(SDRN_PESDR_UTLSET1(port), utlset1);
415 if (!ppc440spe_revB())
416 SDR_WRITE(SDRN_PESDR_UTLSET2(port), 0x11000000);
417 SDR_WRITE(SDRN_PESDR_HSSL0SET1(port), 0x35000000);
418 SDR_WRITE(SDRN_PESDR_HSSL1SET1(port), 0x35000000);
419 SDR_WRITE(SDRN_PESDR_HSSL2SET1(port), 0x35000000);
420 SDR_WRITE(SDRN_PESDR_HSSL3SET1(port), 0x35000000);
422 SDR_WRITE(PESDR0_HSSL4SET1, 0x35000000);
423 SDR_WRITE(PESDR0_HSSL5SET1, 0x35000000);
424 SDR_WRITE(PESDR0_HSSL6SET1, 0x35000000);
425 SDR_WRITE(PESDR0_HSSL7SET1, 0x35000000);
427 SDR_WRITE(SDRN_PESDR_RCSSET(port), (SDR_READ(SDRN_PESDR_RCSSET(port)) &
428 ~(1 << 24 | 1 << 16)) | 1 << 12);
432 #endif /* CONFIG_440SPE */
434 #if defined(CONFIG_405EX)
435 int __ppc4xx_init_pcie_port_hw(int port, int rootport)
441 * This needs some testing and perhaps changes for
442 * endpoint configuration. Probably no PHY reset at all, etc.
450 SDR_WRITE(SDRN_PESDR_DLPSET(port), val);
451 SDR_WRITE(SDRN_PESDR_UTLSET1(port), 0x20222222);
452 SDR_WRITE(SDRN_PESDR_UTLSET2(port), 0x01110000);
453 SDR_WRITE(SDRN_PESDR_PHYSET1(port), 0x720F0000);
454 SDR_WRITE(SDRN_PESDR_PHYSET2(port), 0x70600003);
456 /* Assert the PE0_PHY reset */
457 SDR_WRITE(SDRN_PESDR_RCSSET(port), 0x01010000);
460 /* deassert the PE0_hotreset */
461 SDR_WRITE(SDRN_PESDR_RCSSET(port), 0x01101000);
463 /* poll for phy !reset */
464 while (!(SDR_READ(SDRN_PESDR_PHYSTA(port)) & 0x00001000))
467 /* deassert the PE0_gpl_utl_reset */
468 SDR_WRITE(SDRN_PESDR_RCSSET(port), 0x00101000);
471 mtdcr(DCRN_PEGPL_CFG(PCIE0), 0x10000000); /* guarded on */
473 mtdcr(DCRN_PEGPL_CFG(PCIE1), 0x10000000); /* guarded on */
477 #endif /* CONFIG_405EX */
479 int ppc4xx_init_pcie_port_hw(int port, int rootport)
480 __attribute__((weak, alias("__ppc4xx_init_pcie_port_hw")));
483 * We map PCI Express configuration access into the 512MB regions
485 * NOTICE: revB is very strict about PLB real addressess and ranges to
486 * be mapped for config space; it seems to only work with d_nnnn_nnnn
487 * range (hangs the core upon config transaction attempts when set
488 * otherwise) while revA uses c_nnnn_nnnn.
491 * PCIE0: 0xc_4000_0000
492 * PCIE1: 0xc_8000_0000
493 * PCIE2: 0xc_c000_0000
496 * PCIE0: 0xd_0000_0000
497 * PCIE1: 0xd_2000_0000
498 * PCIE2: 0xd_4000_0000
504 static inline u64 ppc4xx_get_cfgaddr(int port)
506 #if defined(CONFIG_405EX)
508 return (u64)CFG_PCIE0_CFGBASE;
510 return (u64)CFG_PCIE1_CFGBASE;
512 #if defined(CONFIG_440SPE)
513 if (ppc440spe_revB()) {
515 default: /* to satisfy compiler */
517 return 0x0000000d00000000ULL;
519 return 0x0000000d20000000ULL;
521 return 0x0000000d40000000ULL;
525 default: /* to satisfy compiler */
527 return 0x0000000c40000000ULL;
529 return 0x0000000c80000000ULL;
531 return 0x0000000cc0000000ULL;
538 * 4xx boards as end point and root point setup
540 * testing inbound and out bound windows
542 * 4xx boards can be plugged into another 4xx boards or you can get PCI-E
543 * cable which can be used to setup loop back from one port to another port.
544 * Please rememeber that unless there is a endpoint plugged in to root port it
545 * will not initialize. It is the same in case of endpoint , unless there is
546 * root port attached it will not initialize.
548 * In this release of software all the PCI-E ports are configured as either
549 * endpoint or rootpoint.In future we will have support for selective ports
550 * setup as endpoint and root point in single board.
552 * Once your board came up as root point , you can verify by reading
553 * /proc/bus/pci/devices. Where you can see the configuration registers
554 * of end point device attached to the port.
556 * Enpoint cofiguration can be verified by connecting 4xx board to any
557 * host or another 4xx board. Then try to scan the device. In case of
558 * linux use "lspci" or appripriate os command.
560 * How do I verify the inbound and out bound windows ? (4xx to 4xx)
561 * in this configuration inbound and outbound windows are setup to access
562 * sram memroy area. SRAM is at 0x4 0000 0000 , on PLB bus. This address
563 * is mapped at 0x90000000. From u-boot prompt write data 0xb000 0000,
564 * This is waere your POM(PLB out bound memory window) mapped. then
565 * read the data from other 4xx board's u-boot prompt at address
566 * 0x9000 0000(SRAM). Data should match.
567 * In case of inbound , write data to u-boot command prompt at 0xb000 0000
568 * which is mapped to 0x4 0000 0000. Now on rootpoint yucca u-boot prompt check
569 * data at 0x9000 0000(SRAM).Data should match.
571 int ppc4xx_init_pcie_port(int port, int rootport)
573 static int core_init;
574 volatile u32 val = 0;
581 if (ppc4xx_init_pcie())
586 * Initialize various parts of the PCI Express core for our port
588 ppc4xx_init_pcie_port_hw(port, rootport);
591 * Notice: the following delay has critical impact on device
592 * initialization - if too short (<50ms) the link doesn't get up.
596 val = SDR_READ(SDRN_PESDR_RCSSTS(port));
597 if (val & (1 << 20)) {
598 printf("PCIE%d: PGRST failed %08x\n", port, val);
605 val = SDR_READ(SDRN_PESDR_LOOP(port));
606 if (!(val & 0x00001000)) {
607 printf("PCIE%d: link is not up.\n", port);
612 * Setup UTL registers - but only on revA!
613 * We use default settings for revB chip.
615 if (!ppc440spe_revB())
616 ppc4xx_setup_utl(port);
619 * We map PCI Express configuration access into the 512MB regions
621 addr = ppc4xx_get_cfgaddr(port);
622 low = (u32)(addr & 0x00000000ffffffff);
623 high = (u32)(addr >> 32);
627 mtdcr(DCRN_PEGPL_CFGBAH(PCIE0), high);
628 mtdcr(DCRN_PEGPL_CFGBAL(PCIE0), low);
629 mtdcr(DCRN_PEGPL_CFGMSK(PCIE0), 0xe0000001); /* 512MB region, valid */
632 mtdcr(DCRN_PEGPL_CFGBAH(PCIE1), high);
633 mtdcr(DCRN_PEGPL_CFGBAL(PCIE1), low);
634 mtdcr(DCRN_PEGPL_CFGMSK(PCIE1), 0xe0000001); /* 512MB region, valid */
637 mtdcr(DCRN_PEGPL_CFGBAH(PCIE2), high);
638 mtdcr(DCRN_PEGPL_CFGBAL(PCIE2), low);
639 mtdcr(DCRN_PEGPL_CFGMSK(PCIE2), 0xe0000001); /* 512MB region, valid */
644 * Check for VC0 active and assert RDY.
647 while(!(SDR_READ(SDRN_PESDR_RCSSTS(port)) & (1 << 16))) {
649 printf("PCIE%d: VC0 not active\n", port);
654 SDR_WRITE(SDRN_PESDR_RCSSET(port),
655 SDR_READ(SDRN_PESDR_RCSSET(port)) | 1 << 20);
661 int ppc4xx_init_pcie_rootport(int port)
663 return ppc4xx_init_pcie_port(port, 1);
666 int ppc4xx_init_pcie_endport(int port)
668 return ppc4xx_init_pcie_port(port, 0);
671 void ppc4xx_setup_pcie_rootpoint(struct pci_controller *hose, int port)
673 volatile void *mbase = NULL;
674 volatile void *rmbase = NULL;
677 pcie_read_config_byte,
678 pcie_read_config_word,
679 pcie_read_config_dword,
680 pcie_write_config_byte,
681 pcie_write_config_word,
682 pcie_write_config_dword);
686 mbase = (u32 *)CFG_PCIE0_XCFGBASE;
687 rmbase = (u32 *)CFG_PCIE0_CFGBASE;
688 hose->cfg_data = (u8 *)CFG_PCIE0_CFGBASE;
691 mbase = (u32 *)CFG_PCIE1_XCFGBASE;
692 rmbase = (u32 *)CFG_PCIE1_CFGBASE;
693 hose->cfg_data = (u8 *)CFG_PCIE1_CFGBASE;
696 mbase = (u32 *)CFG_PCIE2_XCFGBASE;
697 rmbase = (u32 *)CFG_PCIE2_CFGBASE;
698 hose->cfg_data = (u8 *)CFG_PCIE2_CFGBASE;
703 * Set bus numbers on our root port
705 out_8((u8 *)mbase + PCI_PRIMARY_BUS, 0);
706 out_8((u8 *)mbase + PCI_SECONDARY_BUS, 1);
707 out_8((u8 *)mbase + PCI_SUBORDINATE_BUS, 1);
710 * Set up outbound translation to hose->mem_space from PLB
711 * addresses at an offset of 0xd_0000_0000. We set the low
712 * bits of the mask to 11 to turn off splitting into 8
713 * subregions and to enable the outbound translation.
715 out_le32(mbase + PECFG_POM0LAH, 0x00000000);
716 out_le32(mbase + PECFG_POM0LAL, CFG_PCIE_MEMBASE +
717 port * CFG_PCIE_MEMSIZE);
718 debug("PECFG_POM0LA=%08x.%08x\n", in_le32(mbase + PECFG_POM0LAH),
719 in_le32(mbase + PECFG_POM0LAL));
723 mtdcr(DCRN_PEGPL_OMR1BAH(PCIE0), 0x0000000d);
724 mtdcr(DCRN_PEGPL_OMR1BAL(PCIE0), CFG_PCIE_MEMBASE +
725 port * CFG_PCIE_MEMSIZE);
726 mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE0), 0x7fffffff);
727 mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE0),
728 ~(CFG_PCIE_MEMSIZE - 1) | 3);
729 debug("0:PEGPL_OMR1BA=%08x.%08x MSK=%08x.%08x\n",
730 mfdcr(DCRN_PEGPL_OMR1BAH(PCIE0)),
731 mfdcr(DCRN_PEGPL_OMR1BAL(PCIE0)),
732 mfdcr(DCRN_PEGPL_OMR1MSKH(PCIE0)),
733 mfdcr(DCRN_PEGPL_OMR1MSKL(PCIE0)));
736 mtdcr(DCRN_PEGPL_OMR1BAH(PCIE1), 0x0000000d);
737 mtdcr(DCRN_PEGPL_OMR1BAL(PCIE1), CFG_PCIE_MEMBASE +
738 port * CFG_PCIE_MEMSIZE);
739 mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE1), 0x7fffffff);
740 mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE1),
741 ~(CFG_PCIE_MEMSIZE - 1) | 3);
742 debug("1:PEGPL_OMR1BA=%08x.%08x MSK=%08x.%08x\n",
743 mfdcr(DCRN_PEGPL_OMR1BAH(PCIE1)),
744 mfdcr(DCRN_PEGPL_OMR1BAL(PCIE1)),
745 mfdcr(DCRN_PEGPL_OMR1MSKH(PCIE1)),
746 mfdcr(DCRN_PEGPL_OMR1MSKL(PCIE1)));
749 mtdcr(DCRN_PEGPL_OMR1BAH(PCIE2), 0x0000000d);
750 mtdcr(DCRN_PEGPL_OMR1BAL(PCIE2), CFG_PCIE_MEMBASE +
751 port * CFG_PCIE_MEMSIZE);
752 mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE2), 0x7fffffff);
753 mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE2),
754 ~(CFG_PCIE_MEMSIZE - 1) | 3);
755 debug("2:PEGPL_OMR1BA=%08x.%08x MSK=%08x.%08x\n",
756 mfdcr(DCRN_PEGPL_OMR1BAH(PCIE2)),
757 mfdcr(DCRN_PEGPL_OMR1BAL(PCIE2)),
758 mfdcr(DCRN_PEGPL_OMR1MSKH(PCIE2)),
759 mfdcr(DCRN_PEGPL_OMR1MSKL(PCIE2)));
763 /* Set up 16GB inbound memory window at 0 */
764 out_le32(mbase + PCI_BASE_ADDRESS_0, 0);
765 out_le32(mbase + PCI_BASE_ADDRESS_1, 0);
766 out_le32(mbase + PECFG_BAR0HMPA, 0x7fffffc);
767 out_le32(mbase + PECFG_BAR0LMPA, 0);
769 out_le32(mbase + PECFG_PIM01SAH, 0xffff0000);
770 out_le32(mbase + PECFG_PIM01SAL, 0x00000000);
771 out_le32(mbase + PECFG_PIM0LAL, 0);
772 out_le32(mbase + PECFG_PIM0LAH, 0);
773 out_le32(mbase + PECFG_PIM1LAL, 0x00000000);
774 out_le32(mbase + PECFG_PIM1LAH, 0x00000004);
775 out_le32(mbase + PECFG_PIMEN, 0x1);
777 /* Enable I/O, Mem, and Busmaster cycles */
778 out_le16((u16 *)(mbase + PCI_COMMAND),
779 in_le16((u16 *)(mbase + PCI_COMMAND)) |
780 PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
782 /* Set Device and Vendor Id */
785 out_le16(mbase + 0x200, 0xaaa0);
786 out_le16(mbase + 0x202, 0xbed0);
789 out_le16(mbase + 0x200, 0xaaa1);
790 out_le16(mbase + 0x202, 0xbed1);
793 out_le16(mbase + 0x200, 0xaaa2);
794 out_le16(mbase + 0x202, 0xbed2);
797 out_le16(mbase + 0x200, 0xaaa3);
798 out_le16(mbase + 0x202, 0xbed3);
801 /* Set Class Code to PCI-PCI bridge and Revision Id to 1 */
802 out_le32(mbase + 0x208, 0x06040001);
804 printf("PCIE:%d successfully set as rootpoint\n", port);
807 int ppc4xx_setup_pcie_endpoint(struct pci_controller *hose, int port)
809 volatile void *mbase = NULL;
813 pcie_read_config_byte,
814 pcie_read_config_word,
815 pcie_read_config_dword,
816 pcie_write_config_byte,
817 pcie_write_config_word,
818 pcie_write_config_dword);
822 mbase = (u32 *)CFG_PCIE0_XCFGBASE;
823 hose->cfg_data = (u8 *)CFG_PCIE0_CFGBASE;
826 mbase = (u32 *)CFG_PCIE1_XCFGBASE;
827 hose->cfg_data = (u8 *)CFG_PCIE1_CFGBASE;
830 mbase = (u32 *)CFG_PCIE2_XCFGBASE;
831 hose->cfg_data = (u8 *)CFG_PCIE2_CFGBASE;
836 * Set up outbound translation to hose->mem_space from PLB
837 * addresses at an offset of 0xd_0000_0000. We set the low
838 * bits of the mask to 11 to turn off splitting into 8
839 * subregions and to enable the outbound translation.
841 out_le32(mbase + PECFG_POM0LAH, 0x00001ff8);
842 out_le32(mbase + PECFG_POM0LAL, 0x00001000);
846 mtdcr(DCRN_PEGPL_OMR1BAH(PCIE0), 0x0000000d);
847 mtdcr(DCRN_PEGPL_OMR1BAL(PCIE0), CFG_PCIE_MEMBASE +
848 port * CFG_PCIE_MEMSIZE);
849 mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE0), 0x7fffffff);
850 mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE0),
851 ~(CFG_PCIE_MEMSIZE - 1) | 3);
854 mtdcr(DCRN_PEGPL_OMR1BAH(PCIE1), 0x0000000d);
855 mtdcr(DCRN_PEGPL_OMR1BAL(PCIE1), CFG_PCIE_MEMBASE +
856 port * CFG_PCIE_MEMSIZE);
857 mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE1), 0x7fffffff);
858 mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE1),
859 ~(CFG_PCIE_MEMSIZE - 1) | 3);
862 mtdcr(DCRN_PEGPL_OMR1BAH(PCIE2), 0x0000000d);
863 mtdcr(DCRN_PEGPL_OMR1BAL(PCIE2), CFG_PCIE_MEMBASE +
864 port * CFG_PCIE_MEMSIZE);
865 mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE2), 0x7fffffff);
866 mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE2),
867 ~(CFG_PCIE_MEMSIZE - 1) | 3);
871 /* Set up 16GB inbound memory window at 0 */
872 out_le32(mbase + PCI_BASE_ADDRESS_0, 0);
873 out_le32(mbase + PCI_BASE_ADDRESS_1, 0);
874 out_le32(mbase + PECFG_BAR0HMPA, 0x7fffffc);
875 out_le32(mbase + PECFG_BAR0LMPA, 0);
876 out_le32(mbase + PECFG_PIM0LAL, 0x00000000);
877 out_le32(mbase + PECFG_PIM0LAH, 0x00000004); /* pointing to SRAM */
878 out_le32(mbase + PECFG_PIMEN, 0x1);
880 /* Enable I/O, Mem, and Busmaster cycles */
881 out_le16((u16 *)(mbase + PCI_COMMAND),
882 in_le16((u16 *)(mbase + PCI_COMMAND)) |
883 PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
884 out_le16(mbase + 0x200,0xcaad); /* Setting vendor ID */
885 out_le16(mbase + 0x202,0xfeed); /* Setting device ID */
888 while(!(SDR_READ(SDRN_PESDR_RCSSTS(port)) & (1 << 8))) {
890 printf("PCIE%d: BME not active\n", port);
896 printf("PCIE:%d successfully set as endpoint\n",port);
900 #endif /* CONFIG_440SPE && CONFIG_PCI */