2 * (C) Copyright 2006 - 2007
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * Copyright (c) 2005 Cisco Systems. All rights reserved.
6 * Roland Dreier <rolandd@cisco.com>
8 * See file CREDITS for list of people who contributed to this
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
23 /* define DEBUG for debugging output (obviously ;-)) */
28 #include <asm/processor.h>
29 #include <asm-ppc/io.h>
34 #if (defined(CONFIG_440SPE) || defined(CONFIG_405EX)) && \
37 #include <asm/4xx_pcie.h>
41 PTYPE_LEGACY_ENDPOINT = 0x1,
42 PTYPE_ROOT_PORT = 0x4,
49 static u8* pcie_get_base(struct pci_controller *hose, unsigned int devfn)
51 u8 *base = (u8*)hose->cfg_data;
53 /* use local configuration space for the first bus */
54 if (PCI_BUS(devfn) == 0) {
55 if (hose->cfg_data == (u8*)CFG_PCIE0_CFGBASE)
56 base = (u8*)CFG_PCIE0_XCFGBASE;
57 if (hose->cfg_data == (u8*)CFG_PCIE1_CFGBASE)
58 base = (u8*)CFG_PCIE1_XCFGBASE;
59 #if CFG_PCIE_NR_PORTS > 2
60 if (hose->cfg_data == (u8*)CFG_PCIE2_CFGBASE)
61 base = (u8*)CFG_PCIE2_XCFGBASE;
68 static void pcie_dmer_disable(void)
70 mtdcr (DCRN_PEGPL_CFG(DCRN_PCIE0_BASE),
71 mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE0_BASE)) | GPL_DMER_MASK_DISA);
72 mtdcr (DCRN_PEGPL_CFG(DCRN_PCIE1_BASE),
73 mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE1_BASE)) | GPL_DMER_MASK_DISA);
74 #if CFG_PCIE_NR_PORTS > 2
75 mtdcr (DCRN_PEGPL_CFG(DCRN_PCIE2_BASE),
76 mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE2_BASE)) | GPL_DMER_MASK_DISA);
80 static void pcie_dmer_enable(void)
82 mtdcr (DCRN_PEGPL_CFG (DCRN_PCIE0_BASE),
83 mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE0_BASE)) & ~GPL_DMER_MASK_DISA);
84 mtdcr (DCRN_PEGPL_CFG (DCRN_PCIE1_BASE),
85 mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE1_BASE)) & ~GPL_DMER_MASK_DISA);
86 #if CFG_PCIE_NR_PORTS > 2
87 mtdcr (DCRN_PEGPL_CFG (DCRN_PCIE2_BASE),
88 mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE2_BASE)) & ~GPL_DMER_MASK_DISA);
92 static int pcie_read_config(struct pci_controller *hose, unsigned int devfn,
93 int offset, int len, u32 *val) {
99 * Bus numbers are relative to hose->first_busno
101 devfn -= PCI_BDF(hose->first_busno, 0, 0);
104 * NOTICE: configuration space ranges are currenlty mapped only for
105 * the first 16 buses, so such limit must be imposed. In case more
106 * buses are required the TLB settings in board/amcc/<board>/init.S
107 * need to be altered accordingly (one bus takes 1 MB of memory space).
109 if (PCI_BUS(devfn) >= 16)
113 * Only single device/single function is supported for the primary and
114 * secondary buses of the 440SPe host bridge.
116 if ((!((PCI_FUNC(devfn) == 0) && (PCI_DEV(devfn) == 0))) &&
117 ((PCI_BUS(devfn) == 0) || (PCI_BUS(devfn) == 1)))
120 address = pcie_get_base(hose, devfn);
121 offset += devfn << 4;
124 * Reading from configuration space of non-existing device can
125 * generate transaction errors. For the read duration we suppress
126 * assertion of machine check exceptions to avoid those.
128 pcie_dmer_disable ();
130 debug("%s: cfg_data=%08x offset=%08x\n", __func__, hose->cfg_data, offset);
133 *val = in_8(hose->cfg_data + offset);
136 *val = in_le16((u16 *)(hose->cfg_data + offset));
139 *val = in_le32((u32*)(hose->cfg_data + offset));
148 static int pcie_write_config(struct pci_controller *hose, unsigned int devfn,
149 int offset, int len, u32 val) {
154 * Bus numbers are relative to hose->first_busno
156 devfn -= PCI_BDF(hose->first_busno, 0, 0);
159 * Same constraints as in pcie_read_config().
161 if (PCI_BUS(devfn) >= 16)
164 if ((!((PCI_FUNC(devfn) == 0) && (PCI_DEV(devfn) == 0))) &&
165 ((PCI_BUS(devfn) == 0) || (PCI_BUS(devfn) == 1)))
168 address = pcie_get_base(hose, devfn);
169 offset += devfn << 4;
172 * Suppress MCK exceptions, similar to pcie_read_config()
174 pcie_dmer_disable ();
178 out_8(hose->cfg_data + offset, val);
181 out_le16((u16 *)(hose->cfg_data + offset), val);
184 out_le32((u32 *)(hose->cfg_data + offset), val);
193 int pcie_read_config_byte(struct pci_controller *hose,pci_dev_t dev,int offset,u8 *val)
198 rv = pcie_read_config(hose, dev, offset, 1, &v);
203 int pcie_read_config_word(struct pci_controller *hose,pci_dev_t dev,int offset,u16 *val)
208 rv = pcie_read_config(hose, dev, offset, 2, &v);
213 int pcie_read_config_dword(struct pci_controller *hose,pci_dev_t dev,int offset,u32 *val)
218 rv = pcie_read_config(hose, dev, offset, 3, &v);
223 int pcie_write_config_byte(struct pci_controller *hose,pci_dev_t dev,int offset,u8 val)
225 return pcie_write_config(hose,(u32)dev,offset,1,val);
228 int pcie_write_config_word(struct pci_controller *hose,pci_dev_t dev,int offset,u16 val)
230 return pcie_write_config(hose,(u32)dev,offset,2,(u32 )val);
233 int pcie_write_config_dword(struct pci_controller *hose,pci_dev_t dev,int offset,u32 val)
235 return pcie_write_config(hose,(u32)dev,offset,3,(u32 )val);
238 #if defined(CONFIG_440SPE)
239 static void ppc4xx_setup_utl(u32 port) {
241 volatile void *utl_base = NULL;
248 mtdcr(DCRN_PEGPL_REGBAH(PCIE0), 0x0000000c);
249 mtdcr(DCRN_PEGPL_REGBAL(PCIE0), 0x20000000);
250 mtdcr(DCRN_PEGPL_REGMSK(PCIE0), 0x00007001);
251 mtdcr(DCRN_PEGPL_SPECIAL(PCIE0), 0x68782800);
255 mtdcr(DCRN_PEGPL_REGBAH(PCIE1), 0x0000000c);
256 mtdcr(DCRN_PEGPL_REGBAL(PCIE1), 0x20001000);
257 mtdcr(DCRN_PEGPL_REGMSK(PCIE1), 0x00007001);
258 mtdcr(DCRN_PEGPL_SPECIAL(PCIE1), 0x68782800);
262 mtdcr(DCRN_PEGPL_REGBAH(PCIE2), 0x0000000c);
263 mtdcr(DCRN_PEGPL_REGBAL(PCIE2), 0x20002000);
264 mtdcr(DCRN_PEGPL_REGMSK(PCIE2), 0x00007001);
265 mtdcr(DCRN_PEGPL_SPECIAL(PCIE2), 0x68782800);
268 utl_base = (unsigned int *)(CFG_PCIE_BASE + 0x1000 * port);
271 * Set buffer allocations and then assert VRB and TXE.
273 out_be32(utl_base + PEUTL_OUTTR, 0x08000000);
274 out_be32(utl_base + PEUTL_INTR, 0x02000000);
275 out_be32(utl_base + PEUTL_OPDBSZ, 0x10000000);
276 out_be32(utl_base + PEUTL_PBBSZ, 0x53000000);
277 out_be32(utl_base + PEUTL_IPHBSZ, 0x08000000);
278 out_be32(utl_base + PEUTL_IPDBSZ, 0x10000000);
279 out_be32(utl_base + PEUTL_RCIRQEN, 0x00f00000);
280 out_be32(utl_base + PEUTL_PCTL, 0x80800066);
283 static int check_error(void)
285 u32 valPE0, valPE1, valPE2;
288 /* SDR0_PEGPLLLCT1 reset */
289 if (!(valPE0 = SDR_READ(PESDR0_PLLLCT1) & 0x01000000)) {
290 printf("PCIE: SDR0_PEGPLLLCT1 reset error 0x%x\n", valPE0);
293 valPE0 = SDR_READ(PESDR0_RCSSET);
294 valPE1 = SDR_READ(PESDR1_RCSSET);
295 valPE2 = SDR_READ(PESDR2_RCSSET);
297 /* SDR0_PExRCSSET rstgu */
298 if (!(valPE0 & 0x01000000) ||
299 !(valPE1 & 0x01000000) ||
300 !(valPE2 & 0x01000000)) {
301 printf("PCIE: SDR0_PExRCSSET rstgu error\n");
305 /* SDR0_PExRCSSET rstdl */
306 if (!(valPE0 & 0x00010000) ||
307 !(valPE1 & 0x00010000) ||
308 !(valPE2 & 0x00010000)) {
309 printf("PCIE: SDR0_PExRCSSET rstdl error\n");
313 /* SDR0_PExRCSSET rstpyn */
314 if ((valPE0 & 0x00001000) ||
315 (valPE1 & 0x00001000) ||
316 (valPE2 & 0x00001000)) {
317 printf("PCIE: SDR0_PExRCSSET rstpyn error\n");
321 /* SDR0_PExRCSSET hldplb */
322 if ((valPE0 & 0x10000000) ||
323 (valPE1 & 0x10000000) ||
324 (valPE2 & 0x10000000)) {
325 printf("PCIE: SDR0_PExRCSSET hldplb error\n");
329 /* SDR0_PExRCSSET rdy */
330 if ((valPE0 & 0x00100000) ||
331 (valPE1 & 0x00100000) ||
332 (valPE2 & 0x00100000)) {
333 printf("PCIE: SDR0_PExRCSSET rdy error\n");
337 /* SDR0_PExRCSSET shutdown */
338 if ((valPE0 & 0x00000100) ||
339 (valPE1 & 0x00000100) ||
340 (valPE2 & 0x00000100)) {
341 printf("PCIE: SDR0_PExRCSSET shutdown error\n");
348 * Initialize PCI Express core
350 int ppc4xx_init_pcie(void)
354 /* Set PLL clock receiver to LVPECL */
355 SDR_WRITE(PESDR0_PLLLCT1, SDR_READ(PESDR0_PLLLCT1) | 1 << 28);
360 if (!(SDR_READ(PESDR0_PLLLCT2) & 0x10000))
362 printf("PCIE: PESDR_PLLCT2 resistance calibration failed (0x%08x)\n",
363 SDR_READ(PESDR0_PLLLCT2));
366 /* De-assert reset of PCIe PLL, wait for lock */
367 SDR_WRITE(PESDR0_PLLLCT1, SDR_READ(PESDR0_PLLLCT1) & ~(1 << 24));
371 if (!(SDR_READ(PESDR0_PLLLCT3) & 0x10000000)) {
378 printf("PCIE: VCO output not locked\n");
384 int ppc4xx_init_pcie(void)
387 * Nothing to do on 405EX
394 * Board-specific pcie initialization
395 * Platform code can reimplement ppc4xx_init_pcie_port_hw() if needed
399 * Initialize various parts of the PCI Express core for our port:
401 * - Set as a root port and enable max width
402 * (PXIE0 -> X8, PCIE1 and PCIE2 -> X4).
403 * - Set up UTL configuration.
404 * - Increase SERDES drive strength to levels suggested by AMCC.
405 * - De-assert RSTPYN, RSTDL and RSTGU.
407 * NOTICE for 440SPE revB chip: PESDRn_UTLSET2 is not set - we leave it
408 * with default setting 0x11310000. The register has new fields,
409 * PESDRn_UTLSET2[LKINE] in particular: clearing it leads to PCIE core
412 #if defined(CONFIG_440SPE)
413 int __ppc4xx_init_pcie_port_hw(int port, int rootport)
419 val = PTYPE_ROOT_PORT << 20;
420 utlset1 = 0x21222222;
422 val = PTYPE_LEGACY_ENDPOINT << 20;
423 utlset1 = 0x20222222;
427 val |= LNKW_X8 << 12;
429 val |= LNKW_X4 << 12;
431 SDR_WRITE(SDRN_PESDR_DLPSET(port), val);
432 SDR_WRITE(SDRN_PESDR_UTLSET1(port), utlset1);
433 if (!ppc440spe_revB())
434 SDR_WRITE(SDRN_PESDR_UTLSET2(port), 0x11000000);
435 SDR_WRITE(SDRN_PESDR_HSSL0SET1(port), 0x35000000);
436 SDR_WRITE(SDRN_PESDR_HSSL1SET1(port), 0x35000000);
437 SDR_WRITE(SDRN_PESDR_HSSL2SET1(port), 0x35000000);
438 SDR_WRITE(SDRN_PESDR_HSSL3SET1(port), 0x35000000);
440 SDR_WRITE(PESDR0_HSSL4SET1, 0x35000000);
441 SDR_WRITE(PESDR0_HSSL5SET1, 0x35000000);
442 SDR_WRITE(PESDR0_HSSL6SET1, 0x35000000);
443 SDR_WRITE(PESDR0_HSSL7SET1, 0x35000000);
445 SDR_WRITE(SDRN_PESDR_RCSSET(port), (SDR_READ(SDRN_PESDR_RCSSET(port)) &
446 ~(1 << 24 | 1 << 16)) | 1 << 12);
450 #endif /* CONFIG_440SPE */
452 #if defined(CONFIG_405EX)
453 int __ppc4xx_init_pcie_port_hw(int port, int rootport)
459 * This needs some testing and perhaps changes for
460 * endpoint configuration. Probably no PHY reset at all, etc.
468 SDR_WRITE(SDRN_PESDR_DLPSET(port), val);
469 SDR_WRITE(SDRN_PESDR_UTLSET1(port), 0x20222222);
470 SDR_WRITE(SDRN_PESDR_UTLSET2(port), 0x01110000);
471 SDR_WRITE(SDRN_PESDR_PHYSET1(port), 0x720F0000);
472 SDR_WRITE(SDRN_PESDR_PHYSET2(port), 0x70600003);
474 /* Assert the PE0_PHY reset */
475 SDR_WRITE(SDRN_PESDR_RCSSET(port), 0x01010000);
478 /* deassert the PE0_hotreset */
479 SDR_WRITE(SDRN_PESDR_RCSSET(port), 0x01101000);
481 /* poll for phy !reset */
482 while (!(SDR_READ(SDRN_PESDR_PHYSTA(port)) & 0x00001000))
485 /* deassert the PE0_gpl_utl_reset */
486 SDR_WRITE(SDRN_PESDR_RCSSET(port), 0x00101000);
489 mtdcr(DCRN_PEGPL_CFG(PCIE0), 0x10000000); /* guarded on */
491 mtdcr(DCRN_PEGPL_CFG(PCIE1), 0x10000000); /* guarded on */
495 #endif /* CONFIG_405EX */
497 int ppc4xx_init_pcie_port_hw(int port, int rootport)
498 __attribute__((weak, alias("__ppc4xx_init_pcie_port_hw")));
501 * We map PCI Express configuration access into the 512MB regions
503 * NOTICE: revB is very strict about PLB real addressess and ranges to
504 * be mapped for config space; it seems to only work with d_nnnn_nnnn
505 * range (hangs the core upon config transaction attempts when set
506 * otherwise) while revA uses c_nnnn_nnnn.
509 * PCIE0: 0xc_4000_0000
510 * PCIE1: 0xc_8000_0000
511 * PCIE2: 0xc_c000_0000
514 * PCIE0: 0xd_0000_0000
515 * PCIE1: 0xd_2000_0000
516 * PCIE2: 0xd_4000_0000
522 static inline u64 ppc4xx_get_cfgaddr(int port)
524 #if defined(CONFIG_405EX)
526 return (u64)CFG_PCIE0_CFGBASE;
528 return (u64)CFG_PCIE1_CFGBASE;
530 #if defined(CONFIG_440SPE)
531 if (ppc440spe_revB()) {
533 default: /* to satisfy compiler */
535 return 0x0000000d00000000ULL;
537 return 0x0000000d20000000ULL;
539 return 0x0000000d40000000ULL;
543 default: /* to satisfy compiler */
545 return 0x0000000c40000000ULL;
547 return 0x0000000c80000000ULL;
549 return 0x0000000cc0000000ULL;
556 * 4xx boards as end point and root point setup
558 * testing inbound and out bound windows
560 * 4xx boards can be plugged into another 4xx boards or you can get PCI-E
561 * cable which can be used to setup loop back from one port to another port.
562 * Please rememeber that unless there is a endpoint plugged in to root port it
563 * will not initialize. It is the same in case of endpoint , unless there is
564 * root port attached it will not initialize.
566 * In this release of software all the PCI-E ports are configured as either
567 * endpoint or rootpoint.In future we will have support for selective ports
568 * setup as endpoint and root point in single board.
570 * Once your board came up as root point , you can verify by reading
571 * /proc/bus/pci/devices. Where you can see the configuration registers
572 * of end point device attached to the port.
574 * Enpoint cofiguration can be verified by connecting 4xx board to any
575 * host or another 4xx board. Then try to scan the device. In case of
576 * linux use "lspci" or appripriate os command.
578 * How do I verify the inbound and out bound windows ? (4xx to 4xx)
579 * in this configuration inbound and outbound windows are setup to access
580 * sram memroy area. SRAM is at 0x4 0000 0000 , on PLB bus. This address
581 * is mapped at 0x90000000. From u-boot prompt write data 0xb000 0000,
582 * This is waere your POM(PLB out bound memory window) mapped. then
583 * read the data from other 4xx board's u-boot prompt at address
584 * 0x9000 0000(SRAM). Data should match.
585 * In case of inbound , write data to u-boot command prompt at 0xb000 0000
586 * which is mapped to 0x4 0000 0000. Now on rootpoint yucca u-boot prompt check
587 * data at 0x9000 0000(SRAM).Data should match.
589 int ppc4xx_init_pcie_port(int port, int rootport)
591 static int core_init;
592 volatile u32 val = 0;
599 if (ppc4xx_init_pcie())
604 * Initialize various parts of the PCI Express core for our port
606 ppc4xx_init_pcie_port_hw(port, rootport);
609 * Notice: the following delay has critical impact on device
610 * initialization - if too short (<50ms) the link doesn't get up.
614 val = SDR_READ(SDRN_PESDR_RCSSTS(port));
615 if (val & (1 << 20)) {
616 printf("PCIE%d: PGRST failed %08x\n", port, val);
623 val = SDR_READ(SDRN_PESDR_LOOP(port));
624 if (!(val & 0x00001000)) {
625 printf("PCIE%d: link is not up.\n", port);
629 #if defined(CONFIG_440SPE)
631 * Setup UTL registers - but only on revA!
632 * We use default settings for revB chip.
634 if (!ppc440spe_revB())
635 ppc4xx_setup_utl(port);
639 * We map PCI Express configuration access into the 512MB regions
641 addr = ppc4xx_get_cfgaddr(port);
642 low = U64_TO_U32_LOW(addr);
643 high = U64_TO_U32_HIGH(addr);
647 mtdcr(DCRN_PEGPL_CFGBAH(PCIE0), high);
648 mtdcr(DCRN_PEGPL_CFGBAL(PCIE0), low);
649 mtdcr(DCRN_PEGPL_CFGMSK(PCIE0), 0xe0000001); /* 512MB region, valid */
652 mtdcr(DCRN_PEGPL_CFGBAH(PCIE1), high);
653 mtdcr(DCRN_PEGPL_CFGBAL(PCIE1), low);
654 mtdcr(DCRN_PEGPL_CFGMSK(PCIE1), 0xe0000001); /* 512MB region, valid */
656 #if CFG_PCIE_NR_PORTS > 2
658 mtdcr(DCRN_PEGPL_CFGBAH(PCIE2), high);
659 mtdcr(DCRN_PEGPL_CFGBAL(PCIE2), low);
660 mtdcr(DCRN_PEGPL_CFGMSK(PCIE2), 0xe0000001); /* 512MB region, valid */
666 * Check for VC0 active and assert RDY.
669 while(!(SDR_READ(SDRN_PESDR_RCSSTS(port)) & (1 << 16))) {
671 printf("PCIE%d: VC0 not active\n", port);
676 SDR_WRITE(SDRN_PESDR_RCSSET(port),
677 SDR_READ(SDRN_PESDR_RCSSET(port)) | 1 << 20);
683 int ppc4xx_init_pcie_rootport(int port)
685 return ppc4xx_init_pcie_port(port, 1);
688 int ppc4xx_init_pcie_endport(int port)
690 return ppc4xx_init_pcie_port(port, 0);
693 void ppc4xx_setup_pcie_rootpoint(struct pci_controller *hose, int port)
695 volatile void *mbase = NULL;
696 volatile void *rmbase = NULL;
699 pcie_read_config_byte,
700 pcie_read_config_word,
701 pcie_read_config_dword,
702 pcie_write_config_byte,
703 pcie_write_config_word,
704 pcie_write_config_dword);
708 mbase = (u32 *)CFG_PCIE0_XCFGBASE;
709 rmbase = (u32 *)CFG_PCIE0_CFGBASE;
710 hose->cfg_data = (u8 *)CFG_PCIE0_CFGBASE;
713 mbase = (u32 *)CFG_PCIE1_XCFGBASE;
714 rmbase = (u32 *)CFG_PCIE1_CFGBASE;
715 hose->cfg_data = (u8 *)CFG_PCIE1_CFGBASE;
717 #if CFG_PCIE_NR_PORTS > 2
719 mbase = (u32 *)CFG_PCIE2_XCFGBASE;
720 rmbase = (u32 *)CFG_PCIE2_CFGBASE;
721 hose->cfg_data = (u8 *)CFG_PCIE2_CFGBASE;
727 * Set bus numbers on our root port
729 out_8((u8 *)mbase + PCI_PRIMARY_BUS, 0);
730 out_8((u8 *)mbase + PCI_SECONDARY_BUS, 1);
731 out_8((u8 *)mbase + PCI_SUBORDINATE_BUS, 1);
734 * Set up outbound translation to hose->mem_space from PLB
735 * addresses at an offset of 0xd_0000_0000. We set the low
736 * bits of the mask to 11 to turn off splitting into 8
737 * subregions and to enable the outbound translation.
739 out_le32(mbase + PECFG_POM0LAH, 0x00000000);
740 out_le32(mbase + PECFG_POM0LAL, CFG_PCIE_MEMBASE +
741 port * CFG_PCIE_MEMSIZE);
742 debug("PECFG_POM0LA=%08x.%08x\n", in_le32(mbase + PECFG_POM0LAH),
743 in_le32(mbase + PECFG_POM0LAL));
747 mtdcr(DCRN_PEGPL_OMR1BAH(PCIE0), CFG_PCIE_ADDR_HIGH);
748 mtdcr(DCRN_PEGPL_OMR1BAL(PCIE0), CFG_PCIE_MEMBASE +
749 port * CFG_PCIE_MEMSIZE);
750 mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE0), 0x7fffffff);
751 mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE0),
752 ~(CFG_PCIE_MEMSIZE - 1) | 3);
753 debug("0:PEGPL_OMR1BA=%08x.%08x MSK=%08x.%08x\n",
754 mfdcr(DCRN_PEGPL_OMR1BAH(PCIE0)),
755 mfdcr(DCRN_PEGPL_OMR1BAL(PCIE0)),
756 mfdcr(DCRN_PEGPL_OMR1MSKH(PCIE0)),
757 mfdcr(DCRN_PEGPL_OMR1MSKL(PCIE0)));
760 mtdcr(DCRN_PEGPL_OMR1BAH(PCIE1), CFG_PCIE_ADDR_HIGH);
761 mtdcr(DCRN_PEGPL_OMR1BAL(PCIE1), CFG_PCIE_MEMBASE +
762 port * CFG_PCIE_MEMSIZE);
763 mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE1), 0x7fffffff);
764 mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE1),
765 ~(CFG_PCIE_MEMSIZE - 1) | 3);
766 debug("1:PEGPL_OMR1BA=%08x.%08x MSK=%08x.%08x\n",
767 mfdcr(DCRN_PEGPL_OMR1BAH(PCIE1)),
768 mfdcr(DCRN_PEGPL_OMR1BAL(PCIE1)),
769 mfdcr(DCRN_PEGPL_OMR1MSKH(PCIE1)),
770 mfdcr(DCRN_PEGPL_OMR1MSKL(PCIE1)));
772 #if CFG_PCIE_NR_PORTS > 2
774 mtdcr(DCRN_PEGPL_OMR1BAH(PCIE2), CFG_PCIE_ADDR_HIGH);
775 mtdcr(DCRN_PEGPL_OMR1BAL(PCIE2), CFG_PCIE_MEMBASE +
776 port * CFG_PCIE_MEMSIZE);
777 mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE2), 0x7fffffff);
778 mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE2),
779 ~(CFG_PCIE_MEMSIZE - 1) | 3);
780 debug("2:PEGPL_OMR1BA=%08x.%08x MSK=%08x.%08x\n",
781 mfdcr(DCRN_PEGPL_OMR1BAH(PCIE2)),
782 mfdcr(DCRN_PEGPL_OMR1BAL(PCIE2)),
783 mfdcr(DCRN_PEGPL_OMR1MSKH(PCIE2)),
784 mfdcr(DCRN_PEGPL_OMR1MSKL(PCIE2)));
789 /* Set up 16GB inbound memory window at 0 */
790 out_le32(mbase + PCI_BASE_ADDRESS_0, 0);
791 out_le32(mbase + PCI_BASE_ADDRESS_1, 0);
792 out_le32(mbase + PECFG_BAR0HMPA, 0x7fffffc);
793 out_le32(mbase + PECFG_BAR0LMPA, 0);
795 out_le32(mbase + PECFG_PIM01SAH, 0xffff0000);
796 out_le32(mbase + PECFG_PIM01SAL, 0x00000000);
797 out_le32(mbase + PECFG_PIM0LAL, 0);
798 out_le32(mbase + PECFG_PIM0LAH, 0);
799 out_le32(mbase + PECFG_PIM1LAL, 0x00000000);
800 out_le32(mbase + PECFG_PIM1LAH, 0x00000004);
801 out_le32(mbase + PECFG_PIMEN, 0x1);
803 /* Enable I/O, Mem, and Busmaster cycles */
804 out_le16((u16 *)(mbase + PCI_COMMAND),
805 in_le16((u16 *)(mbase + PCI_COMMAND)) |
806 PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
808 /* Set Device and Vendor Id */
809 out_le16(mbase + 0x200, 0xaaa0 + port);
810 out_le16(mbase + 0x202, 0xbed0 + port);
812 /* Set Class Code to PCI-PCI bridge and Revision Id to 1 */
813 out_le32(mbase + 0x208, 0x06040001);
815 printf("PCIE:%d successfully set as rootpoint\n", port);
818 int ppc4xx_setup_pcie_endpoint(struct pci_controller *hose, int port)
820 volatile void *mbase = NULL;
824 pcie_read_config_byte,
825 pcie_read_config_word,
826 pcie_read_config_dword,
827 pcie_write_config_byte,
828 pcie_write_config_word,
829 pcie_write_config_dword);
833 mbase = (u32 *)CFG_PCIE0_XCFGBASE;
834 hose->cfg_data = (u8 *)CFG_PCIE0_CFGBASE;
837 mbase = (u32 *)CFG_PCIE1_XCFGBASE;
838 hose->cfg_data = (u8 *)CFG_PCIE1_CFGBASE;
840 #if defined(CFG_PCIE2_CFGBASE)
842 mbase = (u32 *)CFG_PCIE2_XCFGBASE;
843 hose->cfg_data = (u8 *)CFG_PCIE2_CFGBASE;
849 * Set up outbound translation to hose->mem_space from PLB
850 * addresses at an offset of 0xd_0000_0000. We set the low
851 * bits of the mask to 11 to turn off splitting into 8
852 * subregions and to enable the outbound translation.
854 out_le32(mbase + PECFG_POM0LAH, 0x00001ff8);
855 out_le32(mbase + PECFG_POM0LAL, 0x00001000);
859 mtdcr(DCRN_PEGPL_OMR1BAH(PCIE0), CFG_PCIE_ADDR_HIGH);
860 mtdcr(DCRN_PEGPL_OMR1BAL(PCIE0), CFG_PCIE_MEMBASE +
861 port * CFG_PCIE_MEMSIZE);
862 mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE0), 0x7fffffff);
863 mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE0),
864 ~(CFG_PCIE_MEMSIZE - 1) | 3);
867 mtdcr(DCRN_PEGPL_OMR1BAH(PCIE1), CFG_PCIE_ADDR_HIGH);
868 mtdcr(DCRN_PEGPL_OMR1BAL(PCIE1), CFG_PCIE_MEMBASE +
869 port * CFG_PCIE_MEMSIZE);
870 mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE1), 0x7fffffff);
871 mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE1),
872 ~(CFG_PCIE_MEMSIZE - 1) | 3);
874 #if CFG_PCIE_NR_PORTS > 2
876 mtdcr(DCRN_PEGPL_OMR1BAH(PCIE2), CFG_PCIE_ADDR_HIGH);
877 mtdcr(DCRN_PEGPL_OMR1BAL(PCIE2), CFG_PCIE_MEMBASE +
878 port * CFG_PCIE_MEMSIZE);
879 mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE2), 0x7fffffff);
880 mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE2),
881 ~(CFG_PCIE_MEMSIZE - 1) | 3);
886 /* Set up 16GB inbound memory window at 0 */
887 out_le32(mbase + PCI_BASE_ADDRESS_0, 0);
888 out_le32(mbase + PCI_BASE_ADDRESS_1, 0);
889 out_le32(mbase + PECFG_BAR0HMPA, 0x7fffffc);
890 out_le32(mbase + PECFG_BAR0LMPA, 0);
891 out_le32(mbase + PECFG_PIM0LAL, U64_TO_U32_LOW(CFG_PCIE_INBOUND_BASE));
892 out_le32(mbase + PECFG_PIM0LAH, U64_TO_U32_HIGH(CFG_PCIE_INBOUND_BASE));
893 out_le32(mbase + PECFG_PIMEN, 0x1);
895 /* Enable I/O, Mem, and Busmaster cycles */
896 out_le16((u16 *)(mbase + PCI_COMMAND),
897 in_le16((u16 *)(mbase + PCI_COMMAND)) |
898 PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
899 out_le16(mbase + 0x200, 0xcaad); /* Setting vendor ID */
900 out_le16(mbase + 0x202, 0xfeed); /* Setting device ID */
903 while(!(SDR_READ(SDRN_PESDR_RCSSTS(port)) & (1 << 8))) {
905 printf("PCIE%d: BME not active\n", port);
911 printf("PCIE:%d successfully set as endpoint\n", port);
915 #endif /* CONFIG_440SPE && CONFIG_PCI */