1 /*-----------------------------------------------------------------------------+
3 * This source code has been made available to you by IBM on an AS-IS
4 * basis. Anyone receiving this source is licensed under IBM
5 * copyrights to use it in any way he or she deems fit, including
6 * copying it, modifying it, compiling it, and redistributing it either
7 * with or without modifications. No license under IBM patents or
8 * patent applications is to be implied by the copyright license.
10 * Any user of this software should understand that IBM cannot provide
11 * technical support for this software and will not be responsible for
12 * any consequences resulting from the use of this software.
14 * Any person who transfers this source code or any derivative work
15 * must include the IBM copyright notice, this paragraph, and the
16 * preceding two paragraphs in the transferred software.
18 * COPYRIGHT I B M CORPORATION 1995
19 * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
20 *-----------------------------------------------------------------------------*/
21 /*-----------------------------------------------------------------------------+
23 * File Name: enetemac.c
25 * Function: Device driver for the ethernet EMAC3 macro on the 405GP.
31 * Date Description of Change BY
32 * --------- --------------------- ---
33 * 05-May-99 Created MKW
34 * 27-Jun-99 Clean up JWB
35 * 16-Jul-99 Added MAL error recovery and better IP packet handling MKW
36 * 29-Jul-99 Added Full duplex support MKW
37 * 06-Aug-99 Changed names for Mal CR reg MKW
38 * 23-Aug-99 Turned off SYE when running at 10Mbs MKW
39 * 24-Aug-99 Marked descriptor empty after call_xlc MKW
40 * 07-Sep-99 Set MAL RX buffer size reg to ENET_MAX_MTU_ALIGNED / 16 MCG
41 * to avoid chaining maximum sized packets. Push starting
42 * RX descriptor address up to the next cache line boundary.
43 * 16-Jan-00 Added support for booting with IP of 0x0 MKW
44 * 15-Mar-00 Updated enetInit() to enable broadcast addresses in the
45 * EMAC_RXM register. JWB
46 * 12-Mar-01 anne-sophie.harnois@nextream.fr
47 * - Variables are compatible with those already defined in
49 * - Receive buffer descriptor ring is used to send buffers
51 * - Info print about send/received/handled packet number if
52 * INFO_405_ENET is set
53 * 17-Apr-01 stefan.roese@esd-electronics.com
54 * - MAL reset in "eth_halt" included
55 * - Enet speed and duplex output now in one line
56 * 08-May-01 stefan.roese@esd-electronics.com
57 * - MAL error handling added (eth_init called again)
58 * 13-Nov-01 stefan.roese@esd-electronics.com
59 * - Set IST bit in EMAC_M1 reg upon 100MBit or full duplex
60 * 04-Jan-02 stefan.roese@esd-electronics.com
61 * - Wait for PHY auto negotiation to complete added
62 * 06-Feb-02 stefan.roese@esd-electronics.com
63 * - Bug fixed in waiting for auto negotiation to complete
64 * 26-Feb-02 stefan.roese@esd-electronics.com
65 * - rx and tx buffer descriptors now allocated (no fixed address
67 * 17-Jun-02 stefan.roese@esd-electronics.com
68 * - MAL error debug printf 'M' removed (rx de interrupt may
69 * occur upon many incoming packets with only 4 rx buffers).
70 *-----------------------------------------------------------------------------*
71 * 17-Nov-03 travis.sawyer@sandburst.com
72 * - ported from 405gp_enet.c to utilized upto 4 EMAC ports
73 * in the 440GX. This port should work with the 440GP
75 * 15-Aug-05 sr@denx.de
76 * - merged 405gp_enet.c and 440gx_enet.c to generic 4xx_enet.c
77 now handling all 4xx cpu's.
78 *-----------------------------------------------------------------------------*/
83 #include <asm/processor.h>
86 #include <ppc4xx_enet.h>
93 * Only compile for platform with AMCC EMAC ethernet controller and
94 * network support enabled.
95 * Remark: CONFIG_405 describes Xilinx PPC405 FPGA without EMAC controller!
97 #if (CONFIG_COMMANDS & CFG_CMD_NET) && !defined(CONFIG_405) && !defined(CONFIG_IOP480)
99 #if !(defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII))
100 #error "CONFIG_MII has to be defined!"
103 #define EMAC_RESET_TIMEOUT 1000 /* 1000 ms reset timeout */
104 #define PHY_AUTONEGOTIATE_TIMEOUT 4000 /* 4000 ms autonegotiate timeout */
106 /* Ethernet Transmit and Receive Buffers */
108 * In the same way ENET_MAX_MTU and ENET_MAX_MTU_ALIGNED are set from
109 * PKTSIZE and PKTSIZE_ALIGN (include/net.h)
111 #define ENET_MAX_MTU PKTSIZE
112 #define ENET_MAX_MTU_ALIGNED PKTSIZE_ALIGN
114 /* define the number of channels implemented */
115 #define EMAC_RXCHL EMAC_NUM_DEV
116 #define EMAC_TXCHL EMAC_NUM_DEV
118 /*-----------------------------------------------------------------------------+
119 * Defines for MAL/EMAC interrupt conditions as reported in the UIC (Universal
120 * Interrupt Controller).
121 *-----------------------------------------------------------------------------*/
122 #define MAL_UIC_ERR ( UIC_MAL_SERR | UIC_MAL_TXDE | UIC_MAL_RXDE)
123 #define MAL_UIC_DEF (UIC_MAL_RXEOB | MAL_UIC_ERR)
124 #define EMAC_UIC_DEF UIC_ENET
125 #define EMAC_UIC_DEF1 UIC_ENET1
126 #define SEL_UIC_DEF(p) (p ? UIC_ENET1 : UIC_ENET )
130 #define BI_PHYMODE_NONE 0
131 #define BI_PHYMODE_ZMII 1
132 #define BI_PHYMODE_RGMII 2
135 /*-----------------------------------------------------------------------------+
136 * Global variables. TX and RX descriptors and buffers.
137 *-----------------------------------------------------------------------------*/
139 static uint32_t mal_ier;
141 #if !defined(CONFIG_NET_MULTI)
142 struct eth_device *emac0_dev = NULL;
145 /*-----------------------------------------------------------------------------+
146 * Prototypes and externals.
147 *-----------------------------------------------------------------------------*/
148 static void enet_rcv (struct eth_device *dev, unsigned long malisr);
150 int enetInt (struct eth_device *dev);
151 static void mal_err (struct eth_device *dev, unsigned long isr,
152 unsigned long uic, unsigned long maldef,
153 unsigned long mal_errr);
154 static void emac_err (struct eth_device *dev, unsigned long isr);
156 extern int phy_setup_aneg (char *devname, unsigned char addr);
157 extern int emac4xx_miiphy_read (char *devname, unsigned char addr,
158 unsigned char reg, unsigned short *value);
159 extern int emac4xx_miiphy_write (char *devname, unsigned char addr,
160 unsigned char reg, unsigned short value);
162 /*-----------------------------------------------------------------------------+
164 | Disable MAL channel, and EMACn
165 +-----------------------------------------------------------------------------*/
166 static void ppc_4xx_eth_halt (struct eth_device *dev)
168 EMAC_4XX_HW_PST hw_p = dev->priv;
169 uint32_t failsafe = 10000;
171 out32 (EMAC_IER + hw_p->hw_addr, 0x00000000); /* disable emac interrupts */
173 /* 1st reset MAL channel */
174 /* Note: writing a 0 to a channel has no effect */
175 #if defined(CONFIG_405EP) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
176 mtdcr (maltxcarr, (MAL_CR_MMSR >> (hw_p->devnum * 2)));
178 mtdcr (maltxcarr, (MAL_CR_MMSR >> hw_p->devnum));
180 mtdcr (malrxcarr, (MAL_CR_MMSR >> hw_p->devnum));
183 while (mfdcr (malrxcasr) & (MAL_CR_MMSR >> hw_p->devnum)) {
184 udelay (1000); /* Delay 1 MS so as not to hammer the register */
191 out32 (EMAC_M0 + hw_p->hw_addr, EMAC_M0_SRST);
193 hw_p->print_speed = 1; /* print speed message again next time */
198 #if defined (CONFIG_440GX)
199 int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis)
202 unsigned long zmiifer;
203 unsigned long rmiifer;
205 mfsdr(sdr_pfc1, pfc1);
206 pfc1 = SDR0_PFC1_EPS_DECODE(pfc1);
213 zmiifer |= ZMII_FER_RMII << ZMII_FER_V(0);
214 zmiifer |= ZMII_FER_RMII << ZMII_FER_V(1);
215 zmiifer |= ZMII_FER_RMII << ZMII_FER_V(2);
216 zmiifer |= ZMII_FER_RMII << ZMII_FER_V(3);
217 bis->bi_phymode[0] = BI_PHYMODE_ZMII;
218 bis->bi_phymode[1] = BI_PHYMODE_ZMII;
219 bis->bi_phymode[2] = BI_PHYMODE_ZMII;
220 bis->bi_phymode[3] = BI_PHYMODE_ZMII;
223 zmiifer = ZMII_FER_SMII << ZMII_FER_V(0);
224 zmiifer = ZMII_FER_SMII << ZMII_FER_V(1);
225 zmiifer = ZMII_FER_SMII << ZMII_FER_V(2);
226 zmiifer = ZMII_FER_SMII << ZMII_FER_V(3);
227 bis->bi_phymode[0] = BI_PHYMODE_ZMII;
228 bis->bi_phymode[1] = BI_PHYMODE_ZMII;
229 bis->bi_phymode[2] = BI_PHYMODE_ZMII;
230 bis->bi_phymode[3] = BI_PHYMODE_ZMII;
233 zmiifer |= ZMII_FER_RMII << ZMII_FER_V(0);
234 rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(2);
235 bis->bi_phymode[0] = BI_PHYMODE_ZMII;
236 bis->bi_phymode[1] = BI_PHYMODE_NONE;
237 bis->bi_phymode[2] = BI_PHYMODE_RGMII;
238 bis->bi_phymode[3] = BI_PHYMODE_NONE;
241 zmiifer |= ZMII_FER_SMII << ZMII_FER_V(0);
242 zmiifer |= ZMII_FER_SMII << ZMII_FER_V(1);
243 rmiifer |= RGMII_FER_RGMII << RGMII_FER_V (2);
244 rmiifer |= RGMII_FER_RGMII << RGMII_FER_V (3);
245 bis->bi_phymode[0] = BI_PHYMODE_ZMII;
246 bis->bi_phymode[1] = BI_PHYMODE_ZMII;
247 bis->bi_phymode[2] = BI_PHYMODE_RGMII;
248 bis->bi_phymode[3] = BI_PHYMODE_RGMII;
251 zmiifer |= ZMII_FER_SMII << ZMII_FER_V (0);
252 zmiifer |= ZMII_FER_SMII << ZMII_FER_V (1);
253 zmiifer |= ZMII_FER_SMII << ZMII_FER_V (2);
254 rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(3);
255 bis->bi_phymode[0] = BI_PHYMODE_ZMII;
256 bis->bi_phymode[1] = BI_PHYMODE_ZMII;
257 bis->bi_phymode[2] = BI_PHYMODE_ZMII;
258 bis->bi_phymode[3] = BI_PHYMODE_RGMII;
261 zmiifer |= ZMII_FER_SMII << ZMII_FER_V (0);
262 zmiifer |= ZMII_FER_SMII << ZMII_FER_V (1);
263 rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(2);
264 bis->bi_phymode[0] = BI_PHYMODE_ZMII;
265 bis->bi_phymode[1] = BI_PHYMODE_ZMII;
266 bis->bi_phymode[2] = BI_PHYMODE_RGMII;
270 zmiifer = ZMII_FER_MII << ZMII_FER_V(devnum);
272 bis->bi_phymode[0] = BI_PHYMODE_ZMII;
273 bis->bi_phymode[1] = BI_PHYMODE_ZMII;
274 bis->bi_phymode[2] = BI_PHYMODE_ZMII;
275 bis->bi_phymode[3] = BI_PHYMODE_ZMII;
279 /* Ensure we setup mdio for this devnum and ONLY this devnum */
280 zmiifer |= (ZMII_FER_MDI) << ZMII_FER_V(devnum);
282 out32 (ZMII_FER, zmiifer);
283 out32 (RGMII_FER, rmiifer);
290 static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
293 unsigned long reg = 0;
296 unsigned long duplex;
297 unsigned long failsafe;
299 unsigned short devnum;
300 unsigned short reg_short;
301 #if defined(CONFIG_440GX)
306 EMAC_4XX_HW_PST hw_p = dev->priv;
308 /* before doing anything, figure out if we have a MAC address */
310 if (memcmp (dev->enetaddr, "\0\0\0\0\0\0", 6) == 0) {
311 printf("ERROR: ethaddr not set!\n");
315 #if defined(CONFIG_440GX)
316 /* Need to get the OPB frequency so we can access the PHY */
317 get_sys_info (&sysinfo);
321 mtmsr (msr & ~(MSR_EE)); /* disable interrupts */
323 devnum = hw_p->devnum;
328 * hw_p->stats.pkts_handled <= hw_p->stats.pkts_rx <= hw_p->stats.pkts_handled+PKTBUFSRX
329 * In the most cases hw_p->stats.pkts_handled = hw_p->stats.pkts_rx, but it
330 * is possible that new packets (without relationship with
331 * current transfer) have got the time to arrived before
332 * netloop calls eth_halt
334 printf ("About preceeding transfer (eth%d):\n"
335 "- Sent packet number %d\n"
336 "- Received packet number %d\n"
337 "- Handled packet number %d\n",
340 hw_p->stats.pkts_rx, hw_p->stats.pkts_handled);
342 hw_p->stats.pkts_tx = 0;
343 hw_p->stats.pkts_rx = 0;
344 hw_p->stats.pkts_handled = 0;
347 hw_p->tx_err_index = 0; /* Transmit Error Index for tx_err_log */
348 hw_p->rx_err_index = 0; /* Receive Error Index for rx_err_log */
350 hw_p->rx_slot = 0; /* MAL Receive Slot */
351 hw_p->rx_i_index = 0; /* Receive Interrupt Queue Index */
352 hw_p->rx_u_index = 0; /* Receive User Queue Index */
354 hw_p->tx_slot = 0; /* MAL Transmit Slot */
355 hw_p->tx_i_index = 0; /* Transmit Interrupt Queue Index */
356 hw_p->tx_u_index = 0; /* Transmit User Queue Index */
358 #if defined(CONFIG_440)
360 /* NOTE: 440GX spec states that mode is mutually exclusive */
361 /* NOTE: Therefore, disable all other EMACS, since we handle */
362 /* NOTE: only one emac at a time */
367 #if defined(CONFIG_440EP) || defined(CONFIG_440GR)
368 out32 (ZMII_FER, (ZMII_FER_RMII | ZMII_FER_MDI) << ZMII_FER_V (devnum));
369 #elif defined(CONFIG_440GX)
370 ethgroup = ppc_4xx_eth_setup_bridge(devnum, bis);
371 #elif defined(CONFIG_440GP)
373 out32 (ZMII_FER, ZMII_RMII | ZMII_MDI0);
375 if ((devnum == 0) || (devnum == 1)) {
376 out32 (ZMII_FER, (ZMII_FER_SMII | ZMII_FER_MDI) << ZMII_FER_V (devnum));
378 else { /* ((devnum == 2) || (devnum == 3)) */
379 out32 (ZMII_FER, ZMII_FER_MDI << ZMII_FER_V (devnum));
380 out32 (RGMII_FER, ((RGMII_FER_RGMII << RGMII_FER_V (2)) |
381 (RGMII_FER_RGMII << RGMII_FER_V (3))));
385 out32 (ZMII_SSR, ZMII_SSR_SP << ZMII_SSR_V(devnum));
386 #endif /* defined(CONFIG_440) */
388 __asm__ volatile ("eieio");
390 /* reset emac so we have access to the phy */
392 out32 (EMAC_M0 + hw_p->hw_addr, EMAC_M0_SRST);
393 __asm__ volatile ("eieio");
396 while ((in32 (EMAC_M0 + hw_p->hw_addr) & (EMAC_M0_SRST)) && failsafe) {
401 #if defined(CONFIG_440GX)
402 /* Whack the M1 register */
404 mode_reg &= ~0x00000038;
405 if (sysinfo.freqOPB <= 50000000);
406 else if (sysinfo.freqOPB <= 66666667)
407 mode_reg |= EMAC_M1_OBCI_66;
408 else if (sysinfo.freqOPB <= 83333333)
409 mode_reg |= EMAC_M1_OBCI_83;
410 else if (sysinfo.freqOPB <= 100000000)
411 mode_reg |= EMAC_M1_OBCI_100;
413 mode_reg |= EMAC_M1_OBCI_GT100;
415 out32 (EMAC_M1 + hw_p->hw_addr, mode_reg);
416 #endif /* defined(CONFIG_440GX) */
418 /* wait for PHY to complete auto negotiation */
420 #ifndef CONFIG_CS8952_PHY
423 reg = CONFIG_PHY_ADDR;
425 #if defined (CONFIG_PHY1_ADDR)
427 reg = CONFIG_PHY1_ADDR;
430 #if defined (CONFIG_440GX)
432 reg = CONFIG_PHY2_ADDR;
435 reg = CONFIG_PHY3_ADDR;
439 reg = CONFIG_PHY_ADDR;
443 bis->bi_phynum[devnum] = reg;
445 #if defined(CONFIG_PHY_RESET)
447 * Reset the phy, only if its the first time through
448 * otherwise, just check the speeds & feeds
450 if (hw_p->first_init == 0) {
451 miiphy_reset (dev->name, reg);
453 #if defined(CONFIG_440GX)
454 #if defined(CONFIG_CIS8201_PHY)
456 * Cicada 8201 PHY needs to have an extended register whacked
459 if ( ((devnum == 2) || (devnum ==3)) && (4 == ethgroup) ) {
460 #if defined(CONFIG_CIS8201_SHORT_ETCH)
461 miiphy_write (dev->name, reg, 23, 0x1300);
463 miiphy_write (dev->name, reg, 23, 0x1000);
466 * Vitesse VSC8201/Cicada CIS8201 errata:
467 * Interoperability problem with Intel 82547EI phys
468 * This work around (provided by Vitesse) changes
469 * the default timer convergence from 8ms to 12ms
471 miiphy_write (dev->name, reg, 0x1f, 0x2a30);
472 miiphy_write (dev->name, reg, 0x08, 0x0200);
473 miiphy_write (dev->name, reg, 0x1f, 0x52b5);
474 miiphy_write (dev->name, reg, 0x02, 0x0004);
475 miiphy_write (dev->name, reg, 0x01, 0x0671);
476 miiphy_write (dev->name, reg, 0x00, 0x8fae);
477 miiphy_write (dev->name, reg, 0x1f, 0x2a30);
478 miiphy_write (dev->name, reg, 0x08, 0x0000);
479 miiphy_write (dev->name, reg, 0x1f, 0x0000);
480 /* end Vitesse/Cicada errata */
484 /* Start/Restart autonegotiation */
485 phy_setup_aneg (dev->name, reg);
488 #endif /* defined(CONFIG_PHY_RESET) */
490 miiphy_read (dev->name, reg, PHY_BMSR, ®_short);
493 * Wait if PHY is capable of autonegotiation and autonegotiation is not complete
495 if ((reg_short & PHY_BMSR_AUTN_ABLE)
496 && !(reg_short & PHY_BMSR_AUTN_COMP)) {
497 puts ("Waiting for PHY auto negotiation to complete");
499 while (!(reg_short & PHY_BMSR_AUTN_COMP)) {
503 if (i > PHY_AUTONEGOTIATE_TIMEOUT) {
504 puts (" TIMEOUT !\n");
508 if ((i++ % 1000) == 0) {
511 udelay (1000); /* 1 ms */
512 miiphy_read (dev->name, reg, PHY_BMSR, ®_short);
516 udelay (500000); /* another 500 ms (results in faster booting) */
518 #endif /* #ifndef CONFIG_CS8952_PHY */
520 speed = miiphy_speed (dev->name, reg);
521 duplex = miiphy_duplex (dev->name, reg);
523 if (hw_p->print_speed) {
524 hw_p->print_speed = 0;
525 printf ("ENET Speed is %d Mbps - %s duplex connection\n",
526 (int) speed, (duplex == HALF) ? "HALF" : "FULL");
529 #if defined(CONFIG_440)
530 #if defined(CONFIG_440EP) || defined(CONFIG_440GR)
533 reg = (reg & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_RMII_100M;
535 reg = (reg & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_RMII_10M;
540 /* Set ZMII/RGMII speed according to the phy link speed */
541 reg = in32 (ZMII_SSR);
542 if ( (speed == 100) || (speed == 1000) )
543 out32 (ZMII_SSR, reg | (ZMII_SSR_SP << ZMII_SSR_V (devnum)));
545 out32 (ZMII_SSR, reg & (~(ZMII_SSR_SP << ZMII_SSR_V (devnum))));
547 if ((devnum == 2) || (devnum == 3)) {
549 reg = (RGMII_SSR_SP_1000MBPS << RGMII_SSR_V (devnum));
550 else if (speed == 100)
551 reg = (RGMII_SSR_SP_100MBPS << RGMII_SSR_V (devnum));
553 reg = (RGMII_SSR_SP_10MBPS << RGMII_SSR_V (devnum));
555 out32 (RGMII_SSR, reg);
557 #endif /* defined(CONFIG_440) */
559 /* set the Mal configuration reg */
560 #if defined(CONFIG_440GX)
561 mtdcr (malmcr, MAL_CR_PLBB | MAL_CR_OPBBL | MAL_CR_LEA |
562 MAL_CR_PLBLT_DEFAULT | MAL_CR_EOPIE | 0x00330000);
564 mtdcr (malmcr, MAL_CR_PLBB | MAL_CR_OPBBL | MAL_CR_LEA | MAL_CR_PLBLT_DEFAULT);
565 /* Errata 1.12: MAL_1 -- Disable MAL bursting */
566 if (get_pvr() == PVR_440GP_RB) {
567 mtdcr (malmcr, mfdcr(malmcr) & ~MAL_CR_PLBB);
571 /* Free "old" buffers */
572 if (hw_p->alloc_tx_buf)
573 free (hw_p->alloc_tx_buf);
574 if (hw_p->alloc_rx_buf)
575 free (hw_p->alloc_rx_buf);
578 * Malloc MAL buffer desciptors, make sure they are
579 * aligned on cache line boundary size
580 * (401/403/IOP480 = 16, 405 = 32)
581 * and doesn't cross cache block boundaries.
584 (mal_desc_t *) malloc ((sizeof (mal_desc_t) * NUM_TX_BUFF) +
585 ((2 * CFG_CACHELINE_SIZE) - 2));
586 if (NULL == hw_p->alloc_tx_buf)
588 if (((int) hw_p->alloc_tx_buf & CACHELINE_MASK) != 0) {
590 (mal_desc_t *) ((int) hw_p->alloc_tx_buf +
593 alloc_tx_buf & CACHELINE_MASK));
595 hw_p->tx = hw_p->alloc_tx_buf;
599 (mal_desc_t *) malloc ((sizeof (mal_desc_t) * NUM_RX_BUFF) +
600 ((2 * CFG_CACHELINE_SIZE) - 2));
601 if (NULL == hw_p->alloc_rx_buf) {
602 free(hw_p->alloc_tx_buf);
603 hw_p->alloc_tx_buf = NULL;
607 if (((int) hw_p->alloc_rx_buf & CACHELINE_MASK) != 0) {
609 (mal_desc_t *) ((int) hw_p->alloc_rx_buf +
612 alloc_rx_buf & CACHELINE_MASK));
614 hw_p->rx = hw_p->alloc_rx_buf;
617 for (i = 0; i < NUM_TX_BUFF; i++) {
618 hw_p->tx[i].ctrl = 0;
619 hw_p->tx[i].data_len = 0;
620 if (hw_p->first_init == 0) {
622 (char *) malloc (ENET_MAX_MTU_ALIGNED);
623 if (NULL == hw_p->txbuf_ptr) {
624 free(hw_p->alloc_rx_buf);
625 free(hw_p->alloc_tx_buf);
626 hw_p->alloc_rx_buf = NULL;
627 hw_p->alloc_tx_buf = NULL;
628 for(j = 0; j < i; j++) {
629 free(hw_p->tx[i].data_ptr);
630 hw_p->tx[i].data_ptr = NULL;
634 hw_p->tx[i].data_ptr = hw_p->txbuf_ptr;
635 if ((NUM_TX_BUFF - 1) == i)
636 hw_p->tx[i].ctrl |= MAL_TX_CTRL_WRAP;
637 hw_p->tx_run[i] = -1;
639 printf ("TX_BUFF %d @ 0x%08lx\n", i,
640 (ulong) hw_p->tx[i].data_ptr);
644 for (i = 0; i < NUM_RX_BUFF; i++) {
645 hw_p->rx[i].ctrl = 0;
646 hw_p->rx[i].data_len = 0;
647 /* rx[i].data_ptr = (char *) &rx_buff[i]; */
648 hw_p->rx[i].data_ptr = (char *) NetRxPackets[i];
649 if ((NUM_RX_BUFF - 1) == i)
650 hw_p->rx[i].ctrl |= MAL_RX_CTRL_WRAP;
651 hw_p->rx[i].ctrl |= MAL_RX_CTRL_EMPTY | MAL_RX_CTRL_INTR;
652 hw_p->rx_ready[i] = -1;
654 printf ("RX_BUFF %d @ 0x%08lx\n", i, (ulong) rx[i].data_ptr);
660 reg |= dev->enetaddr[0]; /* set high address */
662 reg |= dev->enetaddr[1];
664 out32 (EMAC_IAH + hw_p->hw_addr, reg);
667 reg |= dev->enetaddr[2]; /* set low address */
669 reg |= dev->enetaddr[3];
671 reg |= dev->enetaddr[4];
673 reg |= dev->enetaddr[5];
675 out32 (EMAC_IAL + hw_p->hw_addr, reg);
679 /* setup MAL tx & rx channel pointers */
680 #if defined (CONFIG_405EP) || defined (CONFIG_440EP) || defined (CONFIG_440GR)
681 mtdcr (maltxctp2r, hw_p->tx);
683 mtdcr (maltxctp1r, hw_p->tx);
685 #if defined(CONFIG_440)
686 mtdcr (maltxbattr, 0x0);
687 mtdcr (malrxbattr, 0x0);
689 mtdcr (malrxctp1r, hw_p->rx);
690 /* set RX buffer size */
691 mtdcr (malrcbs1, ENET_MAX_MTU_ALIGNED / 16);
693 #if defined (CONFIG_440GX)
695 /* setup MAL tx & rx channel pointers */
696 mtdcr (maltxbattr, 0x0);
697 mtdcr (malrxbattr, 0x0);
698 mtdcr (maltxctp2r, hw_p->tx);
699 mtdcr (malrxctp2r, hw_p->rx);
700 /* set RX buffer size */
701 mtdcr (malrcbs2, ENET_MAX_MTU_ALIGNED / 16);
704 /* setup MAL tx & rx channel pointers */
705 mtdcr (maltxbattr, 0x0);
706 mtdcr (maltxctp3r, hw_p->tx);
707 mtdcr (malrxbattr, 0x0);
708 mtdcr (malrxctp3r, hw_p->rx);
709 /* set RX buffer size */
710 mtdcr (malrcbs3, ENET_MAX_MTU_ALIGNED / 16);
712 #endif /* CONFIG_440GX */
715 /* setup MAL tx & rx channel pointers */
716 #if defined(CONFIG_440)
717 mtdcr (maltxbattr, 0x0);
718 mtdcr (malrxbattr, 0x0);
720 mtdcr (maltxctp0r, hw_p->tx);
721 mtdcr (malrxctp0r, hw_p->rx);
722 /* set RX buffer size */
723 mtdcr (malrcbs0, ENET_MAX_MTU_ALIGNED / 16);
727 /* Enable MAL transmit and receive channels */
728 #if defined(CONFIG_405EP) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
729 mtdcr (maltxcasr, (MAL_TXRX_CASR >> (hw_p->devnum*2)));
731 mtdcr (maltxcasr, (MAL_TXRX_CASR >> hw_p->devnum));
733 mtdcr (malrxcasr, (MAL_TXRX_CASR >> hw_p->devnum));
735 /* set transmit enable & receive enable */
736 out32 (EMAC_M0 + hw_p->hw_addr, EMAC_M0_TXE | EMAC_M0_RXE);
738 /* set receive fifo to 4k and tx fifo to 2k */
739 mode_reg = in32 (EMAC_M1 + hw_p->hw_addr);
740 mode_reg |= EMAC_M1_RFS_4K | EMAC_M1_TX_FIFO_2K;
743 if (speed == _1000BASET)
744 mode_reg = mode_reg | EMAC_M1_MF_1000MBPS | EMAC_M1_IST;
745 else if (speed == _100BASET)
746 mode_reg = mode_reg | EMAC_M1_MF_100MBPS | EMAC_M1_IST;
748 mode_reg = mode_reg & ~0x00C00000; /* 10 MBPS */
750 mode_reg = mode_reg | 0x80000000 | EMAC_M1_IST;
752 out32 (EMAC_M1 + hw_p->hw_addr, mode_reg);
754 /* Enable broadcast and indvidual address */
755 /* TBS: enabling runts as some misbehaved nics will send runts */
756 out32 (EMAC_RXM + hw_p->hw_addr, EMAC_RMR_BAE | EMAC_RMR_IAE);
758 /* we probably need to set the tx mode1 reg? maybe at tx time */
760 /* set transmit request threshold register */
761 out32 (EMAC_TRTR + hw_p->hw_addr, 0x18000000); /* 256 byte threshold */
763 /* set receive low/high water mark register */
764 #if defined(CONFIG_440)
765 /* 440GP has a 64 byte burst length */
766 out32 (EMAC_RX_HI_LO_WMARK + hw_p->hw_addr, 0x80009000);
768 /* 405s have a 16 byte burst length */
769 out32 (EMAC_RX_HI_LO_WMARK + hw_p->hw_addr, 0x0f002000);
770 #endif /* defined(CONFIG_440) */
771 out32 (EMAC_TXM1 + hw_p->hw_addr, 0xf8640000);
773 /* Set fifo limit entry in tx mode 0 */
774 out32 (EMAC_TXM0 + hw_p->hw_addr, 0x00000003);
776 out32 (EMAC_I_FRAME_GAP_REG + hw_p->hw_addr, 0x00000008);
779 hw_p->emac_ier = EMAC_ISR_PTLE | EMAC_ISR_BFCS | EMAC_ISR_ORE | EMAC_ISR_IRE;
780 if (speed == _100BASET)
781 hw_p->emac_ier = hw_p->emac_ier | EMAC_ISR_SYE;
783 out32 (EMAC_ISR + hw_p->hw_addr, 0xffffffff); /* clear pending interrupts */
784 out32 (EMAC_IER + hw_p->hw_addr, hw_p->emac_ier);
786 if (hw_p->first_init == 0) {
788 * Connect interrupt service routines
790 irq_install_handler (VECNUM_ETH0 + (hw_p->devnum * 2),
791 (interrupt_handler_t *) enetInt, dev);
794 mtmsr (msr); /* enable interrupts again */
797 hw_p->first_init = 1;
803 static int ppc_4xx_eth_send (struct eth_device *dev, volatile void *ptr,
806 struct enet_frame *ef_ptr;
807 ulong time_start, time_now;
808 unsigned long temp_txm0;
809 EMAC_4XX_HW_PST hw_p = dev->priv;
811 ef_ptr = (struct enet_frame *) ptr;
813 /*-----------------------------------------------------------------------+
814 * Copy in our address into the frame.
815 *-----------------------------------------------------------------------*/
816 (void) memcpy (ef_ptr->source_addr, dev->enetaddr, ENET_ADDR_LENGTH);
818 /*-----------------------------------------------------------------------+
819 * If frame is too long or too short, modify length.
820 *-----------------------------------------------------------------------*/
821 /* TBS: where does the fragment go???? */
822 if (len > ENET_MAX_MTU)
825 /* memcpy ((void *) &tx_buff[tx_slot], (const void *) ptr, len); */
826 memcpy ((void *) hw_p->txbuf_ptr, (const void *) ptr, len);
828 /*-----------------------------------------------------------------------+
829 * set TX Buffer busy, and send it
830 *-----------------------------------------------------------------------*/
831 hw_p->tx[hw_p->tx_slot].ctrl = (MAL_TX_CTRL_LAST |
832 EMAC_TX_CTRL_GFCS | EMAC_TX_CTRL_GP) &
833 ~(EMAC_TX_CTRL_ISA | EMAC_TX_CTRL_RSA);
834 if ((NUM_TX_BUFF - 1) == hw_p->tx_slot)
835 hw_p->tx[hw_p->tx_slot].ctrl |= MAL_TX_CTRL_WRAP;
837 hw_p->tx[hw_p->tx_slot].data_len = (short) len;
838 hw_p->tx[hw_p->tx_slot].ctrl |= MAL_TX_CTRL_READY;
840 __asm__ volatile ("eieio");
842 out32 (EMAC_TXM0 + hw_p->hw_addr,
843 in32 (EMAC_TXM0 + hw_p->hw_addr) | EMAC_TXM0_GNP0);
845 hw_p->stats.pkts_tx++;
848 /*-----------------------------------------------------------------------+
849 * poll unitl the packet is sent and then make sure it is OK
850 *-----------------------------------------------------------------------*/
851 time_start = get_timer (0);
853 temp_txm0 = in32 (EMAC_TXM0 + hw_p->hw_addr);
854 /* loop until either TINT turns on or 3 seconds elapse */
855 if ((temp_txm0 & EMAC_TXM0_GNP0) != 0) {
856 /* transmit is done, so now check for errors
857 * If there is an error, an interrupt should
858 * happen when we return
860 time_now = get_timer (0);
861 if ((time_now - time_start) > 3000) {
870 #if defined (CONFIG_440)
872 int enetInt (struct eth_device *dev)
875 int rc = -1; /* default to not us */
876 unsigned long mal_isr;
877 unsigned long emac_isr = 0;
878 unsigned long mal_rx_eob;
879 unsigned long my_uic0msr, my_uic1msr;
881 #if defined(CONFIG_440GX)
882 unsigned long my_uic2msr;
884 EMAC_4XX_HW_PST hw_p;
887 * Because the mal is generic, we need to get the current
890 #if defined(CONFIG_NET_MULTI)
899 /* enter loop that stays in interrupt code until nothing to service */
903 my_uic0msr = mfdcr (uic0msr);
904 my_uic1msr = mfdcr (uic1msr);
905 #if defined(CONFIG_440GX)
906 my_uic2msr = mfdcr (uic2msr);
908 if (!(my_uic0msr & (UIC_MRE | UIC_MTE))
910 (UIC_ETH0 | UIC_ETH1 | UIC_MS | UIC_MTDE |
915 #if defined (CONFIG_440GX)
916 if (!(my_uic0msr & (UIC_MRE | UIC_MTE))
917 && !(my_uic2msr & (UIC_ETH2 | UIC_ETH3))) {
922 /* get and clear controller status interrupts */
923 /* look at Mal and EMAC interrupts */
924 if ((my_uic0msr & (UIC_MRE | UIC_MTE))
925 || (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) {
926 /* we have a MAL interrupt */
927 mal_isr = mfdcr (malesr);
928 /* look for mal error */
929 if (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE)) {
930 mal_err (dev, mal_isr, my_uic0msr,
931 MAL_UIC_DEF, MAL_UIC_ERR);
937 /* port by port dispatch of emac interrupts */
938 if (hw_p->devnum == 0) {
939 if (UIC_ETH0 & my_uic1msr) { /* look for EMAC errors */
940 emac_isr = in32 (EMAC_ISR + hw_p->hw_addr);
941 if ((hw_p->emac_ier & emac_isr) != 0) {
942 emac_err (dev, emac_isr);
947 if ((hw_p->emac_ier & emac_isr)
948 || (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) {
949 mtdcr (uic0sr, UIC_MRE | UIC_MTE); /* Clear */
950 mtdcr (uic1sr, UIC_ETH0 | UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */
951 return (rc); /* we had errors so get out */
955 if (hw_p->devnum == 1) {
956 if (UIC_ETH1 & my_uic1msr) { /* look for EMAC errors */
957 emac_isr = in32 (EMAC_ISR + hw_p->hw_addr);
958 if ((hw_p->emac_ier & emac_isr) != 0) {
959 emac_err (dev, emac_isr);
964 if ((hw_p->emac_ier & emac_isr)
965 || (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) {
966 mtdcr (uic0sr, UIC_MRE | UIC_MTE); /* Clear */
967 mtdcr (uic1sr, UIC_ETH1 | UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */
968 return (rc); /* we had errors so get out */
971 #if defined (CONFIG_440GX)
972 if (hw_p->devnum == 2) {
973 if (UIC_ETH2 & my_uic2msr) { /* look for EMAC errors */
974 emac_isr = in32 (EMAC_ISR + hw_p->hw_addr);
975 if ((hw_p->emac_ier & emac_isr) != 0) {
976 emac_err (dev, emac_isr);
981 if ((hw_p->emac_ier & emac_isr)
982 || (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) {
983 mtdcr (uic0sr, UIC_MRE | UIC_MTE); /* Clear */
984 mtdcr (uic1sr, UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */
985 mtdcr (uic2sr, UIC_ETH2);
986 return (rc); /* we had errors so get out */
990 if (hw_p->devnum == 3) {
991 if (UIC_ETH3 & my_uic2msr) { /* look for EMAC errors */
992 emac_isr = in32 (EMAC_ISR + hw_p->hw_addr);
993 if ((hw_p->emac_ier & emac_isr) != 0) {
994 emac_err (dev, emac_isr);
999 if ((hw_p->emac_ier & emac_isr)
1000 || (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) {
1001 mtdcr (uic0sr, UIC_MRE | UIC_MTE); /* Clear */
1002 mtdcr (uic1sr, UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */
1003 mtdcr (uic2sr, UIC_ETH3);
1004 return (rc); /* we had errors so get out */
1007 #endif /* CONFIG_440GX */
1008 /* handle MAX TX EOB interrupt from a tx */
1009 if (my_uic0msr & UIC_MTE) {
1010 mal_rx_eob = mfdcr (maltxeobisr);
1011 mtdcr (maltxeobisr, mal_rx_eob);
1012 mtdcr (uic0sr, UIC_MTE);
1014 /* handle MAL RX EOB interupt from a receive */
1015 /* check for EOB on valid channels */
1016 if (my_uic0msr & UIC_MRE) {
1017 mal_rx_eob = mfdcr (malrxeobisr);
1018 if ((mal_rx_eob & (0x80000000 >> hw_p->devnum)) != 0) { /* call emac routine for channel x */
1020 mtdcr(malrxeobisr, mal_rx_eob); */
1021 enet_rcv (dev, emac_isr);
1022 /* indicate that we serviced an interrupt */
1027 mtdcr (uic0sr, UIC_MRE); /* Clear */
1028 mtdcr (uic1sr, UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */
1029 switch (hw_p->devnum) {
1031 mtdcr (uic1sr, UIC_ETH0);
1034 mtdcr (uic1sr, UIC_ETH1);
1036 #if defined (CONFIG_440GX)
1038 mtdcr (uic2sr, UIC_ETH2);
1041 mtdcr (uic2sr, UIC_ETH3);
1043 #endif /* CONFIG_440GX */
1052 #else /* CONFIG_440 */
1054 int enetInt (struct eth_device *dev)
1057 int rc = -1; /* default to not us */
1058 unsigned long mal_isr;
1059 unsigned long emac_isr = 0;
1060 unsigned long mal_rx_eob;
1061 unsigned long my_uicmsr;
1063 EMAC_4XX_HW_PST hw_p;
1066 * Because the mal is generic, we need to get the current
1069 #if defined(CONFIG_NET_MULTI)
1070 dev = eth_get_dev();
1077 /* enter loop that stays in interrupt code until nothing to service */
1081 my_uicmsr = mfdcr (uicmsr);
1083 if ((my_uicmsr & (MAL_UIC_DEF | EMAC_UIC_DEF)) == 0) { /* not for us */
1086 /* get and clear controller status interrupts */
1087 /* look at Mal and EMAC interrupts */
1088 if ((MAL_UIC_DEF & my_uicmsr) != 0) { /* we have a MAL interrupt */
1089 mal_isr = mfdcr (malesr);
1090 /* look for mal error */
1091 if ((my_uicmsr & MAL_UIC_ERR) != 0) {
1092 mal_err (dev, mal_isr, my_uicmsr, MAL_UIC_DEF, MAL_UIC_ERR);
1098 /* port by port dispatch of emac interrupts */
1100 if ((SEL_UIC_DEF(hw_p->devnum) & my_uicmsr) != 0) { /* look for EMAC errors */
1101 emac_isr = in32 (EMAC_ISR + hw_p->hw_addr);
1102 if ((hw_p->emac_ier & emac_isr) != 0) {
1103 emac_err (dev, emac_isr);
1108 if (((hw_p->emac_ier & emac_isr) != 0) || ((MAL_UIC_ERR & my_uicmsr) != 0)) {
1109 mtdcr (uicsr, MAL_UIC_DEF | SEL_UIC_DEF(hw_p->devnum)); /* Clear */
1110 return (rc); /* we had errors so get out */
1113 /* handle MAX TX EOB interrupt from a tx */
1114 if (my_uicmsr & UIC_MAL_TXEOB) {
1115 mal_rx_eob = mfdcr (maltxeobisr);
1116 mtdcr (maltxeobisr, mal_rx_eob);
1117 mtdcr (uicsr, UIC_MAL_TXEOB);
1119 /* handle MAL RX EOB interupt from a receive */
1120 /* check for EOB on valid channels */
1121 if (my_uicmsr & UIC_MAL_RXEOB)
1123 mal_rx_eob = mfdcr (malrxeobisr);
1124 if ((mal_rx_eob & (0x80000000 >> hw_p->devnum)) != 0) { /* call emac routine for channel x */
1126 mtdcr(malrxeobisr, mal_rx_eob); */
1127 enet_rcv (dev, emac_isr);
1128 /* indicate that we serviced an interrupt */
1133 mtdcr (uicsr, MAL_UIC_DEF|EMAC_UIC_DEF|EMAC_UIC_DEF1); /* Clear */
1140 #endif /* CONFIG_440 */
1142 /*-----------------------------------------------------------------------------+
1144 *-----------------------------------------------------------------------------*/
1145 static void mal_err (struct eth_device *dev, unsigned long isr,
1146 unsigned long uic, unsigned long maldef,
1147 unsigned long mal_errr)
1149 EMAC_4XX_HW_PST hw_p = dev->priv;
1151 mtdcr (malesr, isr); /* clear interrupt */
1153 /* clear DE interrupt */
1154 mtdcr (maltxdeir, 0xC0000000);
1155 mtdcr (malrxdeir, 0x80000000);
1157 #ifdef INFO_4XX_ENET
1158 printf ("\nMAL error occured.... ISR = %lx UIC = = %lx MAL_DEF = %lx MAL_ERR= %lx \n", isr, uic, maldef, mal_errr);
1161 eth_init (hw_p->bis); /* start again... */
1164 /*-----------------------------------------------------------------------------+
1165 * EMAC Error Routine
1166 *-----------------------------------------------------------------------------*/
1167 static void emac_err (struct eth_device *dev, unsigned long isr)
1169 EMAC_4XX_HW_PST hw_p = dev->priv;
1171 printf ("EMAC%d error occured.... ISR = %lx\n", hw_p->devnum, isr);
1172 out32 (EMAC_ISR + hw_p->hw_addr, isr);
1175 /*-----------------------------------------------------------------------------+
1176 * enet_rcv() handles the ethernet receive data
1177 *-----------------------------------------------------------------------------*/
1178 static void enet_rcv (struct eth_device *dev, unsigned long malisr)
1180 struct enet_frame *ef_ptr;
1181 unsigned long data_len;
1182 unsigned long rx_eob_isr;
1183 EMAC_4XX_HW_PST hw_p = dev->priv;
1189 rx_eob_isr = mfdcr (malrxeobisr);
1190 if ((0x80000000 >> hw_p->devnum) & rx_eob_isr) {
1192 mtdcr (malrxeobisr, rx_eob_isr);
1195 while (1) { /* do all */
1198 if ((MAL_RX_CTRL_EMPTY & hw_p->rx[i].ctrl)
1199 || (loop_count >= NUM_RX_BUFF))
1203 if (NUM_RX_BUFF == hw_p->rx_slot)
1206 data_len = (unsigned long) hw_p->rx[i].data_len; /* Get len */
1208 if (data_len > ENET_MAX_MTU) /* Check len */
1211 if (EMAC_RX_ERRORS & hw_p->rx[i].ctrl) { /* Check Errors */
1213 hw_p->stats.rx_err_log[hw_p->
1216 hw_p->rx_err_index++;
1217 if (hw_p->rx_err_index ==
1219 hw_p->rx_err_index =
1222 } /* data_len < max mtu */
1224 if (!data_len) { /* no data */
1225 hw_p->rx[i].ctrl |= MAL_RX_CTRL_EMPTY; /* Free Recv Buffer */
1227 hw_p->stats.data_len_err++; /* Error at Rx */
1232 /* Check if user has already eaten buffer */
1233 /* if not => ERROR */
1234 else if (hw_p->rx_ready[hw_p->rx_i_index] != -1) {
1235 if (hw_p->is_receiving)
1236 printf ("ERROR : Receive buffers are full!\n");
1239 hw_p->stats.rx_frames++;
1240 hw_p->stats.rx += data_len;
1241 ef_ptr = (struct enet_frame *) hw_p->rx[i].
1243 #ifdef INFO_4XX_ENET
1244 hw_p->stats.pkts_rx++;
1249 hw_p->rx_ready[hw_p->rx_i_index] = i;
1251 if (NUM_RX_BUFF == hw_p->rx_i_index)
1252 hw_p->rx_i_index = 0;
1255 * free receive buffer only when
1256 * buffer has been handled (eth_rx)
1257 rx[i].ctrl |= MAL_RX_CTRL_EMPTY;
1261 } /* if EMACK_RXCHL */
1265 static int ppc_4xx_eth_rx (struct eth_device *dev)
1270 EMAC_4XX_HW_PST hw_p = dev->priv;
1272 hw_p->is_receiving = 1; /* tell driver */
1276 * use ring buffer and
1277 * get index from rx buffer desciptor queue
1279 user_index = hw_p->rx_ready[hw_p->rx_u_index];
1280 if (user_index == -1) {
1282 break; /* nothing received - leave for() loop */
1286 mtmsr (msr & ~(MSR_EE));
1288 length = hw_p->rx[user_index].data_len;
1290 /* Pass the packet up to the protocol layers. */
1291 /* NetReceive(NetRxPackets[rxIdx], length - 4); */
1292 /* NetReceive(NetRxPackets[i], length); */
1293 NetReceive (NetRxPackets[user_index], length - 4);
1294 /* Free Recv Buffer */
1295 hw_p->rx[user_index].ctrl |= MAL_RX_CTRL_EMPTY;
1296 /* Free rx buffer descriptor queue */
1297 hw_p->rx_ready[hw_p->rx_u_index] = -1;
1299 if (NUM_RX_BUFF == hw_p->rx_u_index)
1300 hw_p->rx_u_index = 0;
1302 #ifdef INFO_4XX_ENET
1303 hw_p->stats.pkts_handled++;
1306 mtmsr (msr); /* Enable IRQ's */
1309 hw_p->is_receiving = 0; /* tell driver */
1314 int ppc_4xx_eth_initialize (bd_t * bis)
1316 static int virgin = 0;
1317 struct eth_device *dev;
1319 EMAC_4XX_HW_PST hw = NULL;
1321 #if defined(CONFIG_440GX)
1324 mfsdr (sdr_pfc1, pfc1);
1325 pfc1 &= ~(0x01e00000);
1327 mtsdr (sdr_pfc1, pfc1);
1329 /* set phy num and mode */
1330 bis->bi_phynum[0] = CONFIG_PHY_ADDR;
1331 #if defined(CONFIG_PHY1_ADDR)
1332 bis->bi_phynum[1] = CONFIG_PHY1_ADDR;
1334 #if defined(CONFIG_440GX)
1335 bis->bi_phynum[2] = CONFIG_PHY2_ADDR;
1336 bis->bi_phynum[3] = CONFIG_PHY3_ADDR;
1337 bis->bi_phymode[0] = 0;
1338 bis->bi_phymode[1] = 0;
1339 bis->bi_phymode[2] = 2;
1340 bis->bi_phymode[3] = 2;
1342 #if defined (CONFIG_440GX)
1343 ppc_4xx_eth_setup_bridge(0, bis);
1347 for (eth_num = 0; eth_num < EMAC_NUM_DEV; eth_num++) {
1349 /* See if we can actually bring up the interface, otherwise, skip it */
1351 default: /* fall through */
1353 if (memcmp (bis->bi_enetaddr, "\0\0\0\0\0\0", 6) == 0) {
1354 bis->bi_phymode[eth_num] = BI_PHYMODE_NONE;
1358 #ifdef CONFIG_HAS_ETH1
1360 if (memcmp (bis->bi_enet1addr, "\0\0\0\0\0\0", 6) == 0) {
1361 bis->bi_phymode[eth_num] = BI_PHYMODE_NONE;
1366 #ifdef CONFIG_HAS_ETH2
1368 if (memcmp (bis->bi_enet2addr, "\0\0\0\0\0\0", 6) == 0) {
1369 bis->bi_phymode[eth_num] = BI_PHYMODE_NONE;
1374 #ifdef CONFIG_HAS_ETH3
1376 if (memcmp (bis->bi_enet3addr, "\0\0\0\0\0\0", 6) == 0) {
1377 bis->bi_phymode[eth_num] = BI_PHYMODE_NONE;
1384 /* Allocate device structure */
1385 dev = (struct eth_device *) malloc (sizeof (*dev));
1387 printf ("ppc_4xx_eth_initialize: "
1388 "Cannot allocate eth_device %d\n", eth_num);
1391 memset(dev, 0, sizeof(*dev));
1393 /* Allocate our private use data */
1394 hw = (EMAC_4XX_HW_PST) malloc (sizeof (*hw));
1396 printf ("ppc_4xx_eth_initialize: "
1397 "Cannot allocate private hw data for eth_device %d",
1402 memset(hw, 0, sizeof(*hw));
1405 default: /* fall through */
1408 memcpy (dev->enetaddr, bis->bi_enetaddr, 6);
1410 #ifdef CONFIG_HAS_ETH1
1412 hw->hw_addr = 0x100;
1413 memcpy (dev->enetaddr, bis->bi_enet1addr, 6);
1416 #ifdef CONFIG_HAS_ETH2
1418 hw->hw_addr = 0x400;
1419 memcpy (dev->enetaddr, bis->bi_enet2addr, 6);
1422 #ifdef CONFIG_HAS_ETH3
1424 hw->hw_addr = 0x600;
1425 memcpy (dev->enetaddr, bis->bi_enet3addr, 6);
1430 hw->devnum = eth_num;
1431 hw->print_speed = 1;
1433 sprintf (dev->name, "ppc_4xx_eth%d", eth_num);
1434 dev->priv = (void *) hw;
1435 dev->init = ppc_4xx_eth_init;
1436 dev->halt = ppc_4xx_eth_halt;
1437 dev->send = ppc_4xx_eth_send;
1438 dev->recv = ppc_4xx_eth_rx;
1441 /* set the MAL IER ??? names may change with new spec ??? */
1443 MAL_IER_DE | MAL_IER_NE | MAL_IER_TE |
1444 MAL_IER_OPBE | MAL_IER_PLBE;
1445 mtdcr (malesr, 0xffffffff); /* clear pending interrupts */
1446 mtdcr (maltxdeir, 0xffffffff); /* clear pending interrupts */
1447 mtdcr (malrxdeir, 0xffffffff); /* clear pending interrupts */
1448 mtdcr (malier, mal_ier);
1450 /* install MAL interrupt handler */
1451 irq_install_handler (VECNUM_MS,
1452 (interrupt_handler_t *) enetInt,
1454 irq_install_handler (VECNUM_MTE,
1455 (interrupt_handler_t *) enetInt,
1457 irq_install_handler (VECNUM_MRE,
1458 (interrupt_handler_t *) enetInt,
1460 irq_install_handler (VECNUM_TXDE,
1461 (interrupt_handler_t *) enetInt,
1463 irq_install_handler (VECNUM_RXDE,
1464 (interrupt_handler_t *) enetInt,
1469 #if defined(CONFIG_NET_MULTI)
1474 #if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)
1475 miiphy_register (dev->name,
1476 emac4xx_miiphy_read, emac4xx_miiphy_write);
1479 } /* end for each supported device */
1484 #if !defined(CONFIG_NET_MULTI)
1485 void eth_halt (void) {
1487 ppc_4xx_eth_halt(emac0_dev);
1493 int eth_init (bd_t *bis)
1495 ppc_4xx_eth_initialize(bis);
1497 return ppc_4xx_eth_init(emac0_dev, bis);
1499 printf("ERROR: ethaddr not set!\n");
1504 int eth_send(volatile void *packet, int length)
1506 return (ppc_4xx_eth_send(emac0_dev, packet, length));
1511 return (ppc_4xx_eth_rx(emac0_dev));
1514 int emac4xx_miiphy_initialize (bd_t * bis)
1516 #if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)
1517 miiphy_register ("ppc_4xx_eth0",
1518 emac4xx_miiphy_read, emac4xx_miiphy_write);
1523 #endif /* !defined(CONFIG_NET_MULTI) */
1525 #endif /* #if (CONFIG_COMMANDS & CFG_CMD_NET) */