1 /*-----------------------------------------------------------------------------+
3 * This source code has been made available to you by IBM on an AS-IS
4 * basis. Anyone receiving this source is licensed under IBM
5 * copyrights to use it in any way he or she deems fit, including
6 * copying it, modifying it, compiling it, and redistributing it either
7 * with or without modifications. No license under IBM patents or
8 * patent applications is to be implied by the copyright license.
10 * Any user of this software should understand that IBM cannot provide
11 * technical support for this software and will not be responsible for
12 * any consequences resulting from the use of this software.
14 * Any person who transfers this source code or any derivative work
15 * must include the IBM copyright notice, this paragraph, and the
16 * preceding two paragraphs in the transferred software.
18 * COPYRIGHT I B M CORPORATION 1995
19 * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
20 *-----------------------------------------------------------------------------*/
21 /*-----------------------------------------------------------------------------+
23 * File Name: enetemac.c
25 * Function: Device driver for the ethernet EMAC3 macro on the 405GP.
31 * Date Description of Change BY
32 * --------- --------------------- ---
33 * 05-May-99 Created MKW
34 * 27-Jun-99 Clean up JWB
35 * 16-Jul-99 Added MAL error recovery and better IP packet handling MKW
36 * 29-Jul-99 Added Full duplex support MKW
37 * 06-Aug-99 Changed names for Mal CR reg MKW
38 * 23-Aug-99 Turned off SYE when running at 10Mbs MKW
39 * 24-Aug-99 Marked descriptor empty after call_xlc MKW
40 * 07-Sep-99 Set MAL RX buffer size reg to ENET_MAX_MTU_ALIGNED / 16 MCG
41 * to avoid chaining maximum sized packets. Push starting
42 * RX descriptor address up to the next cache line boundary.
43 * 16-Jan-00 Added support for booting with IP of 0x0 MKW
44 * 15-Mar-00 Updated enetInit() to enable broadcast addresses in the
45 * EMAC_RXM register. JWB
46 * 12-Mar-01 anne-sophie.harnois@nextream.fr
47 * - Variables are compatible with those already defined in
49 * - Receive buffer descriptor ring is used to send buffers
51 * - Info print about send/received/handled packet number if
52 * INFO_405_ENET is set
53 * 17-Apr-01 stefan.roese@esd-electronics.com
54 * - MAL reset in "eth_halt" included
55 * - Enet speed and duplex output now in one line
56 * 08-May-01 stefan.roese@esd-electronics.com
57 * - MAL error handling added (eth_init called again)
58 * 13-Nov-01 stefan.roese@esd-electronics.com
59 * - Set IST bit in EMAC_M1 reg upon 100MBit or full duplex
60 * 04-Jan-02 stefan.roese@esd-electronics.com
61 * - Wait for PHY auto negotiation to complete added
62 * 06-Feb-02 stefan.roese@esd-electronics.com
63 * - Bug fixed in waiting for auto negotiation to complete
64 * 26-Feb-02 stefan.roese@esd-electronics.com
65 * - rx and tx buffer descriptors now allocated (no fixed address
67 * 17-Jun-02 stefan.roese@esd-electronics.com
68 * - MAL error debug printf 'M' removed (rx de interrupt may
69 * occur upon many incoming packets with only 4 rx buffers).
70 *-----------------------------------------------------------------------------*
71 * 17-Nov-03 travis.sawyer@sandburst.com
72 * - ported from 405gp_enet.c to utilized upto 4 EMAC ports
73 * in the 440GX. This port should work with the 440GP
75 * 15-Aug-05 sr@denx.de
76 * - merged 405gp_enet.c and 440gx_enet.c to generic 4xx_enet.c
77 now handling all 4xx cpu's.
78 *-----------------------------------------------------------------------------*/
83 #include <asm/processor.h>
86 #include <ppc4xx_enet.h>
93 * Only compile for platform with AMCC EMAC ethernet controller and
94 * network support enabled.
95 * Remark: CONFIG_405 describes Xilinx PPC405 FPGA without EMAC controller!
97 #if (CONFIG_COMMANDS & CFG_CMD_NET) && !defined(CONFIG_405) && !defined(CONFIG_IOP480)
99 #if !(defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII))
100 #error "CONFIG_MII has to be defined!"
103 #if defined(CONFIG_NETCONSOLE) && !defined(CONFIG_NET_MULTI)
104 #error "CONFIG_NET_MULTI has to be defined for NetConsole"
107 #define EMAC_RESET_TIMEOUT 1000 /* 1000 ms reset timeout */
108 #define PHY_AUTONEGOTIATE_TIMEOUT 4000 /* 4000 ms autonegotiate timeout */
110 /* Ethernet Transmit and Receive Buffers */
112 * In the same way ENET_MAX_MTU and ENET_MAX_MTU_ALIGNED are set from
113 * PKTSIZE and PKTSIZE_ALIGN (include/net.h)
115 #define ENET_MAX_MTU PKTSIZE
116 #define ENET_MAX_MTU_ALIGNED PKTSIZE_ALIGN
118 /*-----------------------------------------------------------------------------+
119 * Defines for MAL/EMAC interrupt conditions as reported in the UIC (Universal
120 * Interrupt Controller).
121 *-----------------------------------------------------------------------------*/
122 #define MAL_UIC_ERR ( UIC_MAL_SERR | UIC_MAL_TXDE | UIC_MAL_RXDE)
123 #define MAL_UIC_DEF (UIC_MAL_RXEOB | MAL_UIC_ERR)
124 #define EMAC_UIC_DEF UIC_ENET
125 #define EMAC_UIC_DEF1 UIC_ENET1
126 #define SEL_UIC_DEF(p) (p ? UIC_ENET1 : UIC_ENET )
130 #define BI_PHYMODE_NONE 0
131 #define BI_PHYMODE_ZMII 1
132 #define BI_PHYMODE_RGMII 2
135 /*-----------------------------------------------------------------------------+
136 * Global variables. TX and RX descriptors and buffers.
137 *-----------------------------------------------------------------------------*/
139 static uint32_t mal_ier;
141 #if !defined(CONFIG_NET_MULTI)
142 struct eth_device *emac0_dev = NULL;
146 * Get count of EMAC devices (doesn't have to be the max. possible number
147 * supported by the cpu)
149 #if defined(CONFIG_HAS_ETH3)
150 #define LAST_EMAC_NUM 4
151 #elif defined(CONFIG_HAS_ETH2)
152 #define LAST_EMAC_NUM 3
153 #elif defined(CONFIG_HAS_ETH1)
154 #define LAST_EMAC_NUM 2
156 #define LAST_EMAC_NUM 1
159 /*-----------------------------------------------------------------------------+
160 * Prototypes and externals.
161 *-----------------------------------------------------------------------------*/
162 static void enet_rcv (struct eth_device *dev, unsigned long malisr);
164 int enetInt (struct eth_device *dev);
165 static void mal_err (struct eth_device *dev, unsigned long isr,
166 unsigned long uic, unsigned long maldef,
167 unsigned long mal_errr);
168 static void emac_err (struct eth_device *dev, unsigned long isr);
170 extern int phy_setup_aneg (char *devname, unsigned char addr);
171 extern int emac4xx_miiphy_read (char *devname, unsigned char addr,
172 unsigned char reg, unsigned short *value);
173 extern int emac4xx_miiphy_write (char *devname, unsigned char addr,
174 unsigned char reg, unsigned short value);
176 /*-----------------------------------------------------------------------------+
178 | Disable MAL channel, and EMACn
179 +-----------------------------------------------------------------------------*/
180 static void ppc_4xx_eth_halt (struct eth_device *dev)
182 EMAC_4XX_HW_PST hw_p = dev->priv;
183 uint32_t failsafe = 10000;
185 out32 (EMAC_IER + hw_p->hw_addr, 0x00000000); /* disable emac interrupts */
187 /* 1st reset MAL channel */
188 /* Note: writing a 0 to a channel has no effect */
189 #if defined(CONFIG_405EP) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
190 mtdcr (maltxcarr, (MAL_CR_MMSR >> (hw_p->devnum * 2)));
192 mtdcr (maltxcarr, (MAL_CR_MMSR >> hw_p->devnum));
194 mtdcr (malrxcarr, (MAL_CR_MMSR >> hw_p->devnum));
197 while (mfdcr (malrxcasr) & (MAL_CR_MMSR >> hw_p->devnum)) {
198 udelay (1000); /* Delay 1 MS so as not to hammer the register */
205 out32 (EMAC_M0 + hw_p->hw_addr, EMAC_M0_SRST);
207 #ifndef CONFIG_NETCONSOLE
208 hw_p->print_speed = 1; /* print speed message again next time */
214 #if defined (CONFIG_440GX)
215 int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis)
218 unsigned long zmiifer;
219 unsigned long rmiifer;
221 mfsdr(sdr_pfc1, pfc1);
222 pfc1 = SDR0_PFC1_EPS_DECODE(pfc1);
229 zmiifer |= ZMII_FER_RMII << ZMII_FER_V(0);
230 zmiifer |= ZMII_FER_RMII << ZMII_FER_V(1);
231 zmiifer |= ZMII_FER_RMII << ZMII_FER_V(2);
232 zmiifer |= ZMII_FER_RMII << ZMII_FER_V(3);
233 bis->bi_phymode[0] = BI_PHYMODE_ZMII;
234 bis->bi_phymode[1] = BI_PHYMODE_ZMII;
235 bis->bi_phymode[2] = BI_PHYMODE_ZMII;
236 bis->bi_phymode[3] = BI_PHYMODE_ZMII;
239 zmiifer = ZMII_FER_SMII << ZMII_FER_V(0);
240 zmiifer = ZMII_FER_SMII << ZMII_FER_V(1);
241 zmiifer = ZMII_FER_SMII << ZMII_FER_V(2);
242 zmiifer = ZMII_FER_SMII << ZMII_FER_V(3);
243 bis->bi_phymode[0] = BI_PHYMODE_ZMII;
244 bis->bi_phymode[1] = BI_PHYMODE_ZMII;
245 bis->bi_phymode[2] = BI_PHYMODE_ZMII;
246 bis->bi_phymode[3] = BI_PHYMODE_ZMII;
249 zmiifer |= ZMII_FER_RMII << ZMII_FER_V(0);
250 rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(2);
251 bis->bi_phymode[0] = BI_PHYMODE_ZMII;
252 bis->bi_phymode[1] = BI_PHYMODE_NONE;
253 bis->bi_phymode[2] = BI_PHYMODE_RGMII;
254 bis->bi_phymode[3] = BI_PHYMODE_NONE;
257 zmiifer |= ZMII_FER_SMII << ZMII_FER_V(0);
258 zmiifer |= ZMII_FER_SMII << ZMII_FER_V(1);
259 rmiifer |= RGMII_FER_RGMII << RGMII_FER_V (2);
260 rmiifer |= RGMII_FER_RGMII << RGMII_FER_V (3);
261 bis->bi_phymode[0] = BI_PHYMODE_ZMII;
262 bis->bi_phymode[1] = BI_PHYMODE_ZMII;
263 bis->bi_phymode[2] = BI_PHYMODE_RGMII;
264 bis->bi_phymode[3] = BI_PHYMODE_RGMII;
267 zmiifer |= ZMII_FER_SMII << ZMII_FER_V (0);
268 zmiifer |= ZMII_FER_SMII << ZMII_FER_V (1);
269 zmiifer |= ZMII_FER_SMII << ZMII_FER_V (2);
270 rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(3);
271 bis->bi_phymode[0] = BI_PHYMODE_ZMII;
272 bis->bi_phymode[1] = BI_PHYMODE_ZMII;
273 bis->bi_phymode[2] = BI_PHYMODE_ZMII;
274 bis->bi_phymode[3] = BI_PHYMODE_RGMII;
277 zmiifer |= ZMII_FER_SMII << ZMII_FER_V (0);
278 zmiifer |= ZMII_FER_SMII << ZMII_FER_V (1);
279 rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(2);
280 bis->bi_phymode[0] = BI_PHYMODE_ZMII;
281 bis->bi_phymode[1] = BI_PHYMODE_ZMII;
282 bis->bi_phymode[2] = BI_PHYMODE_RGMII;
286 zmiifer = ZMII_FER_MII << ZMII_FER_V(devnum);
288 bis->bi_phymode[0] = BI_PHYMODE_ZMII;
289 bis->bi_phymode[1] = BI_PHYMODE_ZMII;
290 bis->bi_phymode[2] = BI_PHYMODE_ZMII;
291 bis->bi_phymode[3] = BI_PHYMODE_ZMII;
295 /* Ensure we setup mdio for this devnum and ONLY this devnum */
296 zmiifer |= (ZMII_FER_MDI) << ZMII_FER_V(devnum);
298 out32 (ZMII_FER, zmiifer);
299 out32 (RGMII_FER, rmiifer);
306 static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
309 unsigned long reg = 0;
312 unsigned long duplex;
313 unsigned long failsafe;
315 unsigned short devnum;
316 unsigned short reg_short;
317 #if defined(CONFIG_440GX)
322 EMAC_4XX_HW_PST hw_p = dev->priv;
324 /* before doing anything, figure out if we have a MAC address */
326 if (memcmp (dev->enetaddr, "\0\0\0\0\0\0", 6) == 0) {
327 printf("ERROR: ethaddr not set!\n");
331 #if defined(CONFIG_440GX)
332 /* Need to get the OPB frequency so we can access the PHY */
333 get_sys_info (&sysinfo);
337 mtmsr (msr & ~(MSR_EE)); /* disable interrupts */
339 devnum = hw_p->devnum;
344 * hw_p->stats.pkts_handled <= hw_p->stats.pkts_rx <= hw_p->stats.pkts_handled+PKTBUFSRX
345 * In the most cases hw_p->stats.pkts_handled = hw_p->stats.pkts_rx, but it
346 * is possible that new packets (without relationship with
347 * current transfer) have got the time to arrived before
348 * netloop calls eth_halt
350 printf ("About preceeding transfer (eth%d):\n"
351 "- Sent packet number %d\n"
352 "- Received packet number %d\n"
353 "- Handled packet number %d\n",
356 hw_p->stats.pkts_rx, hw_p->stats.pkts_handled);
358 hw_p->stats.pkts_tx = 0;
359 hw_p->stats.pkts_rx = 0;
360 hw_p->stats.pkts_handled = 0;
363 hw_p->tx_err_index = 0; /* Transmit Error Index for tx_err_log */
364 hw_p->rx_err_index = 0; /* Receive Error Index for rx_err_log */
366 hw_p->rx_slot = 0; /* MAL Receive Slot */
367 hw_p->rx_i_index = 0; /* Receive Interrupt Queue Index */
368 hw_p->rx_u_index = 0; /* Receive User Queue Index */
370 hw_p->tx_slot = 0; /* MAL Transmit Slot */
371 hw_p->tx_i_index = 0; /* Transmit Interrupt Queue Index */
372 hw_p->tx_u_index = 0; /* Transmit User Queue Index */
374 #if defined(CONFIG_440)
376 /* NOTE: 440GX spec states that mode is mutually exclusive */
377 /* NOTE: Therefore, disable all other EMACS, since we handle */
378 /* NOTE: only one emac at a time */
383 #if defined(CONFIG_440EP) || defined(CONFIG_440GR)
384 out32 (ZMII_FER, (ZMII_FER_RMII | ZMII_FER_MDI) << ZMII_FER_V (devnum));
385 #elif defined(CONFIG_440GX)
386 ethgroup = ppc_4xx_eth_setup_bridge(devnum, bis);
387 #elif defined(CONFIG_440GP)
389 out32 (ZMII_FER, ZMII_RMII | ZMII_MDI0);
391 if ((devnum == 0) || (devnum == 1)) {
392 out32 (ZMII_FER, (ZMII_FER_SMII | ZMII_FER_MDI) << ZMII_FER_V (devnum));
394 else { /* ((devnum == 2) || (devnum == 3)) */
395 out32 (ZMII_FER, ZMII_FER_MDI << ZMII_FER_V (devnum));
396 out32 (RGMII_FER, ((RGMII_FER_RGMII << RGMII_FER_V (2)) |
397 (RGMII_FER_RGMII << RGMII_FER_V (3))));
401 out32 (ZMII_SSR, ZMII_SSR_SP << ZMII_SSR_V(devnum));
402 #endif /* defined(CONFIG_440) */
404 __asm__ volatile ("eieio");
406 /* reset emac so we have access to the phy */
408 out32 (EMAC_M0 + hw_p->hw_addr, EMAC_M0_SRST);
409 __asm__ volatile ("eieio");
412 while ((in32 (EMAC_M0 + hw_p->hw_addr) & (EMAC_M0_SRST)) && failsafe) {
417 #if defined(CONFIG_440GX)
418 /* Whack the M1 register */
420 mode_reg &= ~0x00000038;
421 if (sysinfo.freqOPB <= 50000000);
422 else if (sysinfo.freqOPB <= 66666667)
423 mode_reg |= EMAC_M1_OBCI_66;
424 else if (sysinfo.freqOPB <= 83333333)
425 mode_reg |= EMAC_M1_OBCI_83;
426 else if (sysinfo.freqOPB <= 100000000)
427 mode_reg |= EMAC_M1_OBCI_100;
429 mode_reg |= EMAC_M1_OBCI_GT100;
431 out32 (EMAC_M1 + hw_p->hw_addr, mode_reg);
432 #endif /* defined(CONFIG_440GX) */
434 /* wait for PHY to complete auto negotiation */
436 #ifndef CONFIG_CS8952_PHY
439 reg = CONFIG_PHY_ADDR;
441 #if defined (CONFIG_PHY1_ADDR)
443 reg = CONFIG_PHY1_ADDR;
446 #if defined (CONFIG_440GX)
448 reg = CONFIG_PHY2_ADDR;
451 reg = CONFIG_PHY3_ADDR;
455 reg = CONFIG_PHY_ADDR;
459 bis->bi_phynum[devnum] = reg;
461 #if defined(CONFIG_PHY_RESET)
463 * Reset the phy, only if its the first time through
464 * otherwise, just check the speeds & feeds
466 if (hw_p->first_init == 0) {
467 miiphy_reset (dev->name, reg);
469 #if defined(CONFIG_440GX)
470 #if defined(CONFIG_CIS8201_PHY)
472 * Cicada 8201 PHY needs to have an extended register whacked
475 if ( ((devnum == 2) || (devnum ==3)) && (4 == ethgroup) ) {
476 #if defined(CONFIG_CIS8201_SHORT_ETCH)
477 miiphy_write (dev->name, reg, 23, 0x1300);
479 miiphy_write (dev->name, reg, 23, 0x1000);
482 * Vitesse VSC8201/Cicada CIS8201 errata:
483 * Interoperability problem with Intel 82547EI phys
484 * This work around (provided by Vitesse) changes
485 * the default timer convergence from 8ms to 12ms
487 miiphy_write (dev->name, reg, 0x1f, 0x2a30);
488 miiphy_write (dev->name, reg, 0x08, 0x0200);
489 miiphy_write (dev->name, reg, 0x1f, 0x52b5);
490 miiphy_write (dev->name, reg, 0x02, 0x0004);
491 miiphy_write (dev->name, reg, 0x01, 0x0671);
492 miiphy_write (dev->name, reg, 0x00, 0x8fae);
493 miiphy_write (dev->name, reg, 0x1f, 0x2a30);
494 miiphy_write (dev->name, reg, 0x08, 0x0000);
495 miiphy_write (dev->name, reg, 0x1f, 0x0000);
496 /* end Vitesse/Cicada errata */
500 /* Start/Restart autonegotiation */
501 phy_setup_aneg (dev->name, reg);
504 #endif /* defined(CONFIG_PHY_RESET) */
506 miiphy_read (dev->name, reg, PHY_BMSR, ®_short);
509 * Wait if PHY is capable of autonegotiation and autonegotiation is not complete
511 if ((reg_short & PHY_BMSR_AUTN_ABLE)
512 && !(reg_short & PHY_BMSR_AUTN_COMP)) {
513 puts ("Waiting for PHY auto negotiation to complete");
515 while (!(reg_short & PHY_BMSR_AUTN_COMP)) {
519 if (i > PHY_AUTONEGOTIATE_TIMEOUT) {
520 puts (" TIMEOUT !\n");
524 if ((i++ % 1000) == 0) {
527 udelay (1000); /* 1 ms */
528 miiphy_read (dev->name, reg, PHY_BMSR, ®_short);
532 udelay (500000); /* another 500 ms (results in faster booting) */
534 #endif /* #ifndef CONFIG_CS8952_PHY */
536 speed = miiphy_speed (dev->name, reg);
537 duplex = miiphy_duplex (dev->name, reg);
539 if (hw_p->print_speed) {
540 hw_p->print_speed = 0;
541 printf ("ENET Speed is %d Mbps - %s duplex connection\n",
542 (int) speed, (duplex == HALF) ? "HALF" : "FULL");
545 #if defined(CONFIG_440)
546 #if defined(CONFIG_440EP) || defined(CONFIG_440GR)
549 reg = (reg & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_RMII_100M;
551 reg = (reg & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_RMII_10M;
556 /* Set ZMII/RGMII speed according to the phy link speed */
557 reg = in32 (ZMII_SSR);
558 if ( (speed == 100) || (speed == 1000) )
559 out32 (ZMII_SSR, reg | (ZMII_SSR_SP << ZMII_SSR_V (devnum)));
561 out32 (ZMII_SSR, reg & (~(ZMII_SSR_SP << ZMII_SSR_V (devnum))));
563 if ((devnum == 2) || (devnum == 3)) {
565 reg = (RGMII_SSR_SP_1000MBPS << RGMII_SSR_V (devnum));
566 else if (speed == 100)
567 reg = (RGMII_SSR_SP_100MBPS << RGMII_SSR_V (devnum));
569 reg = (RGMII_SSR_SP_10MBPS << RGMII_SSR_V (devnum));
571 out32 (RGMII_SSR, reg);
573 #endif /* defined(CONFIG_440) */
575 /* set the Mal configuration reg */
576 #if defined(CONFIG_440GX)
577 mtdcr (malmcr, MAL_CR_PLBB | MAL_CR_OPBBL | MAL_CR_LEA |
578 MAL_CR_PLBLT_DEFAULT | MAL_CR_EOPIE | 0x00330000);
580 mtdcr (malmcr, MAL_CR_PLBB | MAL_CR_OPBBL | MAL_CR_LEA | MAL_CR_PLBLT_DEFAULT);
581 /* Errata 1.12: MAL_1 -- Disable MAL bursting */
582 if (get_pvr() == PVR_440GP_RB) {
583 mtdcr (malmcr, mfdcr(malmcr) & ~MAL_CR_PLBB);
587 /* Free "old" buffers */
588 if (hw_p->alloc_tx_buf)
589 free (hw_p->alloc_tx_buf);
590 if (hw_p->alloc_rx_buf)
591 free (hw_p->alloc_rx_buf);
594 * Malloc MAL buffer desciptors, make sure they are
595 * aligned on cache line boundary size
596 * (401/403/IOP480 = 16, 405 = 32)
597 * and doesn't cross cache block boundaries.
600 (mal_desc_t *) malloc ((sizeof (mal_desc_t) * NUM_TX_BUFF) +
601 ((2 * CFG_CACHELINE_SIZE) - 2));
602 if (NULL == hw_p->alloc_tx_buf)
604 if (((int) hw_p->alloc_tx_buf & CACHELINE_MASK) != 0) {
606 (mal_desc_t *) ((int) hw_p->alloc_tx_buf +
609 alloc_tx_buf & CACHELINE_MASK));
611 hw_p->tx = hw_p->alloc_tx_buf;
615 (mal_desc_t *) malloc ((sizeof (mal_desc_t) * NUM_RX_BUFF) +
616 ((2 * CFG_CACHELINE_SIZE) - 2));
617 if (NULL == hw_p->alloc_rx_buf) {
618 free(hw_p->alloc_tx_buf);
619 hw_p->alloc_tx_buf = NULL;
623 if (((int) hw_p->alloc_rx_buf & CACHELINE_MASK) != 0) {
625 (mal_desc_t *) ((int) hw_p->alloc_rx_buf +
628 alloc_rx_buf & CACHELINE_MASK));
630 hw_p->rx = hw_p->alloc_rx_buf;
633 for (i = 0; i < NUM_TX_BUFF; i++) {
634 hw_p->tx[i].ctrl = 0;
635 hw_p->tx[i].data_len = 0;
636 if (hw_p->first_init == 0) {
638 (char *) malloc (ENET_MAX_MTU_ALIGNED);
639 if (NULL == hw_p->txbuf_ptr) {
640 free(hw_p->alloc_rx_buf);
641 free(hw_p->alloc_tx_buf);
642 hw_p->alloc_rx_buf = NULL;
643 hw_p->alloc_tx_buf = NULL;
644 for(j = 0; j < i; j++) {
645 free(hw_p->tx[i].data_ptr);
646 hw_p->tx[i].data_ptr = NULL;
650 hw_p->tx[i].data_ptr = hw_p->txbuf_ptr;
651 if ((NUM_TX_BUFF - 1) == i)
652 hw_p->tx[i].ctrl |= MAL_TX_CTRL_WRAP;
653 hw_p->tx_run[i] = -1;
655 printf ("TX_BUFF %d @ 0x%08lx\n", i,
656 (ulong) hw_p->tx[i].data_ptr);
660 for (i = 0; i < NUM_RX_BUFF; i++) {
661 hw_p->rx[i].ctrl = 0;
662 hw_p->rx[i].data_len = 0;
663 /* rx[i].data_ptr = (char *) &rx_buff[i]; */
664 hw_p->rx[i].data_ptr = (char *) NetRxPackets[i];
665 if ((NUM_RX_BUFF - 1) == i)
666 hw_p->rx[i].ctrl |= MAL_RX_CTRL_WRAP;
667 hw_p->rx[i].ctrl |= MAL_RX_CTRL_EMPTY | MAL_RX_CTRL_INTR;
668 hw_p->rx_ready[i] = -1;
670 printf ("RX_BUFF %d @ 0x%08lx\n", i, (ulong) rx[i].data_ptr);
676 reg |= dev->enetaddr[0]; /* set high address */
678 reg |= dev->enetaddr[1];
680 out32 (EMAC_IAH + hw_p->hw_addr, reg);
683 reg |= dev->enetaddr[2]; /* set low address */
685 reg |= dev->enetaddr[3];
687 reg |= dev->enetaddr[4];
689 reg |= dev->enetaddr[5];
691 out32 (EMAC_IAL + hw_p->hw_addr, reg);
695 /* setup MAL tx & rx channel pointers */
696 #if defined (CONFIG_405EP) || defined (CONFIG_440EP) || defined (CONFIG_440GR)
697 mtdcr (maltxctp2r, hw_p->tx);
699 mtdcr (maltxctp1r, hw_p->tx);
701 #if defined(CONFIG_440)
702 mtdcr (maltxbattr, 0x0);
703 mtdcr (malrxbattr, 0x0);
705 mtdcr (malrxctp1r, hw_p->rx);
706 /* set RX buffer size */
707 mtdcr (malrcbs1, ENET_MAX_MTU_ALIGNED / 16);
709 #if defined (CONFIG_440GX)
711 /* setup MAL tx & rx channel pointers */
712 mtdcr (maltxbattr, 0x0);
713 mtdcr (malrxbattr, 0x0);
714 mtdcr (maltxctp2r, hw_p->tx);
715 mtdcr (malrxctp2r, hw_p->rx);
716 /* set RX buffer size */
717 mtdcr (malrcbs2, ENET_MAX_MTU_ALIGNED / 16);
720 /* setup MAL tx & rx channel pointers */
721 mtdcr (maltxbattr, 0x0);
722 mtdcr (maltxctp3r, hw_p->tx);
723 mtdcr (malrxbattr, 0x0);
724 mtdcr (malrxctp3r, hw_p->rx);
725 /* set RX buffer size */
726 mtdcr (malrcbs3, ENET_MAX_MTU_ALIGNED / 16);
728 #endif /* CONFIG_440GX */
731 /* setup MAL tx & rx channel pointers */
732 #if defined(CONFIG_440)
733 mtdcr (maltxbattr, 0x0);
734 mtdcr (malrxbattr, 0x0);
736 mtdcr (maltxctp0r, hw_p->tx);
737 mtdcr (malrxctp0r, hw_p->rx);
738 /* set RX buffer size */
739 mtdcr (malrcbs0, ENET_MAX_MTU_ALIGNED / 16);
743 /* Enable MAL transmit and receive channels */
744 #if defined(CONFIG_405EP) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
745 mtdcr (maltxcasr, (MAL_TXRX_CASR >> (hw_p->devnum*2)));
747 mtdcr (maltxcasr, (MAL_TXRX_CASR >> hw_p->devnum));
749 mtdcr (malrxcasr, (MAL_TXRX_CASR >> hw_p->devnum));
751 /* set transmit enable & receive enable */
752 out32 (EMAC_M0 + hw_p->hw_addr, EMAC_M0_TXE | EMAC_M0_RXE);
754 /* set receive fifo to 4k and tx fifo to 2k */
755 mode_reg = in32 (EMAC_M1 + hw_p->hw_addr);
756 mode_reg |= EMAC_M1_RFS_4K | EMAC_M1_TX_FIFO_2K;
759 if (speed == _1000BASET)
760 mode_reg = mode_reg | EMAC_M1_MF_1000MBPS | EMAC_M1_IST;
761 else if (speed == _100BASET)
762 mode_reg = mode_reg | EMAC_M1_MF_100MBPS | EMAC_M1_IST;
764 mode_reg = mode_reg & ~0x00C00000; /* 10 MBPS */
766 mode_reg = mode_reg | 0x80000000 | EMAC_M1_IST;
768 out32 (EMAC_M1 + hw_p->hw_addr, mode_reg);
770 /* Enable broadcast and indvidual address */
771 /* TBS: enabling runts as some misbehaved nics will send runts */
772 out32 (EMAC_RXM + hw_p->hw_addr, EMAC_RMR_BAE | EMAC_RMR_IAE);
774 /* we probably need to set the tx mode1 reg? maybe at tx time */
776 /* set transmit request threshold register */
777 out32 (EMAC_TRTR + hw_p->hw_addr, 0x18000000); /* 256 byte threshold */
779 /* set receive low/high water mark register */
780 #if defined(CONFIG_440)
781 /* 440GP has a 64 byte burst length */
782 out32 (EMAC_RX_HI_LO_WMARK + hw_p->hw_addr, 0x80009000);
784 /* 405s have a 16 byte burst length */
785 out32 (EMAC_RX_HI_LO_WMARK + hw_p->hw_addr, 0x0f002000);
786 #endif /* defined(CONFIG_440) */
787 out32 (EMAC_TXM1 + hw_p->hw_addr, 0xf8640000);
789 /* Set fifo limit entry in tx mode 0 */
790 out32 (EMAC_TXM0 + hw_p->hw_addr, 0x00000003);
792 out32 (EMAC_I_FRAME_GAP_REG + hw_p->hw_addr, 0x00000008);
795 hw_p->emac_ier = EMAC_ISR_PTLE | EMAC_ISR_BFCS | EMAC_ISR_ORE | EMAC_ISR_IRE;
796 if (speed == _100BASET)
797 hw_p->emac_ier = hw_p->emac_ier | EMAC_ISR_SYE;
799 out32 (EMAC_ISR + hw_p->hw_addr, 0xffffffff); /* clear pending interrupts */
800 out32 (EMAC_IER + hw_p->hw_addr, hw_p->emac_ier);
802 if (hw_p->first_init == 0) {
804 * Connect interrupt service routines
806 irq_install_handler (VECNUM_ETH0 + (hw_p->devnum * 2),
807 (interrupt_handler_t *) enetInt, dev);
810 mtmsr (msr); /* enable interrupts again */
813 hw_p->first_init = 1;
819 static int ppc_4xx_eth_send (struct eth_device *dev, volatile void *ptr,
822 struct enet_frame *ef_ptr;
823 ulong time_start, time_now;
824 unsigned long temp_txm0;
825 EMAC_4XX_HW_PST hw_p = dev->priv;
827 ef_ptr = (struct enet_frame *) ptr;
829 /*-----------------------------------------------------------------------+
830 * Copy in our address into the frame.
831 *-----------------------------------------------------------------------*/
832 (void) memcpy (ef_ptr->source_addr, dev->enetaddr, ENET_ADDR_LENGTH);
834 /*-----------------------------------------------------------------------+
835 * If frame is too long or too short, modify length.
836 *-----------------------------------------------------------------------*/
837 /* TBS: where does the fragment go???? */
838 if (len > ENET_MAX_MTU)
841 /* memcpy ((void *) &tx_buff[tx_slot], (const void *) ptr, len); */
842 memcpy ((void *) hw_p->txbuf_ptr, (const void *) ptr, len);
844 /*-----------------------------------------------------------------------+
845 * set TX Buffer busy, and send it
846 *-----------------------------------------------------------------------*/
847 hw_p->tx[hw_p->tx_slot].ctrl = (MAL_TX_CTRL_LAST |
848 EMAC_TX_CTRL_GFCS | EMAC_TX_CTRL_GP) &
849 ~(EMAC_TX_CTRL_ISA | EMAC_TX_CTRL_RSA);
850 if ((NUM_TX_BUFF - 1) == hw_p->tx_slot)
851 hw_p->tx[hw_p->tx_slot].ctrl |= MAL_TX_CTRL_WRAP;
853 hw_p->tx[hw_p->tx_slot].data_len = (short) len;
854 hw_p->tx[hw_p->tx_slot].ctrl |= MAL_TX_CTRL_READY;
856 __asm__ volatile ("eieio");
858 out32 (EMAC_TXM0 + hw_p->hw_addr,
859 in32 (EMAC_TXM0 + hw_p->hw_addr) | EMAC_TXM0_GNP0);
861 hw_p->stats.pkts_tx++;
864 /*-----------------------------------------------------------------------+
865 * poll unitl the packet is sent and then make sure it is OK
866 *-----------------------------------------------------------------------*/
867 time_start = get_timer (0);
869 temp_txm0 = in32 (EMAC_TXM0 + hw_p->hw_addr);
870 /* loop until either TINT turns on or 3 seconds elapse */
871 if ((temp_txm0 & EMAC_TXM0_GNP0) != 0) {
872 /* transmit is done, so now check for errors
873 * If there is an error, an interrupt should
874 * happen when we return
876 time_now = get_timer (0);
877 if ((time_now - time_start) > 3000) {
886 #if defined (CONFIG_440)
888 int enetInt (struct eth_device *dev)
891 int rc = -1; /* default to not us */
892 unsigned long mal_isr;
893 unsigned long emac_isr = 0;
894 unsigned long mal_rx_eob;
895 unsigned long my_uic0msr, my_uic1msr;
897 #if defined(CONFIG_440GX)
898 unsigned long my_uic2msr;
900 EMAC_4XX_HW_PST hw_p;
903 * Because the mal is generic, we need to get the current
906 #if defined(CONFIG_NET_MULTI)
915 /* enter loop that stays in interrupt code until nothing to service */
919 my_uic0msr = mfdcr (uic0msr);
920 my_uic1msr = mfdcr (uic1msr);
921 #if defined(CONFIG_440GX)
922 my_uic2msr = mfdcr (uic2msr);
924 if (!(my_uic0msr & (UIC_MRE | UIC_MTE))
926 (UIC_ETH0 | UIC_ETH1 | UIC_MS | UIC_MTDE |
931 #if defined (CONFIG_440GX)
932 if (!(my_uic0msr & (UIC_MRE | UIC_MTE))
933 && !(my_uic2msr & (UIC_ETH2 | UIC_ETH3))) {
938 /* get and clear controller status interrupts */
939 /* look at Mal and EMAC interrupts */
940 if ((my_uic0msr & (UIC_MRE | UIC_MTE))
941 || (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) {
942 /* we have a MAL interrupt */
943 mal_isr = mfdcr (malesr);
944 /* look for mal error */
945 if (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE)) {
946 mal_err (dev, mal_isr, my_uic0msr,
947 MAL_UIC_DEF, MAL_UIC_ERR);
953 /* port by port dispatch of emac interrupts */
954 if (hw_p->devnum == 0) {
955 if (UIC_ETH0 & my_uic1msr) { /* look for EMAC errors */
956 emac_isr = in32 (EMAC_ISR + hw_p->hw_addr);
957 if ((hw_p->emac_ier & emac_isr) != 0) {
958 emac_err (dev, emac_isr);
963 if ((hw_p->emac_ier & emac_isr)
964 || (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) {
965 mtdcr (uic0sr, UIC_MRE | UIC_MTE); /* Clear */
966 mtdcr (uic1sr, UIC_ETH0 | UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */
967 return (rc); /* we had errors so get out */
971 if (hw_p->devnum == 1) {
972 if (UIC_ETH1 & my_uic1msr) { /* look for EMAC errors */
973 emac_isr = in32 (EMAC_ISR + hw_p->hw_addr);
974 if ((hw_p->emac_ier & emac_isr) != 0) {
975 emac_err (dev, emac_isr);
980 if ((hw_p->emac_ier & emac_isr)
981 || (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) {
982 mtdcr (uic0sr, UIC_MRE | UIC_MTE); /* Clear */
983 mtdcr (uic1sr, UIC_ETH1 | UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */
984 return (rc); /* we had errors so get out */
987 #if defined (CONFIG_440GX)
988 if (hw_p->devnum == 2) {
989 if (UIC_ETH2 & my_uic2msr) { /* look for EMAC errors */
990 emac_isr = in32 (EMAC_ISR + hw_p->hw_addr);
991 if ((hw_p->emac_ier & emac_isr) != 0) {
992 emac_err (dev, emac_isr);
997 if ((hw_p->emac_ier & emac_isr)
998 || (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) {
999 mtdcr (uic0sr, UIC_MRE | UIC_MTE); /* Clear */
1000 mtdcr (uic1sr, UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */
1001 mtdcr (uic2sr, UIC_ETH2);
1002 return (rc); /* we had errors so get out */
1006 if (hw_p->devnum == 3) {
1007 if (UIC_ETH3 & my_uic2msr) { /* look for EMAC errors */
1008 emac_isr = in32 (EMAC_ISR + hw_p->hw_addr);
1009 if ((hw_p->emac_ier & emac_isr) != 0) {
1010 emac_err (dev, emac_isr);
1015 if ((hw_p->emac_ier & emac_isr)
1016 || (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) {
1017 mtdcr (uic0sr, UIC_MRE | UIC_MTE); /* Clear */
1018 mtdcr (uic1sr, UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */
1019 mtdcr (uic2sr, UIC_ETH3);
1020 return (rc); /* we had errors so get out */
1023 #endif /* CONFIG_440GX */
1024 /* handle MAX TX EOB interrupt from a tx */
1025 if (my_uic0msr & UIC_MTE) {
1026 mal_rx_eob = mfdcr (maltxeobisr);
1027 mtdcr (maltxeobisr, mal_rx_eob);
1028 mtdcr (uic0sr, UIC_MTE);
1030 /* handle MAL RX EOB interupt from a receive */
1031 /* check for EOB on valid channels */
1032 if (my_uic0msr & UIC_MRE) {
1033 mal_rx_eob = mfdcr (malrxeobisr);
1034 if ((mal_rx_eob & (0x80000000 >> hw_p->devnum)) != 0) { /* call emac routine for channel x */
1036 mtdcr(malrxeobisr, mal_rx_eob); */
1037 enet_rcv (dev, emac_isr);
1038 /* indicate that we serviced an interrupt */
1043 mtdcr (uic0sr, UIC_MRE); /* Clear */
1044 mtdcr (uic1sr, UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */
1045 switch (hw_p->devnum) {
1047 mtdcr (uic1sr, UIC_ETH0);
1050 mtdcr (uic1sr, UIC_ETH1);
1052 #if defined (CONFIG_440GX)
1054 mtdcr (uic2sr, UIC_ETH2);
1057 mtdcr (uic2sr, UIC_ETH3);
1059 #endif /* CONFIG_440GX */
1068 #else /* CONFIG_440 */
1070 int enetInt (struct eth_device *dev)
1073 int rc = -1; /* default to not us */
1074 unsigned long mal_isr;
1075 unsigned long emac_isr = 0;
1076 unsigned long mal_rx_eob;
1077 unsigned long my_uicmsr;
1079 EMAC_4XX_HW_PST hw_p;
1082 * Because the mal is generic, we need to get the current
1085 #if defined(CONFIG_NET_MULTI)
1086 dev = eth_get_dev();
1093 /* enter loop that stays in interrupt code until nothing to service */
1097 my_uicmsr = mfdcr (uicmsr);
1099 if ((my_uicmsr & (MAL_UIC_DEF | EMAC_UIC_DEF)) == 0) { /* not for us */
1102 /* get and clear controller status interrupts */
1103 /* look at Mal and EMAC interrupts */
1104 if ((MAL_UIC_DEF & my_uicmsr) != 0) { /* we have a MAL interrupt */
1105 mal_isr = mfdcr (malesr);
1106 /* look for mal error */
1107 if ((my_uicmsr & MAL_UIC_ERR) != 0) {
1108 mal_err (dev, mal_isr, my_uicmsr, MAL_UIC_DEF, MAL_UIC_ERR);
1114 /* port by port dispatch of emac interrupts */
1116 if ((SEL_UIC_DEF(hw_p->devnum) & my_uicmsr) != 0) { /* look for EMAC errors */
1117 emac_isr = in32 (EMAC_ISR + hw_p->hw_addr);
1118 if ((hw_p->emac_ier & emac_isr) != 0) {
1119 emac_err (dev, emac_isr);
1124 if (((hw_p->emac_ier & emac_isr) != 0) || ((MAL_UIC_ERR & my_uicmsr) != 0)) {
1125 mtdcr (uicsr, MAL_UIC_DEF | SEL_UIC_DEF(hw_p->devnum)); /* Clear */
1126 return (rc); /* we had errors so get out */
1129 /* handle MAX TX EOB interrupt from a tx */
1130 if (my_uicmsr & UIC_MAL_TXEOB) {
1131 mal_rx_eob = mfdcr (maltxeobisr);
1132 mtdcr (maltxeobisr, mal_rx_eob);
1133 mtdcr (uicsr, UIC_MAL_TXEOB);
1135 /* handle MAL RX EOB interupt from a receive */
1136 /* check for EOB on valid channels */
1137 if (my_uicmsr & UIC_MAL_RXEOB)
1139 mal_rx_eob = mfdcr (malrxeobisr);
1140 if ((mal_rx_eob & (0x80000000 >> hw_p->devnum)) != 0) { /* call emac routine for channel x */
1142 mtdcr(malrxeobisr, mal_rx_eob); */
1143 enet_rcv (dev, emac_isr);
1144 /* indicate that we serviced an interrupt */
1149 mtdcr (uicsr, MAL_UIC_DEF|EMAC_UIC_DEF|EMAC_UIC_DEF1); /* Clear */
1156 #endif /* CONFIG_440 */
1158 /*-----------------------------------------------------------------------------+
1160 *-----------------------------------------------------------------------------*/
1161 static void mal_err (struct eth_device *dev, unsigned long isr,
1162 unsigned long uic, unsigned long maldef,
1163 unsigned long mal_errr)
1165 EMAC_4XX_HW_PST hw_p = dev->priv;
1167 mtdcr (malesr, isr); /* clear interrupt */
1169 /* clear DE interrupt */
1170 mtdcr (maltxdeir, 0xC0000000);
1171 mtdcr (malrxdeir, 0x80000000);
1173 #ifdef INFO_4XX_ENET
1174 printf ("\nMAL error occured.... ISR = %lx UIC = = %lx MAL_DEF = %lx MAL_ERR= %lx \n", isr, uic, maldef, mal_errr);
1177 eth_init (hw_p->bis); /* start again... */
1180 /*-----------------------------------------------------------------------------+
1181 * EMAC Error Routine
1182 *-----------------------------------------------------------------------------*/
1183 static void emac_err (struct eth_device *dev, unsigned long isr)
1185 EMAC_4XX_HW_PST hw_p = dev->priv;
1187 printf ("EMAC%d error occured.... ISR = %lx\n", hw_p->devnum, isr);
1188 out32 (EMAC_ISR + hw_p->hw_addr, isr);
1191 /*-----------------------------------------------------------------------------+
1192 * enet_rcv() handles the ethernet receive data
1193 *-----------------------------------------------------------------------------*/
1194 static void enet_rcv (struct eth_device *dev, unsigned long malisr)
1196 struct enet_frame *ef_ptr;
1197 unsigned long data_len;
1198 unsigned long rx_eob_isr;
1199 EMAC_4XX_HW_PST hw_p = dev->priv;
1205 rx_eob_isr = mfdcr (malrxeobisr);
1206 if ((0x80000000 >> hw_p->devnum) & rx_eob_isr) {
1208 mtdcr (malrxeobisr, rx_eob_isr);
1211 while (1) { /* do all */
1214 if ((MAL_RX_CTRL_EMPTY & hw_p->rx[i].ctrl)
1215 || (loop_count >= NUM_RX_BUFF))
1219 if (NUM_RX_BUFF == hw_p->rx_slot)
1222 data_len = (unsigned long) hw_p->rx[i].data_len; /* Get len */
1224 if (data_len > ENET_MAX_MTU) /* Check len */
1227 if (EMAC_RX_ERRORS & hw_p->rx[i].ctrl) { /* Check Errors */
1229 hw_p->stats.rx_err_log[hw_p->
1232 hw_p->rx_err_index++;
1233 if (hw_p->rx_err_index ==
1235 hw_p->rx_err_index =
1238 } /* data_len < max mtu */
1240 if (!data_len) { /* no data */
1241 hw_p->rx[i].ctrl |= MAL_RX_CTRL_EMPTY; /* Free Recv Buffer */
1243 hw_p->stats.data_len_err++; /* Error at Rx */
1248 /* Check if user has already eaten buffer */
1249 /* if not => ERROR */
1250 else if (hw_p->rx_ready[hw_p->rx_i_index] != -1) {
1251 if (hw_p->is_receiving)
1252 printf ("ERROR : Receive buffers are full!\n");
1255 hw_p->stats.rx_frames++;
1256 hw_p->stats.rx += data_len;
1257 ef_ptr = (struct enet_frame *) hw_p->rx[i].
1259 #ifdef INFO_4XX_ENET
1260 hw_p->stats.pkts_rx++;
1265 hw_p->rx_ready[hw_p->rx_i_index] = i;
1267 if (NUM_RX_BUFF == hw_p->rx_i_index)
1268 hw_p->rx_i_index = 0;
1271 * free receive buffer only when
1272 * buffer has been handled (eth_rx)
1273 rx[i].ctrl |= MAL_RX_CTRL_EMPTY;
1277 } /* if EMACK_RXCHL */
1281 static int ppc_4xx_eth_rx (struct eth_device *dev)
1286 EMAC_4XX_HW_PST hw_p = dev->priv;
1288 hw_p->is_receiving = 1; /* tell driver */
1292 * use ring buffer and
1293 * get index from rx buffer desciptor queue
1295 user_index = hw_p->rx_ready[hw_p->rx_u_index];
1296 if (user_index == -1) {
1298 break; /* nothing received - leave for() loop */
1302 mtmsr (msr & ~(MSR_EE));
1304 length = hw_p->rx[user_index].data_len;
1306 /* Pass the packet up to the protocol layers. */
1307 /* NetReceive(NetRxPackets[rxIdx], length - 4); */
1308 /* NetReceive(NetRxPackets[i], length); */
1309 NetReceive (NetRxPackets[user_index], length - 4);
1310 /* Free Recv Buffer */
1311 hw_p->rx[user_index].ctrl |= MAL_RX_CTRL_EMPTY;
1312 /* Free rx buffer descriptor queue */
1313 hw_p->rx_ready[hw_p->rx_u_index] = -1;
1315 if (NUM_RX_BUFF == hw_p->rx_u_index)
1316 hw_p->rx_u_index = 0;
1318 #ifdef INFO_4XX_ENET
1319 hw_p->stats.pkts_handled++;
1322 mtmsr (msr); /* Enable IRQ's */
1325 hw_p->is_receiving = 0; /* tell driver */
1330 int ppc_4xx_eth_initialize (bd_t * bis)
1332 static int virgin = 0;
1333 struct eth_device *dev;
1335 EMAC_4XX_HW_PST hw = NULL;
1337 #if defined(CONFIG_440GX)
1340 mfsdr (sdr_pfc1, pfc1);
1341 pfc1 &= ~(0x01e00000);
1343 mtsdr (sdr_pfc1, pfc1);
1345 /* set phy num and mode */
1346 bis->bi_phynum[0] = CONFIG_PHY_ADDR;
1347 #if defined(CONFIG_PHY1_ADDR)
1348 bis->bi_phynum[1] = CONFIG_PHY1_ADDR;
1350 #if defined(CONFIG_440GX)
1351 bis->bi_phynum[2] = CONFIG_PHY2_ADDR;
1352 bis->bi_phynum[3] = CONFIG_PHY3_ADDR;
1353 bis->bi_phymode[0] = 0;
1354 bis->bi_phymode[1] = 0;
1355 bis->bi_phymode[2] = 2;
1356 bis->bi_phymode[3] = 2;
1358 #if defined (CONFIG_440GX)
1359 ppc_4xx_eth_setup_bridge(0, bis);
1363 for (eth_num = 0; eth_num < LAST_EMAC_NUM; eth_num++) {
1365 /* See if we can actually bring up the interface, otherwise, skip it */
1367 default: /* fall through */
1369 if (memcmp (bis->bi_enetaddr, "\0\0\0\0\0\0", 6) == 0) {
1370 bis->bi_phymode[eth_num] = BI_PHYMODE_NONE;
1374 #ifdef CONFIG_HAS_ETH1
1376 if (memcmp (bis->bi_enet1addr, "\0\0\0\0\0\0", 6) == 0) {
1377 bis->bi_phymode[eth_num] = BI_PHYMODE_NONE;
1382 #ifdef CONFIG_HAS_ETH2
1384 if (memcmp (bis->bi_enet2addr, "\0\0\0\0\0\0", 6) == 0) {
1385 bis->bi_phymode[eth_num] = BI_PHYMODE_NONE;
1390 #ifdef CONFIG_HAS_ETH3
1392 if (memcmp (bis->bi_enet3addr, "\0\0\0\0\0\0", 6) == 0) {
1393 bis->bi_phymode[eth_num] = BI_PHYMODE_NONE;
1400 /* Allocate device structure */
1401 dev = (struct eth_device *) malloc (sizeof (*dev));
1403 printf ("ppc_4xx_eth_initialize: "
1404 "Cannot allocate eth_device %d\n", eth_num);
1407 memset(dev, 0, sizeof(*dev));
1409 /* Allocate our private use data */
1410 hw = (EMAC_4XX_HW_PST) malloc (sizeof (*hw));
1412 printf ("ppc_4xx_eth_initialize: "
1413 "Cannot allocate private hw data for eth_device %d",
1418 memset(hw, 0, sizeof(*hw));
1421 default: /* fall through */
1424 memcpy (dev->enetaddr, bis->bi_enetaddr, 6);
1426 #ifdef CONFIG_HAS_ETH1
1428 hw->hw_addr = 0x100;
1429 memcpy (dev->enetaddr, bis->bi_enet1addr, 6);
1432 #ifdef CONFIG_HAS_ETH2
1434 hw->hw_addr = 0x400;
1435 memcpy (dev->enetaddr, bis->bi_enet2addr, 6);
1438 #ifdef CONFIG_HAS_ETH3
1440 hw->hw_addr = 0x600;
1441 memcpy (dev->enetaddr, bis->bi_enet3addr, 6);
1446 hw->devnum = eth_num;
1447 hw->print_speed = 1;
1449 sprintf (dev->name, "ppc_4xx_eth%d", eth_num);
1450 dev->priv = (void *) hw;
1451 dev->init = ppc_4xx_eth_init;
1452 dev->halt = ppc_4xx_eth_halt;
1453 dev->send = ppc_4xx_eth_send;
1454 dev->recv = ppc_4xx_eth_rx;
1457 /* set the MAL IER ??? names may change with new spec ??? */
1459 MAL_IER_DE | MAL_IER_NE | MAL_IER_TE |
1460 MAL_IER_OPBE | MAL_IER_PLBE;
1461 mtdcr (malesr, 0xffffffff); /* clear pending interrupts */
1462 mtdcr (maltxdeir, 0xffffffff); /* clear pending interrupts */
1463 mtdcr (malrxdeir, 0xffffffff); /* clear pending interrupts */
1464 mtdcr (malier, mal_ier);
1466 /* install MAL interrupt handler */
1467 irq_install_handler (VECNUM_MS,
1468 (interrupt_handler_t *) enetInt,
1470 irq_install_handler (VECNUM_MTE,
1471 (interrupt_handler_t *) enetInt,
1473 irq_install_handler (VECNUM_MRE,
1474 (interrupt_handler_t *) enetInt,
1476 irq_install_handler (VECNUM_TXDE,
1477 (interrupt_handler_t *) enetInt,
1479 irq_install_handler (VECNUM_RXDE,
1480 (interrupt_handler_t *) enetInt,
1485 #if defined(CONFIG_NET_MULTI)
1490 #if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)
1491 miiphy_register (dev->name,
1492 emac4xx_miiphy_read, emac4xx_miiphy_write);
1495 } /* end for each supported device */
1500 #if !defined(CONFIG_NET_MULTI)
1501 void eth_halt (void) {
1503 ppc_4xx_eth_halt(emac0_dev);
1509 int eth_init (bd_t *bis)
1511 ppc_4xx_eth_initialize(bis);
1513 return ppc_4xx_eth_init(emac0_dev, bis);
1515 printf("ERROR: ethaddr not set!\n");
1520 int eth_send(volatile void *packet, int length)
1522 return (ppc_4xx_eth_send(emac0_dev, packet, length));
1527 return (ppc_4xx_eth_rx(emac0_dev));
1530 int emac4xx_miiphy_initialize (bd_t * bis)
1532 #if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)
1533 miiphy_register ("ppc_4xx_eth0",
1534 emac4xx_miiphy_read, emac4xx_miiphy_write);
1539 #endif /* !defined(CONFIG_NET_MULTI) */
1541 #endif /* #if (CONFIG_COMMANDS & CFG_CMD_NET) */