1 /*-----------------------------------------------------------------------------+
3 * This source code has been made available to you by IBM on an AS-IS
4 * basis. Anyone receiving this source is licensed under IBM
5 * copyrights to use it in any way he or she deems fit, including
6 * copying it, modifying it, compiling it, and redistributing it either
7 * with or without modifications. No license under IBM patents or
8 * patent applications is to be implied by the copyright license.
10 * Any user of this software should understand that IBM cannot provide
11 * technical support for this software and will not be responsible for
12 * any consequences resulting from the use of this software.
14 * Any person who transfers this source code or any derivative work
15 * must include the IBM copyright notice, this paragraph, and the
16 * preceding two paragraphs in the transferred software.
18 * COPYRIGHT I B M CORPORATION 1995
19 * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
20 *-----------------------------------------------------------------------------*/
21 /*-----------------------------------------------------------------------------+
23 * File Name: enetemac.c
25 * Function: Device driver for the ethernet EMAC3 macro on the 405GP.
31 * Date Description of Change BY
32 * --------- --------------------- ---
33 * 05-May-99 Created MKW
34 * 27-Jun-99 Clean up JWB
35 * 16-Jul-99 Added MAL error recovery and better IP packet handling MKW
36 * 29-Jul-99 Added Full duplex support MKW
37 * 06-Aug-99 Changed names for Mal CR reg MKW
38 * 23-Aug-99 Turned off SYE when running at 10Mbs MKW
39 * 24-Aug-99 Marked descriptor empty after call_xlc MKW
40 * 07-Sep-99 Set MAL RX buffer size reg to ENET_MAX_MTU_ALIGNED / 16 MCG
41 * to avoid chaining maximum sized packets. Push starting
42 * RX descriptor address up to the next cache line boundary.
43 * 16-Jan-00 Added support for booting with IP of 0x0 MKW
44 * 15-Mar-00 Updated enetInit() to enable broadcast addresses in the
45 * EMAC_RXM register. JWB
46 * 12-Mar-01 anne-sophie.harnois@nextream.fr
47 * - Variables are compatible with those already defined in
49 * - Receive buffer descriptor ring is used to send buffers
51 * - Info print about send/received/handled packet number if
52 * INFO_405_ENET is set
53 * 17-Apr-01 stefan.roese@esd-electronics.com
54 * - MAL reset in "eth_halt" included
55 * - Enet speed and duplex output now in one line
56 * 08-May-01 stefan.roese@esd-electronics.com
57 * - MAL error handling added (eth_init called again)
58 * 13-Nov-01 stefan.roese@esd-electronics.com
59 * - Set IST bit in EMAC_M1 reg upon 100MBit or full duplex
60 * 04-Jan-02 stefan.roese@esd-electronics.com
61 * - Wait for PHY auto negotiation to complete added
62 * 06-Feb-02 stefan.roese@esd-electronics.com
63 * - Bug fixed in waiting for auto negotiation to complete
64 * 26-Feb-02 stefan.roese@esd-electronics.com
65 * - rx and tx buffer descriptors now allocated (no fixed address
67 * 17-Jun-02 stefan.roese@esd-electronics.com
68 * - MAL error debug printf 'M' removed (rx de interrupt may
69 * occur upon many incoming packets with only 4 rx buffers).
70 *-----------------------------------------------------------------------------*
71 * 17-Nov-03 travis.sawyer@sandburst.com
72 * - ported from 405gp_enet.c to utilized upto 4 EMAC ports
73 * in the 440GX. This port should work with the 440GP
75 * 15-Aug-05 sr@denx.de
76 * - merged 405gp_enet.c and 440gx_enet.c to generic 4xx_enet.c
77 now handling all 4xx cpu's.
78 *-----------------------------------------------------------------------------*/
83 #include <asm/processor.h>
86 #include <ppc4xx_enet.h>
93 * Only compile for platform with AMCC EMAC ethernet controller and
94 * network support enabled.
95 * Remark: CONFIG_405 describes Xilinx PPC405 FPGA without EMAC controller!
97 #if (CONFIG_COMMANDS & CFG_CMD_NET) && !defined(CONFIG_405) && !defined(CONFIG_IOP480)
99 #if !(defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII))
100 #error "CONFIG_MII has to be defined!"
103 #if defined(CONFIG_NETCONSOLE) && !defined(CONFIG_NET_MULTI)
104 #error "CONFIG_NET_MULTI has to be defined for NetConsole"
107 #define EMAC_RESET_TIMEOUT 1000 /* 1000 ms reset timeout */
108 #define PHY_AUTONEGOTIATE_TIMEOUT 4000 /* 4000 ms autonegotiate timeout */
110 /* Ethernet Transmit and Receive Buffers */
112 * In the same way ENET_MAX_MTU and ENET_MAX_MTU_ALIGNED are set from
113 * PKTSIZE and PKTSIZE_ALIGN (include/net.h)
115 #define ENET_MAX_MTU PKTSIZE
116 #define ENET_MAX_MTU_ALIGNED PKTSIZE_ALIGN
118 /*-----------------------------------------------------------------------------+
119 * Defines for MAL/EMAC interrupt conditions as reported in the UIC (Universal
120 * Interrupt Controller).
121 *-----------------------------------------------------------------------------*/
122 #define MAL_UIC_ERR ( UIC_MAL_SERR | UIC_MAL_TXDE | UIC_MAL_RXDE)
123 #define MAL_UIC_DEF (UIC_MAL_RXEOB | MAL_UIC_ERR)
124 #define EMAC_UIC_DEF UIC_ENET
125 #define EMAC_UIC_DEF1 UIC_ENET1
126 #define SEL_UIC_DEF(p) (p ? UIC_ENET1 : UIC_ENET )
130 #define BI_PHYMODE_NONE 0
131 #define BI_PHYMODE_ZMII 1
132 #define BI_PHYMODE_RGMII 2
133 #define BI_PHYMODE_GMII 3
134 #define BI_PHYMODE_RTBI 4
135 #define BI_PHYMODE_TBI 5
136 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
137 #define BI_PHYMODE_SMII 6
138 #define BI_PHYMODE_MII 7
141 #if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
142 #define SDR0_MFR_ETH_CLK_SEL_V(n) ((0x01<<27) / (n+1))
145 /*-----------------------------------------------------------------------------+
146 * Global variables. TX and RX descriptors and buffers.
147 *-----------------------------------------------------------------------------*/
149 static uint32_t mal_ier;
151 #if !defined(CONFIG_NET_MULTI)
152 struct eth_device *emac0_dev = NULL;
156 * Get count of EMAC devices (doesn't have to be the max. possible number
157 * supported by the cpu)
159 #if defined(CONFIG_HAS_ETH3)
160 #define LAST_EMAC_NUM 4
161 #elif defined(CONFIG_HAS_ETH2)
162 #define LAST_EMAC_NUM 3
163 #elif defined(CONFIG_HAS_ETH1)
164 #define LAST_EMAC_NUM 2
166 #define LAST_EMAC_NUM 1
169 /*-----------------------------------------------------------------------------+
170 * Prototypes and externals.
171 *-----------------------------------------------------------------------------*/
172 static void enet_rcv (struct eth_device *dev, unsigned long malisr);
174 int enetInt (struct eth_device *dev);
175 static void mal_err (struct eth_device *dev, unsigned long isr,
176 unsigned long uic, unsigned long maldef,
177 unsigned long mal_errr);
178 static void emac_err (struct eth_device *dev, unsigned long isr);
180 extern int phy_setup_aneg (char *devname, unsigned char addr);
181 extern int emac4xx_miiphy_read (char *devname, unsigned char addr,
182 unsigned char reg, unsigned short *value);
183 extern int emac4xx_miiphy_write (char *devname, unsigned char addr,
184 unsigned char reg, unsigned short value);
186 /*-----------------------------------------------------------------------------+
188 | Disable MAL channel, and EMACn
189 +-----------------------------------------------------------------------------*/
190 static void ppc_4xx_eth_halt (struct eth_device *dev)
192 EMAC_4XX_HW_PST hw_p = dev->priv;
193 uint32_t failsafe = 10000;
194 #if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
198 out32 (EMAC_IER + hw_p->hw_addr, 0x00000000); /* disable emac interrupts */
200 /* 1st reset MAL channel */
201 /* Note: writing a 0 to a channel has no effect */
202 #if defined(CONFIG_405EP) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
203 mtdcr (maltxcarr, (MAL_CR_MMSR >> (hw_p->devnum * 2)));
205 mtdcr (maltxcarr, (MAL_CR_MMSR >> hw_p->devnum));
207 mtdcr (malrxcarr, (MAL_CR_MMSR >> hw_p->devnum));
210 while (mfdcr (malrxcasr) & (MAL_CR_MMSR >> hw_p->devnum)) {
211 udelay (1000); /* Delay 1 MS so as not to hammer the register */
218 #if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
219 /* provide clocks for EMAC internal loopback */
220 mfsdr (sdr_mfr, mfr);
221 mfr |= SDR0_MFR_ETH_CLK_SEL_V(hw_p->devnum);
225 out32 (EMAC_M0 + hw_p->hw_addr, EMAC_M0_SRST);
227 #if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
228 /* remove clocks for EMAC internal loopback */
229 mfsdr (sdr_mfr, mfr);
230 mfr &= ~SDR0_MFR_ETH_CLK_SEL_V(hw_p->devnum);
235 #ifndef CONFIG_NETCONSOLE
236 hw_p->print_speed = 1; /* print speed message again next time */
242 #if defined (CONFIG_440GX)
243 int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis)
246 unsigned long zmiifer;
247 unsigned long rmiifer;
249 mfsdr(sdr_pfc1, pfc1);
250 pfc1 = SDR0_PFC1_EPS_DECODE(pfc1);
257 zmiifer |= ZMII_FER_RMII << ZMII_FER_V(0);
258 zmiifer |= ZMII_FER_RMII << ZMII_FER_V(1);
259 zmiifer |= ZMII_FER_RMII << ZMII_FER_V(2);
260 zmiifer |= ZMII_FER_RMII << ZMII_FER_V(3);
261 bis->bi_phymode[0] = BI_PHYMODE_ZMII;
262 bis->bi_phymode[1] = BI_PHYMODE_ZMII;
263 bis->bi_phymode[2] = BI_PHYMODE_ZMII;
264 bis->bi_phymode[3] = BI_PHYMODE_ZMII;
267 zmiifer = ZMII_FER_SMII << ZMII_FER_V(0);
268 zmiifer = ZMII_FER_SMII << ZMII_FER_V(1);
269 zmiifer = ZMII_FER_SMII << ZMII_FER_V(2);
270 zmiifer = ZMII_FER_SMII << ZMII_FER_V(3);
271 bis->bi_phymode[0] = BI_PHYMODE_ZMII;
272 bis->bi_phymode[1] = BI_PHYMODE_ZMII;
273 bis->bi_phymode[2] = BI_PHYMODE_ZMII;
274 bis->bi_phymode[3] = BI_PHYMODE_ZMII;
277 zmiifer |= ZMII_FER_RMII << ZMII_FER_V(0);
278 rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(2);
279 bis->bi_phymode[0] = BI_PHYMODE_ZMII;
280 bis->bi_phymode[1] = BI_PHYMODE_NONE;
281 bis->bi_phymode[2] = BI_PHYMODE_RGMII;
282 bis->bi_phymode[3] = BI_PHYMODE_NONE;
285 zmiifer |= ZMII_FER_SMII << ZMII_FER_V(0);
286 zmiifer |= ZMII_FER_SMII << ZMII_FER_V(1);
287 rmiifer |= RGMII_FER_RGMII << RGMII_FER_V (2);
288 rmiifer |= RGMII_FER_RGMII << RGMII_FER_V (3);
289 bis->bi_phymode[0] = BI_PHYMODE_ZMII;
290 bis->bi_phymode[1] = BI_PHYMODE_ZMII;
291 bis->bi_phymode[2] = BI_PHYMODE_RGMII;
292 bis->bi_phymode[3] = BI_PHYMODE_RGMII;
295 zmiifer |= ZMII_FER_SMII << ZMII_FER_V (0);
296 zmiifer |= ZMII_FER_SMII << ZMII_FER_V (1);
297 zmiifer |= ZMII_FER_SMII << ZMII_FER_V (2);
298 rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(3);
299 bis->bi_phymode[0] = BI_PHYMODE_ZMII;
300 bis->bi_phymode[1] = BI_PHYMODE_ZMII;
301 bis->bi_phymode[2] = BI_PHYMODE_ZMII;
302 bis->bi_phymode[3] = BI_PHYMODE_RGMII;
305 zmiifer |= ZMII_FER_SMII << ZMII_FER_V (0);
306 zmiifer |= ZMII_FER_SMII << ZMII_FER_V (1);
307 rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(2);
308 bis->bi_phymode[0] = BI_PHYMODE_ZMII;
309 bis->bi_phymode[1] = BI_PHYMODE_ZMII;
310 bis->bi_phymode[2] = BI_PHYMODE_RGMII;
314 zmiifer = ZMII_FER_MII << ZMII_FER_V(devnum);
316 bis->bi_phymode[0] = BI_PHYMODE_ZMII;
317 bis->bi_phymode[1] = BI_PHYMODE_ZMII;
318 bis->bi_phymode[2] = BI_PHYMODE_ZMII;
319 bis->bi_phymode[3] = BI_PHYMODE_ZMII;
323 /* Ensure we setup mdio for this devnum and ONLY this devnum */
324 zmiifer |= (ZMII_FER_MDI) << ZMII_FER_V(devnum);
326 out32 (ZMII_FER, zmiifer);
327 out32 (RGMII_FER, rmiifer);
331 #endif /* CONFIG_440_GX */
333 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
334 int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis)
336 unsigned long zmiifer=0x0;
339 * Right now only 2*RGMII is supported. Please extend when needed.
345 out32 (ZMII_FER, 0x00);
346 out32 (RGMII_FER, 0x00000037);
347 bis->bi_phymode[0] = BI_PHYMODE_GMII;
348 bis->bi_phymode[1] = BI_PHYMODE_NONE;
351 /* 2 x RGMII ports */
352 out32 (ZMII_FER, 0x00);
353 out32 (RGMII_FER, 0x00000055);
354 bis->bi_phymode[0] = BI_PHYMODE_RGMII;
355 bis->bi_phymode[1] = BI_PHYMODE_RGMII;
365 /* Ensure we setup mdio for this devnum and ONLY this devnum */
366 zmiifer = in32 (ZMII_FER);
367 zmiifer |= (ZMII_FER_MDI) << ZMII_FER_V(devnum);
368 out32 (ZMII_FER, zmiifer);
372 #endif /* CONFIG_440EPX */
374 static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
377 unsigned long reg = 0;
380 unsigned long duplex;
381 unsigned long failsafe;
383 unsigned short devnum;
384 unsigned short reg_short;
385 #if defined(CONFIG_440GX) || \
386 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
387 defined(CONFIG_440SP) || defined(CONFIG_440SPE)
389 #if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \
390 defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
394 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || defined(CONFIG_440SPE)
399 EMAC_4XX_HW_PST hw_p = dev->priv;
401 /* before doing anything, figure out if we have a MAC address */
403 if (memcmp (dev->enetaddr, "\0\0\0\0\0\0", 6) == 0) {
404 printf("ERROR: ethaddr not set!\n");
408 #if defined(CONFIG_440GX) || \
409 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
410 defined(CONFIG_440SP) || defined(CONFIG_440SPE)
411 /* Need to get the OPB frequency so we can access the PHY */
412 get_sys_info (&sysinfo);
416 mtmsr (msr & ~(MSR_EE)); /* disable interrupts */
418 devnum = hw_p->devnum;
423 * hw_p->stats.pkts_handled <= hw_p->stats.pkts_rx <= hw_p->stats.pkts_handled+PKTBUFSRX
424 * In the most cases hw_p->stats.pkts_handled = hw_p->stats.pkts_rx, but it
425 * is possible that new packets (without relationship with
426 * current transfer) have got the time to arrived before
427 * netloop calls eth_halt
429 printf ("About preceeding transfer (eth%d):\n"
430 "- Sent packet number %d\n"
431 "- Received packet number %d\n"
432 "- Handled packet number %d\n",
435 hw_p->stats.pkts_rx, hw_p->stats.pkts_handled);
437 hw_p->stats.pkts_tx = 0;
438 hw_p->stats.pkts_rx = 0;
439 hw_p->stats.pkts_handled = 0;
440 hw_p->print_speed = 1; /* print speed message again next time */
443 hw_p->tx_err_index = 0; /* Transmit Error Index for tx_err_log */
444 hw_p->rx_err_index = 0; /* Receive Error Index for rx_err_log */
446 hw_p->rx_slot = 0; /* MAL Receive Slot */
447 hw_p->rx_i_index = 0; /* Receive Interrupt Queue Index */
448 hw_p->rx_u_index = 0; /* Receive User Queue Index */
450 hw_p->tx_slot = 0; /* MAL Transmit Slot */
451 hw_p->tx_i_index = 0; /* Transmit Interrupt Queue Index */
452 hw_p->tx_u_index = 0; /* Transmit User Queue Index */
454 #if defined(CONFIG_440) && !defined(CONFIG_440SP) && !defined(CONFIG_440SPE)
456 /* NOTE: 440GX spec states that mode is mutually exclusive */
457 /* NOTE: Therefore, disable all other EMACS, since we handle */
458 /* NOTE: only one emac at a time */
463 #if defined(CONFIG_440EP) || defined(CONFIG_440GR)
464 out32 (ZMII_FER, (ZMII_FER_RMII | ZMII_FER_MDI) << ZMII_FER_V (devnum));
465 #elif defined(CONFIG_440GX) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
466 ethgroup = ppc_4xx_eth_setup_bridge(devnum, bis);
467 #elif defined(CONFIG_440GP)
469 out32 (ZMII_FER, ZMII_RMII | ZMII_MDI0);
471 if ((devnum == 0) || (devnum == 1)) {
472 out32 (ZMII_FER, (ZMII_FER_SMII | ZMII_FER_MDI) << ZMII_FER_V (devnum));
473 } else { /* ((devnum == 2) || (devnum == 3)) */
474 out32 (ZMII_FER, ZMII_FER_MDI << ZMII_FER_V (devnum));
475 out32 (RGMII_FER, ((RGMII_FER_RGMII << RGMII_FER_V (2)) |
476 (RGMII_FER_RGMII << RGMII_FER_V (3))));
480 out32 (ZMII_SSR, ZMII_SSR_SP << ZMII_SSR_V(devnum));
481 #endif /* defined(CONFIG_440) && !defined(CONFIG_440SP) */
483 __asm__ volatile ("eieio");
485 /* reset emac so we have access to the phy */
486 #if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
487 /* provide clocks for EMAC internal loopback */
488 mfsdr (sdr_mfr, mfr);
489 mfr |= SDR0_MFR_ETH_CLK_SEL_V(devnum);
493 out32 (EMAC_M0 + hw_p->hw_addr, EMAC_M0_SRST);
494 __asm__ volatile ("eieio");
497 while ((in32 (EMAC_M0 + hw_p->hw_addr) & (EMAC_M0_SRST)) && failsafe) {
502 printf("\nProblem resetting EMAC!\n");
504 #if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
505 /* remove clocks for EMAC internal loopback */
506 mfsdr (sdr_mfr, mfr);
507 mfr &= ~SDR0_MFR_ETH_CLK_SEL_V(devnum);
511 #if defined(CONFIG_440GX) || \
512 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
513 defined(CONFIG_440SP) || defined(CONFIG_440SPE)
514 /* Whack the M1 register */
516 mode_reg &= ~0x00000038;
517 if (sysinfo.freqOPB <= 50000000);
518 else if (sysinfo.freqOPB <= 66666667)
519 mode_reg |= EMAC_M1_OBCI_66;
520 else if (sysinfo.freqOPB <= 83333333)
521 mode_reg |= EMAC_M1_OBCI_83;
522 else if (sysinfo.freqOPB <= 100000000)
523 mode_reg |= EMAC_M1_OBCI_100;
525 mode_reg |= EMAC_M1_OBCI_GT100;
527 out32 (EMAC_M1 + hw_p->hw_addr, mode_reg);
528 #endif /* defined(CONFIG_440GX) || defined(CONFIG_440SP) */
530 /* wait for PHY to complete auto negotiation */
532 #ifndef CONFIG_CS8952_PHY
535 reg = CONFIG_PHY_ADDR;
537 #if defined (CONFIG_PHY1_ADDR)
539 reg = CONFIG_PHY1_ADDR;
542 #if defined (CONFIG_440GX)
544 reg = CONFIG_PHY2_ADDR;
547 reg = CONFIG_PHY3_ADDR;
551 reg = CONFIG_PHY_ADDR;
555 bis->bi_phynum[devnum] = reg;
557 #if defined(CONFIG_PHY_RESET)
559 * Reset the phy, only if its the first time through
560 * otherwise, just check the speeds & feeds
562 if (hw_p->first_init == 0) {
563 #if defined(CONFIG_88E1111_CLK_DELAY)
565 * On some boards (e.g. ALPR) the Marvell 88E1111 PHY needs
566 * the "RGMII transmit timing control" and "RGMII receive
567 * timing control" bits set, so that Gbit communication works
569 * Also set the "Transmitter disable" to 1 to enable the
571 * After setting these bits a soft-reset must occur for this
572 * change to become active.
574 miiphy_read (dev->name, reg, 0x14, ®_short);
575 reg_short |= (1 << 7) | (1 << 1) | (1 << 0);
576 miiphy_write (dev->name, reg, 0x14, reg_short);
578 #if defined(CONFIG_M88E1111_PHY) /* test-only: merge with CONFIG_88E1111_CLK_DELAY !!! */
579 miiphy_write (dev->name, reg, 0x14, 0x0ce3);
580 miiphy_write (dev->name, reg, 0x18, 0x4101);
581 miiphy_write (dev->name, reg, 0x09, 0x0e00);
582 miiphy_write (dev->name, reg, 0x04, 0x01e1);
584 miiphy_reset (dev->name, reg);
586 #if defined(CONFIG_440GX) || \
587 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
588 defined(CONFIG_440SP) || defined(CONFIG_440SPE)
590 #if defined(CONFIG_CIS8201_PHY)
592 * Cicada 8201 PHY needs to have an extended register whacked
595 if (((devnum == 2) || (devnum == 3)) && (4 == ethgroup)) {
596 #if defined(CONFIG_CIS8201_SHORT_ETCH)
597 miiphy_write (dev->name, reg, 23, 0x1300);
599 miiphy_write (dev->name, reg, 23, 0x1000);
602 * Vitesse VSC8201/Cicada CIS8201 errata:
603 * Interoperability problem with Intel 82547EI phys
604 * This work around (provided by Vitesse) changes
605 * the default timer convergence from 8ms to 12ms
607 miiphy_write (dev->name, reg, 0x1f, 0x2a30);
608 miiphy_write (dev->name, reg, 0x08, 0x0200);
609 miiphy_write (dev->name, reg, 0x1f, 0x52b5);
610 miiphy_write (dev->name, reg, 0x02, 0x0004);
611 miiphy_write (dev->name, reg, 0x01, 0x0671);
612 miiphy_write (dev->name, reg, 0x00, 0x8fae);
613 miiphy_write (dev->name, reg, 0x1f, 0x2a30);
614 miiphy_write (dev->name, reg, 0x08, 0x0000);
615 miiphy_write (dev->name, reg, 0x1f, 0x0000);
616 /* end Vitesse/Cicada errata */
620 /* Start/Restart autonegotiation */
621 phy_setup_aneg (dev->name, reg);
624 #endif /* defined(CONFIG_PHY_RESET) */
626 miiphy_read (dev->name, reg, PHY_BMSR, ®_short);
629 * Wait if PHY is capable of autonegotiation and autonegotiation is not complete
631 if ((reg_short & PHY_BMSR_AUTN_ABLE)
632 && !(reg_short & PHY_BMSR_AUTN_COMP)) {
633 puts ("Waiting for PHY auto negotiation to complete");
635 while (!(reg_short & PHY_BMSR_AUTN_COMP)) {
639 if (i > PHY_AUTONEGOTIATE_TIMEOUT) {
640 puts (" TIMEOUT !\n");
644 if ((i++ % 1000) == 0) {
647 udelay (1000); /* 1 ms */
648 miiphy_read (dev->name, reg, PHY_BMSR, ®_short);
652 udelay (500000); /* another 500 ms (results in faster booting) */
654 #endif /* #ifndef CONFIG_CS8952_PHY */
656 speed = miiphy_speed (dev->name, reg);
657 duplex = miiphy_duplex (dev->name, reg);
659 if (hw_p->print_speed) {
660 hw_p->print_speed = 0;
661 printf ("ENET Speed is %d Mbps - %s duplex connection\n",
662 (int) speed, (duplex == HALF) ? "HALF" : "FULL");
665 #if defined(CONFIG_440) && !defined(CONFIG_440SP) && !defined(CONFIG_440SPE) && \
666 !defined(CONFIG_440EPX) && !defined(CONFIG_440GRX)
667 #if defined(CONFIG_440EP) || defined(CONFIG_440GR)
670 reg = (reg & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_RMII_100M;
672 reg = (reg & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_RMII_10M;
677 /* Set ZMII/RGMII speed according to the phy link speed */
678 reg = in32 (ZMII_SSR);
679 if ( (speed == 100) || (speed == 1000) )
680 out32 (ZMII_SSR, reg | (ZMII_SSR_SP << ZMII_SSR_V (devnum)));
682 out32 (ZMII_SSR, reg & (~(ZMII_SSR_SP << ZMII_SSR_V (devnum))));
684 if ((devnum == 2) || (devnum == 3)) {
686 reg = (RGMII_SSR_SP_1000MBPS << RGMII_SSR_V (devnum));
687 else if (speed == 100)
688 reg = (RGMII_SSR_SP_100MBPS << RGMII_SSR_V (devnum));
689 else if (speed == 10)
690 reg = (RGMII_SSR_SP_10MBPS << RGMII_SSR_V (devnum));
692 printf("Error in RGMII Speed\n");
695 out32 (RGMII_SSR, reg);
697 #endif /* defined(CONFIG_440) && !defined(CONFIG_440SP) */
699 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
701 reg = (RGMII_SSR_SP_1000MBPS << RGMII_SSR_V (devnum));
702 else if (speed == 100)
703 reg = (RGMII_SSR_SP_100MBPS << RGMII_SSR_V (devnum));
704 else if (speed == 10)
705 reg = (RGMII_SSR_SP_10MBPS << RGMII_SSR_V (devnum));
707 printf("Error in RGMII Speed\n");
710 out32 (RGMII_SSR, reg);
713 /* set the Mal configuration reg */
714 #if defined(CONFIG_440GX) || \
715 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
716 defined(CONFIG_440SP) || defined(CONFIG_440SPE)
717 mtdcr (malmcr, MAL_CR_PLBB | MAL_CR_OPBBL | MAL_CR_LEA |
718 MAL_CR_PLBLT_DEFAULT | MAL_CR_EOPIE | 0x00330000);
720 mtdcr (malmcr, MAL_CR_PLBB | MAL_CR_OPBBL | MAL_CR_LEA | MAL_CR_PLBLT_DEFAULT);
721 /* Errata 1.12: MAL_1 -- Disable MAL bursting */
722 if (get_pvr() == PVR_440GP_RB) {
723 mtdcr (malmcr, mfdcr(malmcr) & ~MAL_CR_PLBB);
727 /* Free "old" buffers */
728 if (hw_p->alloc_tx_buf)
729 free (hw_p->alloc_tx_buf);
730 if (hw_p->alloc_rx_buf)
731 free (hw_p->alloc_rx_buf);
734 * Malloc MAL buffer desciptors, make sure they are
735 * aligned on cache line boundary size
736 * (401/403/IOP480 = 16, 405 = 32)
737 * and doesn't cross cache block boundaries.
740 (mal_desc_t *) malloc ((sizeof (mal_desc_t) * NUM_TX_BUFF) +
741 ((2 * CFG_CACHELINE_SIZE) - 2));
742 if (NULL == hw_p->alloc_tx_buf)
744 if (((int) hw_p->alloc_tx_buf & CACHELINE_MASK) != 0) {
746 (mal_desc_t *) ((int) hw_p->alloc_tx_buf +
749 alloc_tx_buf & CACHELINE_MASK));
751 hw_p->tx = hw_p->alloc_tx_buf;
755 (mal_desc_t *) malloc ((sizeof (mal_desc_t) * NUM_RX_BUFF) +
756 ((2 * CFG_CACHELINE_SIZE) - 2));
757 if (NULL == hw_p->alloc_rx_buf) {
758 free(hw_p->alloc_tx_buf);
759 hw_p->alloc_tx_buf = NULL;
763 if (((int) hw_p->alloc_rx_buf & CACHELINE_MASK) != 0) {
765 (mal_desc_t *) ((int) hw_p->alloc_rx_buf +
768 alloc_rx_buf & CACHELINE_MASK));
770 hw_p->rx = hw_p->alloc_rx_buf;
773 for (i = 0; i < NUM_TX_BUFF; i++) {
774 hw_p->tx[i].ctrl = 0;
775 hw_p->tx[i].data_len = 0;
776 if (hw_p->first_init == 0) {
778 (char *) malloc (ENET_MAX_MTU_ALIGNED);
779 if (NULL == hw_p->txbuf_ptr) {
780 free(hw_p->alloc_rx_buf);
781 free(hw_p->alloc_tx_buf);
782 hw_p->alloc_rx_buf = NULL;
783 hw_p->alloc_tx_buf = NULL;
784 for(j = 0; j < i; j++) {
785 free(hw_p->tx[i].data_ptr);
786 hw_p->tx[i].data_ptr = NULL;
790 hw_p->tx[i].data_ptr = hw_p->txbuf_ptr;
791 if ((NUM_TX_BUFF - 1) == i)
792 hw_p->tx[i].ctrl |= MAL_TX_CTRL_WRAP;
793 hw_p->tx_run[i] = -1;
795 printf ("TX_BUFF %d @ 0x%08lx\n", i,
796 (ulong) hw_p->tx[i].data_ptr);
800 for (i = 0; i < NUM_RX_BUFF; i++) {
801 hw_p->rx[i].ctrl = 0;
802 hw_p->rx[i].data_len = 0;
803 /* rx[i].data_ptr = (char *) &rx_buff[i]; */
804 hw_p->rx[i].data_ptr = (char *) NetRxPackets[i];
805 if ((NUM_RX_BUFF - 1) == i)
806 hw_p->rx[i].ctrl |= MAL_RX_CTRL_WRAP;
807 hw_p->rx[i].ctrl |= MAL_RX_CTRL_EMPTY | MAL_RX_CTRL_INTR;
808 hw_p->rx_ready[i] = -1;
810 printf ("RX_BUFF %d @ 0x%08lx\n", i, (ulong) hw_p->rx[i].data_ptr);
816 reg |= dev->enetaddr[0]; /* set high address */
818 reg |= dev->enetaddr[1];
820 out32 (EMAC_IAH + hw_p->hw_addr, reg);
823 reg |= dev->enetaddr[2]; /* set low address */
825 reg |= dev->enetaddr[3];
827 reg |= dev->enetaddr[4];
829 reg |= dev->enetaddr[5];
831 out32 (EMAC_IAL + hw_p->hw_addr, reg);
835 /* setup MAL tx & rx channel pointers */
836 #if defined (CONFIG_405EP) || defined (CONFIG_440EP) || defined (CONFIG_440GR)
837 mtdcr (maltxctp2r, hw_p->tx);
839 mtdcr (maltxctp1r, hw_p->tx);
841 #if defined(CONFIG_440)
842 mtdcr (maltxbattr, 0x0);
843 mtdcr (malrxbattr, 0x0);
845 mtdcr (malrxctp1r, hw_p->rx);
846 /* set RX buffer size */
847 mtdcr (malrcbs1, ENET_MAX_MTU_ALIGNED / 16);
849 #if defined (CONFIG_440GX)
851 /* setup MAL tx & rx channel pointers */
852 mtdcr (maltxbattr, 0x0);
853 mtdcr (malrxbattr, 0x0);
854 mtdcr (maltxctp2r, hw_p->tx);
855 mtdcr (malrxctp2r, hw_p->rx);
856 /* set RX buffer size */
857 mtdcr (malrcbs2, ENET_MAX_MTU_ALIGNED / 16);
860 /* setup MAL tx & rx channel pointers */
861 mtdcr (maltxbattr, 0x0);
862 mtdcr (maltxctp3r, hw_p->tx);
863 mtdcr (malrxbattr, 0x0);
864 mtdcr (malrxctp3r, hw_p->rx);
865 /* set RX buffer size */
866 mtdcr (malrcbs3, ENET_MAX_MTU_ALIGNED / 16);
868 #endif /* CONFIG_440GX */
871 /* setup MAL tx & rx channel pointers */
872 #if defined(CONFIG_440)
873 mtdcr (maltxbattr, 0x0);
874 mtdcr (malrxbattr, 0x0);
876 mtdcr (maltxctp0r, hw_p->tx);
877 mtdcr (malrxctp0r, hw_p->rx);
878 /* set RX buffer size */
879 mtdcr (malrcbs0, ENET_MAX_MTU_ALIGNED / 16);
883 /* Enable MAL transmit and receive channels */
884 #if defined(CONFIG_405EP) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
885 mtdcr (maltxcasr, (MAL_TXRX_CASR >> (hw_p->devnum*2)));
887 mtdcr (maltxcasr, (MAL_TXRX_CASR >> hw_p->devnum));
889 mtdcr (malrxcasr, (MAL_TXRX_CASR >> hw_p->devnum));
891 /* set transmit enable & receive enable */
892 out32 (EMAC_M0 + hw_p->hw_addr, EMAC_M0_TXE | EMAC_M0_RXE);
894 /* set receive fifo to 4k and tx fifo to 2k */
895 mode_reg = in32 (EMAC_M1 + hw_p->hw_addr);
896 mode_reg |= EMAC_M1_RFS_4K | EMAC_M1_TX_FIFO_2K;
899 if (speed == _1000BASET) {
900 #if defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
901 defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
904 mfsdr (sdr_pfc1, pfc1);
905 pfc1 |= SDR0_PFC1_EM_1000;
906 mtsdr (sdr_pfc1, pfc1);
908 mode_reg = mode_reg | EMAC_M1_MF_1000MBPS | EMAC_M1_IST;
909 } else if (speed == _100BASET)
910 mode_reg = mode_reg | EMAC_M1_MF_100MBPS | EMAC_M1_IST;
912 mode_reg = mode_reg & ~0x00C00000; /* 10 MBPS */
914 mode_reg = mode_reg | 0x80000000 | EMAC_M1_IST;
916 out32 (EMAC_M1 + hw_p->hw_addr, mode_reg);
918 /* Enable broadcast and indvidual address */
919 /* TBS: enabling runts as some misbehaved nics will send runts */
920 out32 (EMAC_RXM + hw_p->hw_addr, EMAC_RMR_BAE | EMAC_RMR_IAE);
922 /* we probably need to set the tx mode1 reg? maybe at tx time */
924 /* set transmit request threshold register */
925 out32 (EMAC_TRTR + hw_p->hw_addr, 0x18000000); /* 256 byte threshold */
927 /* set receive low/high water mark register */
928 #if defined(CONFIG_440)
929 /* 440s has a 64 byte burst length */
930 out32 (EMAC_RX_HI_LO_WMARK + hw_p->hw_addr, 0x80009000);
932 /* 405s have a 16 byte burst length */
933 out32 (EMAC_RX_HI_LO_WMARK + hw_p->hw_addr, 0x0f002000);
934 #endif /* defined(CONFIG_440) */
935 out32 (EMAC_TXM1 + hw_p->hw_addr, 0xf8640000);
937 /* Set fifo limit entry in tx mode 0 */
938 out32 (EMAC_TXM0 + hw_p->hw_addr, 0x00000003);
940 out32 (EMAC_I_FRAME_GAP_REG + hw_p->hw_addr, 0x00000008);
943 hw_p->emac_ier = EMAC_ISR_PTLE | EMAC_ISR_BFCS | EMAC_ISR_ORE | EMAC_ISR_IRE;
944 if (speed == _100BASET)
945 hw_p->emac_ier = hw_p->emac_ier | EMAC_ISR_SYE;
947 out32 (EMAC_ISR + hw_p->hw_addr, 0xffffffff); /* clear pending interrupts */
948 out32 (EMAC_IER + hw_p->hw_addr, hw_p->emac_ier);
950 if (hw_p->first_init == 0) {
952 * Connect interrupt service routines
954 irq_install_handler (VECNUM_ETH0 + (hw_p->devnum * 2),
955 (interrupt_handler_t *) enetInt, dev);
958 mtmsr (msr); /* enable interrupts again */
961 hw_p->first_init = 1;
967 static int ppc_4xx_eth_send (struct eth_device *dev, volatile void *ptr,
970 struct enet_frame *ef_ptr;
971 ulong time_start, time_now;
972 unsigned long temp_txm0;
973 EMAC_4XX_HW_PST hw_p = dev->priv;
975 ef_ptr = (struct enet_frame *) ptr;
977 /*-----------------------------------------------------------------------+
978 * Copy in our address into the frame.
979 *-----------------------------------------------------------------------*/
980 (void) memcpy (ef_ptr->source_addr, dev->enetaddr, ENET_ADDR_LENGTH);
982 /*-----------------------------------------------------------------------+
983 * If frame is too long or too short, modify length.
984 *-----------------------------------------------------------------------*/
985 /* TBS: where does the fragment go???? */
986 if (len > ENET_MAX_MTU)
989 /* memcpy ((void *) &tx_buff[tx_slot], (const void *) ptr, len); */
990 memcpy ((void *) hw_p->txbuf_ptr, (const void *) ptr, len);
992 /*-----------------------------------------------------------------------+
993 * set TX Buffer busy, and send it
994 *-----------------------------------------------------------------------*/
995 hw_p->tx[hw_p->tx_slot].ctrl = (MAL_TX_CTRL_LAST |
996 EMAC_TX_CTRL_GFCS | EMAC_TX_CTRL_GP) &
997 ~(EMAC_TX_CTRL_ISA | EMAC_TX_CTRL_RSA);
998 if ((NUM_TX_BUFF - 1) == hw_p->tx_slot)
999 hw_p->tx[hw_p->tx_slot].ctrl |= MAL_TX_CTRL_WRAP;
1001 hw_p->tx[hw_p->tx_slot].data_len = (short) len;
1002 hw_p->tx[hw_p->tx_slot].ctrl |= MAL_TX_CTRL_READY;
1004 __asm__ volatile ("eieio");
1006 out32 (EMAC_TXM0 + hw_p->hw_addr,
1007 in32 (EMAC_TXM0 + hw_p->hw_addr) | EMAC_TXM0_GNP0);
1008 #ifdef INFO_4XX_ENET
1009 hw_p->stats.pkts_tx++;
1012 /*-----------------------------------------------------------------------+
1013 * poll unitl the packet is sent and then make sure it is OK
1014 *-----------------------------------------------------------------------*/
1015 time_start = get_timer (0);
1017 temp_txm0 = in32 (EMAC_TXM0 + hw_p->hw_addr);
1018 /* loop until either TINT turns on or 3 seconds elapse */
1019 if ((temp_txm0 & EMAC_TXM0_GNP0) != 0) {
1020 /* transmit is done, so now check for errors
1021 * If there is an error, an interrupt should
1022 * happen when we return
1024 time_now = get_timer (0);
1025 if ((time_now - time_start) > 3000) {
1035 #if defined (CONFIG_440)
1037 #if defined(CONFIG_440SP) || defined(CONFIG_440SPE)
1039 * Hack: On 440SP all enet irq sources are located on UIC1
1040 * Needs some cleanup. --sr
1042 #define UIC0MSR uic1msr
1043 #define UIC0SR uic1sr
1045 #define UIC0MSR uic0msr
1046 #define UIC0SR uic0sr
1049 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
1050 #define UICMSR_ETHX uic0msr
1051 #define UICSR_ETHX uic0sr
1053 #define UICMSR_ETHX uic1msr
1054 #define UICSR_ETHX uic1sr
1057 int enetInt (struct eth_device *dev)
1060 int rc = -1; /* default to not us */
1061 unsigned long mal_isr;
1062 unsigned long emac_isr = 0;
1063 unsigned long mal_rx_eob;
1064 unsigned long my_uic0msr, my_uic1msr;
1065 unsigned long my_uicmsr_ethx;
1067 #if defined(CONFIG_440GX)
1068 unsigned long my_uic2msr;
1070 EMAC_4XX_HW_PST hw_p;
1073 * Because the mal is generic, we need to get the current
1076 #if defined(CONFIG_NET_MULTI)
1077 dev = eth_get_dev();
1084 /* enter loop that stays in interrupt code until nothing to service */
1088 my_uic0msr = mfdcr (UIC0MSR);
1089 my_uic1msr = mfdcr (uic1msr);
1090 #if defined(CONFIG_440GX)
1091 my_uic2msr = mfdcr (uic2msr);
1093 my_uicmsr_ethx = mfdcr (UICMSR_ETHX);
1095 if (!(my_uic0msr & (UIC_MRE | UIC_MTE))
1096 && !(my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))
1097 && !(my_uicmsr_ethx & (UIC_ETH0 | UIC_ETH1))) {
1101 #if defined (CONFIG_440GX)
1102 if (!(my_uic0msr & (UIC_MRE | UIC_MTE))
1103 && !(my_uic2msr & (UIC_ETH2 | UIC_ETH3))) {
1108 /* get and clear controller status interrupts */
1109 /* look at Mal and EMAC interrupts */
1110 if ((my_uic0msr & (UIC_MRE | UIC_MTE))
1111 || (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) {
1112 /* we have a MAL interrupt */
1113 mal_isr = mfdcr (malesr);
1114 /* look for mal error */
1115 if (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE)) {
1116 mal_err (dev, mal_isr, my_uic1msr, MAL_UIC_DEF, MAL_UIC_ERR);
1122 /* port by port dispatch of emac interrupts */
1123 if (hw_p->devnum == 0) {
1124 if (UIC_ETH0 & my_uicmsr_ethx) { /* look for EMAC errors */
1125 emac_isr = in32 (EMAC_ISR + hw_p->hw_addr);
1126 if ((hw_p->emac_ier & emac_isr) != 0) {
1127 emac_err (dev, emac_isr);
1132 if ((hw_p->emac_ier & emac_isr)
1133 || (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) {
1134 mtdcr (UIC0SR, UIC_MRE | UIC_MTE); /* Clear */
1135 mtdcr (uic1sr, UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */
1136 mtdcr (UICSR_ETHX, UIC_ETH0); /* Clear */
1137 return (rc); /* we had errors so get out */
1141 #if !defined(CONFIG_440SP)
1142 if (hw_p->devnum == 1) {
1143 if (UIC_ETH1 & my_uicmsr_ethx) { /* look for EMAC errors */
1144 emac_isr = in32 (EMAC_ISR + hw_p->hw_addr);
1145 if ((hw_p->emac_ier & emac_isr) != 0) {
1146 emac_err (dev, emac_isr);
1151 if ((hw_p->emac_ier & emac_isr)
1152 || (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) {
1153 mtdcr (UIC0SR, UIC_MRE | UIC_MTE); /* Clear */
1154 mtdcr (uic1sr, UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */
1155 mtdcr (UICSR_ETHX, UIC_ETH1); /* Clear */
1156 return (rc); /* we had errors so get out */
1159 #if defined (CONFIG_440GX)
1160 if (hw_p->devnum == 2) {
1161 if (UIC_ETH2 & my_uic2msr) { /* look for EMAC errors */
1162 emac_isr = in32 (EMAC_ISR + hw_p->hw_addr);
1163 if ((hw_p->emac_ier & emac_isr) != 0) {
1164 emac_err (dev, emac_isr);
1169 if ((hw_p->emac_ier & emac_isr)
1170 || (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) {
1171 mtdcr (UIC0SR, UIC_MRE | UIC_MTE); /* Clear */
1172 mtdcr (uic1sr, UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */
1173 mtdcr (uic2sr, UIC_ETH2);
1174 return (rc); /* we had errors so get out */
1178 if (hw_p->devnum == 3) {
1179 if (UIC_ETH3 & my_uic2msr) { /* look for EMAC errors */
1180 emac_isr = in32 (EMAC_ISR + hw_p->hw_addr);
1181 if ((hw_p->emac_ier & emac_isr) != 0) {
1182 emac_err (dev, emac_isr);
1187 if ((hw_p->emac_ier & emac_isr)
1188 || (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) {
1189 mtdcr (UIC0SR, UIC_MRE | UIC_MTE); /* Clear */
1190 mtdcr (uic1sr, UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */
1191 mtdcr (uic2sr, UIC_ETH3);
1192 return (rc); /* we had errors so get out */
1195 #endif /* CONFIG_440GX */
1196 #endif /* !CONFIG_440SP */
1198 /* handle MAX TX EOB interrupt from a tx */
1199 if (my_uic0msr & UIC_MTE) {
1200 mal_rx_eob = mfdcr (maltxeobisr);
1201 mtdcr (maltxeobisr, mal_rx_eob);
1202 mtdcr (UIC0SR, UIC_MTE);
1204 /* handle MAL RX EOB interupt from a receive */
1205 /* check for EOB on valid channels */
1206 if (my_uic0msr & UIC_MRE) {
1207 mal_rx_eob = mfdcr (malrxeobisr);
1208 if ((mal_rx_eob & (0x80000000 >> hw_p->devnum)) != 0) { /* call emac routine for channel x */
1210 mtdcr(malrxeobisr, mal_rx_eob); */
1211 enet_rcv (dev, emac_isr);
1212 /* indicate that we serviced an interrupt */
1218 mtdcr (UIC0SR, UIC_MRE); /* Clear */
1219 mtdcr (uic1sr, UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */
1220 switch (hw_p->devnum) {
1222 mtdcr (UICSR_ETHX, UIC_ETH0);
1225 mtdcr (UICSR_ETHX, UIC_ETH1);
1227 #if defined (CONFIG_440GX)
1229 mtdcr (uic2sr, UIC_ETH2);
1232 mtdcr (uic2sr, UIC_ETH3);
1234 #endif /* CONFIG_440GX */
1243 #else /* CONFIG_440 */
1245 int enetInt (struct eth_device *dev)
1248 int rc = -1; /* default to not us */
1249 unsigned long mal_isr;
1250 unsigned long emac_isr = 0;
1251 unsigned long mal_rx_eob;
1252 unsigned long my_uicmsr;
1254 EMAC_4XX_HW_PST hw_p;
1257 * Because the mal is generic, we need to get the current
1260 #if defined(CONFIG_NET_MULTI)
1261 dev = eth_get_dev();
1268 /* enter loop that stays in interrupt code until nothing to service */
1272 my_uicmsr = mfdcr (uicmsr);
1274 if ((my_uicmsr & (MAL_UIC_DEF | EMAC_UIC_DEF)) == 0) { /* not for us */
1277 /* get and clear controller status interrupts */
1278 /* look at Mal and EMAC interrupts */
1279 if ((MAL_UIC_DEF & my_uicmsr) != 0) { /* we have a MAL interrupt */
1280 mal_isr = mfdcr (malesr);
1281 /* look for mal error */
1282 if ((my_uicmsr & MAL_UIC_ERR) != 0) {
1283 mal_err (dev, mal_isr, my_uicmsr, MAL_UIC_DEF, MAL_UIC_ERR);
1289 /* port by port dispatch of emac interrupts */
1291 if ((SEL_UIC_DEF(hw_p->devnum) & my_uicmsr) != 0) { /* look for EMAC errors */
1292 emac_isr = in32 (EMAC_ISR + hw_p->hw_addr);
1293 if ((hw_p->emac_ier & emac_isr) != 0) {
1294 emac_err (dev, emac_isr);
1299 if (((hw_p->emac_ier & emac_isr) != 0) || ((MAL_UIC_ERR & my_uicmsr) != 0)) {
1300 mtdcr (uicsr, MAL_UIC_DEF | SEL_UIC_DEF(hw_p->devnum)); /* Clear */
1301 return (rc); /* we had errors so get out */
1304 /* handle MAX TX EOB interrupt from a tx */
1305 if (my_uicmsr & UIC_MAL_TXEOB) {
1306 mal_rx_eob = mfdcr (maltxeobisr);
1307 mtdcr (maltxeobisr, mal_rx_eob);
1308 mtdcr (uicsr, UIC_MAL_TXEOB);
1310 /* handle MAL RX EOB interupt from a receive */
1311 /* check for EOB on valid channels */
1312 if (my_uicmsr & UIC_MAL_RXEOB)
1314 mal_rx_eob = mfdcr (malrxeobisr);
1315 if ((mal_rx_eob & (0x80000000 >> hw_p->devnum)) != 0) { /* call emac routine for channel x */
1317 mtdcr(malrxeobisr, mal_rx_eob); */
1318 enet_rcv (dev, emac_isr);
1319 /* indicate that we serviced an interrupt */
1324 mtdcr (uicsr, MAL_UIC_DEF|EMAC_UIC_DEF|EMAC_UIC_DEF1); /* Clear */
1331 #endif /* CONFIG_440 */
1333 /*-----------------------------------------------------------------------------+
1335 *-----------------------------------------------------------------------------*/
1336 static void mal_err (struct eth_device *dev, unsigned long isr,
1337 unsigned long uic, unsigned long maldef,
1338 unsigned long mal_errr)
1340 EMAC_4XX_HW_PST hw_p = dev->priv;
1342 mtdcr (malesr, isr); /* clear interrupt */
1344 /* clear DE interrupt */
1345 mtdcr (maltxdeir, 0xC0000000);
1346 mtdcr (malrxdeir, 0x80000000);
1348 #ifdef INFO_4XX_ENET
1349 printf ("\nMAL error occured.... ISR = %lx UIC = = %lx MAL_DEF = %lx MAL_ERR= %lx \n", isr, uic, maldef, mal_errr);
1352 eth_init (hw_p->bis); /* start again... */
1355 /*-----------------------------------------------------------------------------+
1356 * EMAC Error Routine
1357 *-----------------------------------------------------------------------------*/
1358 static void emac_err (struct eth_device *dev, unsigned long isr)
1360 EMAC_4XX_HW_PST hw_p = dev->priv;
1362 printf ("EMAC%d error occured.... ISR = %lx\n", hw_p->devnum, isr);
1363 out32 (EMAC_ISR + hw_p->hw_addr, isr);
1366 /*-----------------------------------------------------------------------------+
1367 * enet_rcv() handles the ethernet receive data
1368 *-----------------------------------------------------------------------------*/
1369 static void enet_rcv (struct eth_device *dev, unsigned long malisr)
1371 struct enet_frame *ef_ptr;
1372 unsigned long data_len;
1373 unsigned long rx_eob_isr;
1374 EMAC_4XX_HW_PST hw_p = dev->priv;
1380 rx_eob_isr = mfdcr (malrxeobisr);
1381 if ((0x80000000 >> hw_p->devnum) & rx_eob_isr) {
1383 mtdcr (malrxeobisr, rx_eob_isr);
1386 while (1) { /* do all */
1389 if ((MAL_RX_CTRL_EMPTY & hw_p->rx[i].ctrl)
1390 || (loop_count >= NUM_RX_BUFF))
1394 if (NUM_RX_BUFF == hw_p->rx_slot)
1397 data_len = (unsigned long) hw_p->rx[i].data_len; /* Get len */
1399 if (data_len > ENET_MAX_MTU) /* Check len */
1402 if (EMAC_RX_ERRORS & hw_p->rx[i].ctrl) { /* Check Errors */
1404 hw_p->stats.rx_err_log[hw_p->
1407 hw_p->rx_err_index++;
1408 if (hw_p->rx_err_index ==
1410 hw_p->rx_err_index =
1413 } /* data_len < max mtu */
1415 if (!data_len) { /* no data */
1416 hw_p->rx[i].ctrl |= MAL_RX_CTRL_EMPTY; /* Free Recv Buffer */
1418 hw_p->stats.data_len_err++; /* Error at Rx */
1423 /* Check if user has already eaten buffer */
1424 /* if not => ERROR */
1425 else if (hw_p->rx_ready[hw_p->rx_i_index] != -1) {
1426 if (hw_p->is_receiving)
1427 printf ("ERROR : Receive buffers are full!\n");
1430 hw_p->stats.rx_frames++;
1431 hw_p->stats.rx += data_len;
1432 ef_ptr = (struct enet_frame *) hw_p->rx[i].
1434 #ifdef INFO_4XX_ENET
1435 hw_p->stats.pkts_rx++;
1440 hw_p->rx_ready[hw_p->rx_i_index] = i;
1442 if (NUM_RX_BUFF == hw_p->rx_i_index)
1443 hw_p->rx_i_index = 0;
1446 * free receive buffer only when
1447 * buffer has been handled (eth_rx)
1448 rx[i].ctrl |= MAL_RX_CTRL_EMPTY;
1452 } /* if EMACK_RXCHL */
1456 static int ppc_4xx_eth_rx (struct eth_device *dev)
1461 EMAC_4XX_HW_PST hw_p = dev->priv;
1463 hw_p->is_receiving = 1; /* tell driver */
1467 * use ring buffer and
1468 * get index from rx buffer desciptor queue
1470 user_index = hw_p->rx_ready[hw_p->rx_u_index];
1471 if (user_index == -1) {
1473 break; /* nothing received - leave for() loop */
1477 mtmsr (msr & ~(MSR_EE));
1479 length = hw_p->rx[user_index].data_len;
1481 /* Pass the packet up to the protocol layers. */
1482 /* NetReceive(NetRxPackets[rxIdx], length - 4); */
1483 /* NetReceive(NetRxPackets[i], length); */
1484 NetReceive (NetRxPackets[user_index], length - 4);
1485 /* Free Recv Buffer */
1486 hw_p->rx[user_index].ctrl |= MAL_RX_CTRL_EMPTY;
1487 /* Free rx buffer descriptor queue */
1488 hw_p->rx_ready[hw_p->rx_u_index] = -1;
1490 if (NUM_RX_BUFF == hw_p->rx_u_index)
1491 hw_p->rx_u_index = 0;
1493 #ifdef INFO_4XX_ENET
1494 hw_p->stats.pkts_handled++;
1497 mtmsr (msr); /* Enable IRQ's */
1500 hw_p->is_receiving = 0; /* tell driver */
1505 int ppc_4xx_eth_initialize (bd_t * bis)
1507 static int virgin = 0;
1508 struct eth_device *dev;
1510 EMAC_4XX_HW_PST hw = NULL;
1512 #if defined(CONFIG_440GX)
1515 mfsdr (sdr_pfc1, pfc1);
1516 pfc1 &= ~(0x01e00000);
1518 mtsdr (sdr_pfc1, pfc1);
1520 /* set phy num and mode */
1521 bis->bi_phynum[0] = CONFIG_PHY_ADDR;
1522 bis->bi_phymode[0] = 0;
1524 #if defined(CONFIG_PHY1_ADDR)
1525 bis->bi_phynum[1] = CONFIG_PHY1_ADDR;
1526 bis->bi_phymode[1] = 0;
1528 #if defined(CONFIG_440GX)
1529 bis->bi_phynum[2] = CONFIG_PHY2_ADDR;
1530 bis->bi_phynum[3] = CONFIG_PHY3_ADDR;
1531 bis->bi_phymode[2] = 2;
1532 bis->bi_phymode[3] = 2;
1534 ppc_4xx_eth_setup_bridge(0, bis);
1537 for (eth_num = 0; eth_num < LAST_EMAC_NUM; eth_num++) {
1539 /* See if we can actually bring up the interface, otherwise, skip it */
1541 default: /* fall through */
1543 if (memcmp (bis->bi_enetaddr, "\0\0\0\0\0\0", 6) == 0) {
1544 bis->bi_phymode[eth_num] = BI_PHYMODE_NONE;
1548 #ifdef CONFIG_HAS_ETH1
1550 if (memcmp (bis->bi_enet1addr, "\0\0\0\0\0\0", 6) == 0) {
1551 bis->bi_phymode[eth_num] = BI_PHYMODE_NONE;
1556 #ifdef CONFIG_HAS_ETH2
1558 if (memcmp (bis->bi_enet2addr, "\0\0\0\0\0\0", 6) == 0) {
1559 bis->bi_phymode[eth_num] = BI_PHYMODE_NONE;
1564 #ifdef CONFIG_HAS_ETH3
1566 if (memcmp (bis->bi_enet3addr, "\0\0\0\0\0\0", 6) == 0) {
1567 bis->bi_phymode[eth_num] = BI_PHYMODE_NONE;
1574 /* Allocate device structure */
1575 dev = (struct eth_device *) malloc (sizeof (*dev));
1577 printf ("ppc_4xx_eth_initialize: "
1578 "Cannot allocate eth_device %d\n", eth_num);
1581 memset(dev, 0, sizeof(*dev));
1583 /* Allocate our private use data */
1584 hw = (EMAC_4XX_HW_PST) malloc (sizeof (*hw));
1586 printf ("ppc_4xx_eth_initialize: "
1587 "Cannot allocate private hw data for eth_device %d",
1592 memset(hw, 0, sizeof(*hw));
1595 default: /* fall through */
1598 memcpy (dev->enetaddr, bis->bi_enetaddr, 6);
1600 #ifdef CONFIG_HAS_ETH1
1602 hw->hw_addr = 0x100;
1603 memcpy (dev->enetaddr, bis->bi_enet1addr, 6);
1606 #ifdef CONFIG_HAS_ETH2
1608 hw->hw_addr = 0x400;
1609 memcpy (dev->enetaddr, bis->bi_enet2addr, 6);
1612 #ifdef CONFIG_HAS_ETH3
1614 hw->hw_addr = 0x600;
1615 memcpy (dev->enetaddr, bis->bi_enet3addr, 6);
1620 hw->devnum = eth_num;
1621 hw->print_speed = 1;
1623 sprintf (dev->name, "ppc_4xx_eth%d", eth_num);
1624 dev->priv = (void *) hw;
1625 dev->init = ppc_4xx_eth_init;
1626 dev->halt = ppc_4xx_eth_halt;
1627 dev->send = ppc_4xx_eth_send;
1628 dev->recv = ppc_4xx_eth_rx;
1631 /* set the MAL IER ??? names may change with new spec ??? */
1632 #if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
1634 MAL_IER_PT | MAL_IER_PRE | MAL_IER_PWE |
1635 MAL_IER_DE | MAL_IER_OTE | MAL_IER_OE | MAL_IER_PE ;
1638 MAL_IER_DE | MAL_IER_NE | MAL_IER_TE |
1639 MAL_IER_OPBE | MAL_IER_PLBE;
1641 mtdcr (malesr, 0xffffffff); /* clear pending interrupts */
1642 mtdcr (maltxdeir, 0xffffffff); /* clear pending interrupts */
1643 mtdcr (malrxdeir, 0xffffffff); /* clear pending interrupts */
1644 mtdcr (malier, mal_ier);
1646 /* install MAL interrupt handler */
1647 irq_install_handler (VECNUM_MS,
1648 (interrupt_handler_t *) enetInt,
1650 irq_install_handler (VECNUM_MTE,
1651 (interrupt_handler_t *) enetInt,
1653 irq_install_handler (VECNUM_MRE,
1654 (interrupt_handler_t *) enetInt,
1656 irq_install_handler (VECNUM_TXDE,
1657 (interrupt_handler_t *) enetInt,
1659 irq_install_handler (VECNUM_RXDE,
1660 (interrupt_handler_t *) enetInt,
1665 #if defined(CONFIG_NET_MULTI)
1671 #if defined(CONFIG_NET_MULTI)
1672 #if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)
1673 miiphy_register (dev->name,
1674 emac4xx_miiphy_read, emac4xx_miiphy_write);
1677 } /* end for each supported device */
1682 #if !defined(CONFIG_NET_MULTI)
1683 void eth_halt (void) {
1685 ppc_4xx_eth_halt(emac0_dev);
1691 int eth_init (bd_t *bis)
1693 ppc_4xx_eth_initialize(bis);
1695 return ppc_4xx_eth_init(emac0_dev, bis);
1697 printf("ERROR: ethaddr not set!\n");
1702 int eth_send(volatile void *packet, int length)
1704 return (ppc_4xx_eth_send(emac0_dev, packet, length));
1709 return (ppc_4xx_eth_rx(emac0_dev));
1712 int emac4xx_miiphy_initialize (bd_t * bis)
1714 #if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)
1715 miiphy_register ("ppc_4xx_eth0",
1716 emac4xx_miiphy_read, emac4xx_miiphy_write);
1721 #endif /* !defined(CONFIG_NET_MULTI) */
1723 #endif /* #if (CONFIG_COMMANDS & CFG_CMD_NET) */