1 /*-----------------------------------------------------------------------------+
3 * This source code has been made available to you by IBM on an AS-IS
4 * basis. Anyone receiving this source is licensed under IBM
5 * copyrights to use it in any way he or she deems fit, including
6 * copying it, modifying it, compiling it, and redistributing it either
7 * with or without modifications. No license under IBM patents or
8 * patent applications is to be implied by the copyright license.
10 * Any user of this software should understand that IBM cannot provide
11 * technical support for this software and will not be responsible for
12 * any consequences resulting from the use of this software.
14 * Any person who transfers this source code or any derivative work
15 * must include the IBM copyright notice, this paragraph, and the
16 * preceding two paragraphs in the transferred software.
18 * COPYRIGHT I B M CORPORATION 1995
19 * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
20 *-----------------------------------------------------------------------------*/
21 /*-----------------------------------------------------------------------------+
23 * File Name: enetemac.c
25 * Function: Device driver for the ethernet EMAC3 macro on the 405GP.
31 * Date Description of Change BY
32 * --------- --------------------- ---
33 * 05-May-99 Created MKW
34 * 27-Jun-99 Clean up JWB
35 * 16-Jul-99 Added MAL error recovery and better IP packet handling MKW
36 * 29-Jul-99 Added Full duplex support MKW
37 * 06-Aug-99 Changed names for Mal CR reg MKW
38 * 23-Aug-99 Turned off SYE when running at 10Mbs MKW
39 * 24-Aug-99 Marked descriptor empty after call_xlc MKW
40 * 07-Sep-99 Set MAL RX buffer size reg to ENET_MAX_MTU_ALIGNED / 16 MCG
41 * to avoid chaining maximum sized packets. Push starting
42 * RX descriptor address up to the next cache line boundary.
43 * 16-Jan-00 Added support for booting with IP of 0x0 MKW
44 * 15-Mar-00 Updated enetInit() to enable broadcast addresses in the
45 * EMAC_RXM register. JWB
46 * 12-Mar-01 anne-sophie.harnois@nextream.fr
47 * - Variables are compatible with those already defined in
49 * - Receive buffer descriptor ring is used to send buffers
51 * - Info print about send/received/handled packet number if
52 * INFO_405_ENET is set
53 * 17-Apr-01 stefan.roese@esd-electronics.com
54 * - MAL reset in "eth_halt" included
55 * - Enet speed and duplex output now in one line
56 * 08-May-01 stefan.roese@esd-electronics.com
57 * - MAL error handling added (eth_init called again)
58 * 13-Nov-01 stefan.roese@esd-electronics.com
59 * - Set IST bit in EMAC_M1 reg upon 100MBit or full duplex
60 * 04-Jan-02 stefan.roese@esd-electronics.com
61 * - Wait for PHY auto negotiation to complete added
62 * 06-Feb-02 stefan.roese@esd-electronics.com
63 * - Bug fixed in waiting for auto negotiation to complete
64 * 26-Feb-02 stefan.roese@esd-electronics.com
65 * - rx and tx buffer descriptors now allocated (no fixed address
67 * 17-Jun-02 stefan.roese@esd-electronics.com
68 * - MAL error debug printf 'M' removed (rx de interrupt may
69 * occur upon many incoming packets with only 4 rx buffers).
70 *-----------------------------------------------------------------------------*
71 * 17-Nov-03 travis.sawyer@sandburst.com
72 * - ported from 405gp_enet.c to utilized upto 4 EMAC ports
73 * in the 440GX. This port should work with the 440GP
75 * 15-Aug-05 sr@denx.de
76 * - merged 405gp_enet.c and 440gx_enet.c to generic 4xx_enet.c
77 now handling all 4xx cpu's.
78 *-----------------------------------------------------------------------------*/
83 #include <asm/processor.h>
86 #include <ppc4xx_enet.h>
93 * Only compile for platform with AMCC EMAC ethernet controller and
94 * network support enabled.
95 * Remark: CONFIG_405 describes Xilinx PPC405 FPGA without EMAC controller!
97 #if defined(CONFIG_CMD_NET) && !defined(CONFIG_405) && !defined(CONFIG_IOP480)
99 #if !(defined(CONFIG_MII) || defined(CONFIG_CMD_MII))
100 #error "CONFIG_MII has to be defined!"
103 #if defined(CONFIG_NETCONSOLE) && !defined(CONFIG_NET_MULTI)
104 #error "CONFIG_NET_MULTI has to be defined for NetConsole"
107 #define EMAC_RESET_TIMEOUT 1000 /* 1000 ms reset timeout */
108 #define PHY_AUTONEGOTIATE_TIMEOUT 4000 /* 4000 ms autonegotiate timeout */
110 /* Ethernet Transmit and Receive Buffers */
112 * In the same way ENET_MAX_MTU and ENET_MAX_MTU_ALIGNED are set from
113 * PKTSIZE and PKTSIZE_ALIGN (include/net.h)
115 #define ENET_MAX_MTU PKTSIZE
116 #define ENET_MAX_MTU_ALIGNED PKTSIZE_ALIGN
118 /*-----------------------------------------------------------------------------+
119 * Defines for MAL/EMAC interrupt conditions as reported in the UIC (Universal
120 * Interrupt Controller).
121 *-----------------------------------------------------------------------------*/
122 #define MAL_UIC_ERR ( UIC_MAL_SERR | UIC_MAL_TXDE | UIC_MAL_RXDE)
123 #define MAL_UIC_DEF (UIC_MAL_RXEOB | MAL_UIC_ERR)
124 #define EMAC_UIC_DEF UIC_ENET
125 #define EMAC_UIC_DEF1 UIC_ENET1
126 #define SEL_UIC_DEF(p) (p ? UIC_ENET1 : UIC_ENET )
130 #define BI_PHYMODE_NONE 0
131 #define BI_PHYMODE_ZMII 1
132 #define BI_PHYMODE_RGMII 2
133 #define BI_PHYMODE_GMII 3
134 #define BI_PHYMODE_RTBI 4
135 #define BI_PHYMODE_TBI 5
136 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
137 defined(CONFIG_405EX)
138 #define BI_PHYMODE_SMII 6
139 #define BI_PHYMODE_MII 7
142 #if defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
143 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
144 defined(CONFIG_405EX)
145 #define SDR0_MFR_ETH_CLK_SEL_V(n) ((0x01<<27) / (n+1))
148 /*-----------------------------------------------------------------------------+
149 * Global variables. TX and RX descriptors and buffers.
150 *-----------------------------------------------------------------------------*/
152 static uint32_t mal_ier;
154 #if !defined(CONFIG_NET_MULTI)
155 struct eth_device *emac0_dev = NULL;
159 * Get count of EMAC devices (doesn't have to be the max. possible number
160 * supported by the cpu)
162 #if defined(CONFIG_HAS_ETH3)
163 #define LAST_EMAC_NUM 4
164 #elif defined(CONFIG_HAS_ETH2)
165 #define LAST_EMAC_NUM 3
166 #elif defined(CONFIG_HAS_ETH1)
167 #define LAST_EMAC_NUM 2
169 #define LAST_EMAC_NUM 1
172 /* normal boards start with EMAC0 */
173 #if !defined(CONFIG_EMAC_NR_START)
174 #define CONFIG_EMAC_NR_START 0
177 #if defined(CONFIG_405EX) || defined(CONFIG_440EPX)
178 #define ETH_IRQ_NUM(dev) (VECNUM_ETH0 + ((dev)))
180 #define ETH_IRQ_NUM(dev) (VECNUM_ETH0 + ((dev) * 2))
183 /*-----------------------------------------------------------------------------+
184 * Prototypes and externals.
185 *-----------------------------------------------------------------------------*/
186 static void enet_rcv (struct eth_device *dev, unsigned long malisr);
188 int enetInt (struct eth_device *dev);
189 static void mal_err (struct eth_device *dev, unsigned long isr,
190 unsigned long uic, unsigned long maldef,
191 unsigned long mal_errr);
192 static void emac_err (struct eth_device *dev, unsigned long isr);
194 extern int phy_setup_aneg (char *devname, unsigned char addr);
195 extern int emac4xx_miiphy_read (char *devname, unsigned char addr,
196 unsigned char reg, unsigned short *value);
197 extern int emac4xx_miiphy_write (char *devname, unsigned char addr,
198 unsigned char reg, unsigned short value);
200 /*-----------------------------------------------------------------------------+
202 | Disable MAL channel, and EMACn
203 +-----------------------------------------------------------------------------*/
204 static void ppc_4xx_eth_halt (struct eth_device *dev)
206 EMAC_4XX_HW_PST hw_p = dev->priv;
207 uint32_t failsafe = 10000;
208 #if defined(CONFIG_440SPE) || \
209 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
210 defined(CONFIG_405EX)
214 out32 (EMAC_IER + hw_p->hw_addr, 0x00000000); /* disable emac interrupts */
216 /* 1st reset MAL channel */
217 /* Note: writing a 0 to a channel has no effect */
218 #if defined(CONFIG_405EP) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
219 mtdcr (maltxcarr, (MAL_CR_MMSR >> (hw_p->devnum * 2)));
221 mtdcr (maltxcarr, (MAL_CR_MMSR >> hw_p->devnum));
223 mtdcr (malrxcarr, (MAL_CR_MMSR >> hw_p->devnum));
226 while (mfdcr (malrxcasr) & (MAL_CR_MMSR >> hw_p->devnum)) {
227 udelay (1000); /* Delay 1 MS so as not to hammer the register */
234 #if defined(CONFIG_440SPE) || \
235 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
236 defined(CONFIG_405EX)
237 /* provide clocks for EMAC internal loopback */
238 mfsdr (sdr_mfr, mfr);
239 mfr |= SDR0_MFR_ETH_CLK_SEL_V(hw_p->devnum);
243 out32 (EMAC_M0 + hw_p->hw_addr, EMAC_M0_SRST);
245 #if defined(CONFIG_440SPE) || \
246 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
247 defined(CONFIG_405EX)
248 /* remove clocks for EMAC internal loopback */
249 mfsdr (sdr_mfr, mfr);
250 mfr &= ~SDR0_MFR_ETH_CLK_SEL_V(hw_p->devnum);
255 #ifndef CONFIG_NETCONSOLE
256 hw_p->print_speed = 1; /* print speed message again next time */
262 #if defined (CONFIG_440GX)
263 int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis)
266 unsigned long zmiifer;
267 unsigned long rmiifer;
269 mfsdr(sdr_pfc1, pfc1);
270 pfc1 = SDR0_PFC1_EPS_DECODE(pfc1);
277 zmiifer |= ZMII_FER_RMII << ZMII_FER_V(0);
278 zmiifer |= ZMII_FER_RMII << ZMII_FER_V(1);
279 zmiifer |= ZMII_FER_RMII << ZMII_FER_V(2);
280 zmiifer |= ZMII_FER_RMII << ZMII_FER_V(3);
281 bis->bi_phymode[0] = BI_PHYMODE_ZMII;
282 bis->bi_phymode[1] = BI_PHYMODE_ZMII;
283 bis->bi_phymode[2] = BI_PHYMODE_ZMII;
284 bis->bi_phymode[3] = BI_PHYMODE_ZMII;
287 zmiifer |= ZMII_FER_SMII << ZMII_FER_V(0);
288 zmiifer |= ZMII_FER_SMII << ZMII_FER_V(1);
289 zmiifer |= ZMII_FER_SMII << ZMII_FER_V(2);
290 zmiifer |= ZMII_FER_SMII << ZMII_FER_V(3);
291 bis->bi_phymode[0] = BI_PHYMODE_ZMII;
292 bis->bi_phymode[1] = BI_PHYMODE_ZMII;
293 bis->bi_phymode[2] = BI_PHYMODE_ZMII;
294 bis->bi_phymode[3] = BI_PHYMODE_ZMII;
297 zmiifer |= ZMII_FER_RMII << ZMII_FER_V(0);
298 rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(2);
299 bis->bi_phymode[0] = BI_PHYMODE_ZMII;
300 bis->bi_phymode[1] = BI_PHYMODE_NONE;
301 bis->bi_phymode[2] = BI_PHYMODE_RGMII;
302 bis->bi_phymode[3] = BI_PHYMODE_NONE;
305 zmiifer |= ZMII_FER_SMII << ZMII_FER_V(0);
306 zmiifer |= ZMII_FER_SMII << ZMII_FER_V(1);
307 rmiifer |= RGMII_FER_RGMII << RGMII_FER_V (2);
308 rmiifer |= RGMII_FER_RGMII << RGMII_FER_V (3);
309 bis->bi_phymode[0] = BI_PHYMODE_ZMII;
310 bis->bi_phymode[1] = BI_PHYMODE_ZMII;
311 bis->bi_phymode[2] = BI_PHYMODE_RGMII;
312 bis->bi_phymode[3] = BI_PHYMODE_RGMII;
315 zmiifer |= ZMII_FER_SMII << ZMII_FER_V (0);
316 zmiifer |= ZMII_FER_SMII << ZMII_FER_V (1);
317 zmiifer |= ZMII_FER_SMII << ZMII_FER_V (2);
318 rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(3);
319 bis->bi_phymode[0] = BI_PHYMODE_ZMII;
320 bis->bi_phymode[1] = BI_PHYMODE_ZMII;
321 bis->bi_phymode[2] = BI_PHYMODE_ZMII;
322 bis->bi_phymode[3] = BI_PHYMODE_RGMII;
325 zmiifer |= ZMII_FER_SMII << ZMII_FER_V (0);
326 zmiifer |= ZMII_FER_SMII << ZMII_FER_V (1);
327 rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(2);
328 bis->bi_phymode[0] = BI_PHYMODE_ZMII;
329 bis->bi_phymode[1] = BI_PHYMODE_ZMII;
330 bis->bi_phymode[2] = BI_PHYMODE_RGMII;
334 zmiifer = ZMII_FER_MII << ZMII_FER_V(devnum);
336 bis->bi_phymode[0] = BI_PHYMODE_ZMII;
337 bis->bi_phymode[1] = BI_PHYMODE_ZMII;
338 bis->bi_phymode[2] = BI_PHYMODE_ZMII;
339 bis->bi_phymode[3] = BI_PHYMODE_ZMII;
343 /* Ensure we setup mdio for this devnum and ONLY this devnum */
344 zmiifer |= (ZMII_FER_MDI) << ZMII_FER_V(devnum);
346 out32 (ZMII_FER, zmiifer);
347 out32 (RGMII_FER, rmiifer);
351 #endif /* CONFIG_440_GX */
353 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
354 int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis)
356 unsigned long zmiifer=0x0;
359 mfsdr(sdr_pfc1, pfc1);
360 pfc1 &= SDR0_PFC1_SELECT_MASK;
363 case SDR0_PFC1_SELECT_CONFIG_2:
365 out32 (ZMII_FER, 0x00);
366 out32 (RGMII_FER, 0x00000037);
367 bis->bi_phymode[0] = BI_PHYMODE_GMII;
368 bis->bi_phymode[1] = BI_PHYMODE_NONE;
370 case SDR0_PFC1_SELECT_CONFIG_4:
371 /* 2 x RGMII ports */
372 out32 (ZMII_FER, 0x00);
373 out32 (RGMII_FER, 0x00000055);
374 bis->bi_phymode[0] = BI_PHYMODE_RGMII;
375 bis->bi_phymode[1] = BI_PHYMODE_RGMII;
377 case SDR0_PFC1_SELECT_CONFIG_6:
380 ((ZMII_FER_SMII) << ZMII_FER_V(0)) |
381 ((ZMII_FER_SMII) << ZMII_FER_V(1)));
382 out32 (RGMII_FER, 0x00000000);
383 bis->bi_phymode[0] = BI_PHYMODE_SMII;
384 bis->bi_phymode[1] = BI_PHYMODE_SMII;
386 case SDR0_PFC1_SELECT_CONFIG_1_2:
387 /* only 1 x MII supported */
388 out32 (ZMII_FER, (ZMII_FER_MII) << ZMII_FER_V(0));
389 out32 (RGMII_FER, 0x00000000);
390 bis->bi_phymode[0] = BI_PHYMODE_MII;
391 bis->bi_phymode[1] = BI_PHYMODE_NONE;
397 /* Ensure we setup mdio for this devnum and ONLY this devnum */
398 zmiifer = in32 (ZMII_FER);
399 zmiifer |= (ZMII_FER_MDI) << ZMII_FER_V(devnum);
400 out32 (ZMII_FER, zmiifer);
404 #endif /* CONFIG_440EPX */
406 #if defined(CONFIG_405EX)
407 int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis)
412 * Right now only 2*RGMII is supported. Please extend when needed.
417 /* 2 x RGMII ports */
418 out32 (RGMII_FER, 0x00000055);
419 bis->bi_phymode[0] = BI_PHYMODE_RGMII;
420 bis->bi_phymode[1] = BI_PHYMODE_RGMII;
429 /* Ensure we setup mdio for this devnum and ONLY this devnum */
430 gmiifer = in32(RGMII_FER);
431 gmiifer |= (1 << (19-devnum));
432 out32 (RGMII_FER, gmiifer);
436 #endif /* CONFIG_405EX */
438 static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
441 unsigned long reg = 0;
444 unsigned long duplex;
445 unsigned long failsafe;
447 unsigned short devnum;
448 unsigned short reg_short;
449 #if defined(CONFIG_440GX) || \
450 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
451 defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
452 defined(CONFIG_405EX)
454 #if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \
455 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
456 defined(CONFIG_405EX)
460 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
461 defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
462 defined(CONFIG_405EX)
466 EMAC_4XX_HW_PST hw_p = dev->priv;
468 /* before doing anything, figure out if we have a MAC address */
470 if (memcmp (dev->enetaddr, "\0\0\0\0\0\0", 6) == 0) {
471 printf("ERROR: ethaddr not set!\n");
475 #if defined(CONFIG_440GX) || \
476 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
477 defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
478 defined(CONFIG_405EX)
479 /* Need to get the OPB frequency so we can access the PHY */
480 get_sys_info (&sysinfo);
484 mtmsr (msr & ~(MSR_EE)); /* disable interrupts */
486 devnum = hw_p->devnum;
491 * hw_p->stats.pkts_handled <= hw_p->stats.pkts_rx <= hw_p->stats.pkts_handled+PKTBUFSRX
492 * In the most cases hw_p->stats.pkts_handled = hw_p->stats.pkts_rx, but it
493 * is possible that new packets (without relationship with
494 * current transfer) have got the time to arrived before
495 * netloop calls eth_halt
497 printf ("About preceeding transfer (eth%d):\n"
498 "- Sent packet number %d\n"
499 "- Received packet number %d\n"
500 "- Handled packet number %d\n",
503 hw_p->stats.pkts_rx, hw_p->stats.pkts_handled);
505 hw_p->stats.pkts_tx = 0;
506 hw_p->stats.pkts_rx = 0;
507 hw_p->stats.pkts_handled = 0;
508 hw_p->print_speed = 1; /* print speed message again next time */
511 hw_p->tx_err_index = 0; /* Transmit Error Index for tx_err_log */
512 hw_p->rx_err_index = 0; /* Receive Error Index for rx_err_log */
514 hw_p->rx_slot = 0; /* MAL Receive Slot */
515 hw_p->rx_i_index = 0; /* Receive Interrupt Queue Index */
516 hw_p->rx_u_index = 0; /* Receive User Queue Index */
518 hw_p->tx_slot = 0; /* MAL Transmit Slot */
519 hw_p->tx_i_index = 0; /* Transmit Interrupt Queue Index */
520 hw_p->tx_u_index = 0; /* Transmit User Queue Index */
522 #if defined(CONFIG_440) && !defined(CONFIG_440SP) && !defined(CONFIG_440SPE)
524 /* NOTE: 440GX spec states that mode is mutually exclusive */
525 /* NOTE: Therefore, disable all other EMACS, since we handle */
526 /* NOTE: only one emac at a time */
531 #if defined(CONFIG_440EP) || defined(CONFIG_440GR)
532 out32 (ZMII_FER, (ZMII_FER_RMII | ZMII_FER_MDI) << ZMII_FER_V (devnum));
533 #elif defined(CONFIG_440GX) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
534 ethgroup = ppc_4xx_eth_setup_bridge(devnum, bis);
535 #elif defined(CONFIG_440GP)
537 out32 (ZMII_FER, ZMII_RMII | ZMII_MDI0);
539 if ((devnum == 0) || (devnum == 1)) {
540 out32 (ZMII_FER, (ZMII_FER_SMII | ZMII_FER_MDI) << ZMII_FER_V (devnum));
541 } else { /* ((devnum == 2) || (devnum == 3)) */
542 out32 (ZMII_FER, ZMII_FER_MDI << ZMII_FER_V (devnum));
543 out32 (RGMII_FER, ((RGMII_FER_RGMII << RGMII_FER_V (2)) |
544 (RGMII_FER_RGMII << RGMII_FER_V (3))));
548 out32 (ZMII_SSR, ZMII_SSR_SP << ZMII_SSR_V(devnum));
549 #endif /* defined(CONFIG_440) && !defined(CONFIG_440SP) */
550 #if defined(CONFIG_405EX)
551 ethgroup = ppc_4xx_eth_setup_bridge(devnum, bis);
554 __asm__ volatile ("eieio");
556 /* reset emac so we have access to the phy */
557 #if defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
558 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
559 defined(CONFIG_405EX)
560 /* provide clocks for EMAC internal loopback */
561 mfsdr (sdr_mfr, mfr);
562 mfr |= SDR0_MFR_ETH_CLK_SEL_V(devnum);
566 out32 (EMAC_M0 + hw_p->hw_addr, EMAC_M0_SRST);
567 __asm__ volatile ("eieio");
570 while ((in32 (EMAC_M0 + hw_p->hw_addr) & (EMAC_M0_SRST)) && failsafe) {
575 printf("\nProblem resetting EMAC!\n");
577 #if defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
578 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
579 defined(CONFIG_405EX)
580 /* remove clocks for EMAC internal loopback */
581 mfsdr (sdr_mfr, mfr);
582 mfr &= ~SDR0_MFR_ETH_CLK_SEL_V(devnum);
586 #if defined(CONFIG_440GX) || \
587 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
588 defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
589 defined(CONFIG_405EX)
590 /* Whack the M1 register */
592 mode_reg &= ~0x00000038;
593 if (sysinfo.freqOPB <= 50000000);
594 else if (sysinfo.freqOPB <= 66666667)
595 mode_reg |= EMAC_M1_OBCI_66;
596 else if (sysinfo.freqOPB <= 83333333)
597 mode_reg |= EMAC_M1_OBCI_83;
598 else if (sysinfo.freqOPB <= 100000000)
599 mode_reg |= EMAC_M1_OBCI_100;
601 mode_reg |= EMAC_M1_OBCI_GT100;
603 out32 (EMAC_M1 + hw_p->hw_addr, mode_reg);
604 #endif /* defined(CONFIG_440GX) || defined(CONFIG_440SP) */
606 /* wait for PHY to complete auto negotiation */
608 #ifndef CONFIG_CS8952_PHY
611 reg = CONFIG_PHY_ADDR;
613 #if defined (CONFIG_PHY1_ADDR)
615 reg = CONFIG_PHY1_ADDR;
618 #if defined (CONFIG_440GX)
620 reg = CONFIG_PHY2_ADDR;
623 reg = CONFIG_PHY3_ADDR;
627 reg = CONFIG_PHY_ADDR;
631 bis->bi_phynum[devnum] = reg;
633 #if defined(CONFIG_PHY_RESET)
635 * Reset the phy, only if its the first time through
636 * otherwise, just check the speeds & feeds
638 if (hw_p->first_init == 0) {
639 #if defined(CONFIG_M88E1111_PHY)
640 miiphy_write (dev->name, reg, 0x14, 0x0ce3);
641 miiphy_write (dev->name, reg, 0x18, 0x4101);
642 miiphy_write (dev->name, reg, 0x09, 0x0e00);
643 miiphy_write (dev->name, reg, 0x04, 0x01e1);
645 miiphy_reset (dev->name, reg);
647 #if defined(CONFIG_440GX) || \
648 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
649 defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
650 defined(CONFIG_405EX)
652 #if defined(CONFIG_CIS8201_PHY)
654 * Cicada 8201 PHY needs to have an extended register whacked
657 if (((devnum == 2) || (devnum == 3)) && (4 == ethgroup)) {
658 #if defined(CONFIG_CIS8201_SHORT_ETCH)
659 miiphy_write (dev->name, reg, 23, 0x1300);
661 miiphy_write (dev->name, reg, 23, 0x1000);
664 * Vitesse VSC8201/Cicada CIS8201 errata:
665 * Interoperability problem with Intel 82547EI phys
666 * This work around (provided by Vitesse) changes
667 * the default timer convergence from 8ms to 12ms
669 miiphy_write (dev->name, reg, 0x1f, 0x2a30);
670 miiphy_write (dev->name, reg, 0x08, 0x0200);
671 miiphy_write (dev->name, reg, 0x1f, 0x52b5);
672 miiphy_write (dev->name, reg, 0x02, 0x0004);
673 miiphy_write (dev->name, reg, 0x01, 0x0671);
674 miiphy_write (dev->name, reg, 0x00, 0x8fae);
675 miiphy_write (dev->name, reg, 0x1f, 0x2a30);
676 miiphy_write (dev->name, reg, 0x08, 0x0000);
677 miiphy_write (dev->name, reg, 0x1f, 0x0000);
678 /* end Vitesse/Cicada errata */
682 #if defined(CONFIG_ET1011C_PHY)
684 * Agere ET1011c PHY needs to have an extended register whacked
687 if (((devnum == 2) || (devnum ==3)) && (4 == ethgroup)) {
688 miiphy_read (dev->name, reg, 0x16, ®_short);
690 reg_short |= 0x6; /* RGMII DLL Delay*/
691 miiphy_write (dev->name, reg, 0x16, reg_short);
693 miiphy_read (dev->name, reg, 0x17, ®_short);
694 reg_short &= ~(0x40);
695 miiphy_write (dev->name, reg, 0x17, reg_short);
697 miiphy_write(dev->name, reg, 0x1c, 0x74f0);
702 /* Start/Restart autonegotiation */
703 phy_setup_aneg (dev->name, reg);
706 #endif /* defined(CONFIG_PHY_RESET) */
708 miiphy_read (dev->name, reg, PHY_BMSR, ®_short);
711 * Wait if PHY is capable of autonegotiation and autonegotiation is not complete
713 if ((reg_short & PHY_BMSR_AUTN_ABLE)
714 && !(reg_short & PHY_BMSR_AUTN_COMP)) {
715 puts ("Waiting for PHY auto negotiation to complete");
717 while (!(reg_short & PHY_BMSR_AUTN_COMP)) {
721 if (i > PHY_AUTONEGOTIATE_TIMEOUT) {
722 puts (" TIMEOUT !\n");
726 if ((i++ % 1000) == 0) {
729 udelay (1000); /* 1 ms */
730 miiphy_read (dev->name, reg, PHY_BMSR, ®_short);
734 udelay (500000); /* another 500 ms (results in faster booting) */
736 #endif /* #ifndef CONFIG_CS8952_PHY */
738 speed = miiphy_speed (dev->name, reg);
739 duplex = miiphy_duplex (dev->name, reg);
741 if (hw_p->print_speed) {
742 hw_p->print_speed = 0;
743 printf ("ENET Speed is %d Mbps - %s duplex connection (EMAC%d)\n",
744 (int) speed, (duplex == HALF) ? "HALF" : "FULL",
748 #if defined(CONFIG_440) && !defined(CONFIG_440SP) && !defined(CONFIG_440SPE) && \
749 !defined(CONFIG_440EPX) && !defined(CONFIG_440GRX)
750 #if defined(CONFIG_440EP) || defined(CONFIG_440GR)
753 reg = (reg & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_RMII_100M;
755 reg = (reg & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_RMII_10M;
760 /* Set ZMII/RGMII speed according to the phy link speed */
761 reg = in32 (ZMII_SSR);
762 if ( (speed == 100) || (speed == 1000) )
763 out32 (ZMII_SSR, reg | (ZMII_SSR_SP << ZMII_SSR_V (devnum)));
765 out32 (ZMII_SSR, reg & (~(ZMII_SSR_SP << ZMII_SSR_V (devnum))));
767 if ((devnum == 2) || (devnum == 3)) {
769 reg = (RGMII_SSR_SP_1000MBPS << RGMII_SSR_V (devnum));
770 else if (speed == 100)
771 reg = (RGMII_SSR_SP_100MBPS << RGMII_SSR_V (devnum));
772 else if (speed == 10)
773 reg = (RGMII_SSR_SP_10MBPS << RGMII_SSR_V (devnum));
775 printf("Error in RGMII Speed\n");
778 out32 (RGMII_SSR, reg);
780 #endif /* defined(CONFIG_440) && !defined(CONFIG_440SP) */
782 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
783 defined(CONFIG_405EX)
785 reg = (RGMII_SSR_SP_1000MBPS << RGMII_SSR_V (devnum));
786 else if (speed == 100)
787 reg = (RGMII_SSR_SP_100MBPS << RGMII_SSR_V (devnum));
788 else if (speed == 10)
789 reg = (RGMII_SSR_SP_10MBPS << RGMII_SSR_V (devnum));
791 printf("Error in RGMII Speed\n");
794 out32 (RGMII_SSR, reg);
797 /* set the Mal configuration reg */
798 #if defined(CONFIG_440GX) || \
799 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
800 defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
801 defined(CONFIG_405EX)
802 mtdcr (malmcr, MAL_CR_PLBB | MAL_CR_OPBBL | MAL_CR_LEA |
803 MAL_CR_PLBLT_DEFAULT | MAL_CR_EOPIE | 0x00330000);
805 mtdcr (malmcr, MAL_CR_PLBB | MAL_CR_OPBBL | MAL_CR_LEA | MAL_CR_PLBLT_DEFAULT);
806 /* Errata 1.12: MAL_1 -- Disable MAL bursting */
807 if (get_pvr() == PVR_440GP_RB) {
808 mtdcr (malmcr, mfdcr(malmcr) & ~MAL_CR_PLBB);
812 /* Free "old" buffers */
813 if (hw_p->alloc_tx_buf)
814 free (hw_p->alloc_tx_buf);
815 if (hw_p->alloc_rx_buf)
816 free (hw_p->alloc_rx_buf);
819 * Malloc MAL buffer desciptors, make sure they are
820 * aligned on cache line boundary size
821 * (401/403/IOP480 = 16, 405 = 32)
822 * and doesn't cross cache block boundaries.
825 (mal_desc_t *) malloc ((sizeof (mal_desc_t) * NUM_TX_BUFF) +
826 ((2 * CFG_CACHELINE_SIZE) - 2));
827 if (NULL == hw_p->alloc_tx_buf)
829 if (((int) hw_p->alloc_tx_buf & CACHELINE_MASK) != 0) {
831 (mal_desc_t *) ((int) hw_p->alloc_tx_buf +
834 alloc_tx_buf & CACHELINE_MASK));
836 hw_p->tx = hw_p->alloc_tx_buf;
840 (mal_desc_t *) malloc ((sizeof (mal_desc_t) * NUM_RX_BUFF) +
841 ((2 * CFG_CACHELINE_SIZE) - 2));
842 if (NULL == hw_p->alloc_rx_buf) {
843 free(hw_p->alloc_tx_buf);
844 hw_p->alloc_tx_buf = NULL;
848 if (((int) hw_p->alloc_rx_buf & CACHELINE_MASK) != 0) {
850 (mal_desc_t *) ((int) hw_p->alloc_rx_buf +
853 alloc_rx_buf & CACHELINE_MASK));
855 hw_p->rx = hw_p->alloc_rx_buf;
858 for (i = 0; i < NUM_TX_BUFF; i++) {
859 hw_p->tx[i].ctrl = 0;
860 hw_p->tx[i].data_len = 0;
861 if (hw_p->first_init == 0) {
863 (char *) malloc (ENET_MAX_MTU_ALIGNED);
864 if (NULL == hw_p->txbuf_ptr) {
865 free(hw_p->alloc_rx_buf);
866 free(hw_p->alloc_tx_buf);
867 hw_p->alloc_rx_buf = NULL;
868 hw_p->alloc_tx_buf = NULL;
869 for(j = 0; j < i; j++) {
870 free(hw_p->tx[i].data_ptr);
871 hw_p->tx[i].data_ptr = NULL;
875 hw_p->tx[i].data_ptr = hw_p->txbuf_ptr;
876 if ((NUM_TX_BUFF - 1) == i)
877 hw_p->tx[i].ctrl |= MAL_TX_CTRL_WRAP;
878 hw_p->tx_run[i] = -1;
880 printf ("TX_BUFF %d @ 0x%08lx\n", i,
881 (ulong) hw_p->tx[i].data_ptr);
885 for (i = 0; i < NUM_RX_BUFF; i++) {
886 hw_p->rx[i].ctrl = 0;
887 hw_p->rx[i].data_len = 0;
888 /* rx[i].data_ptr = (char *) &rx_buff[i]; */
889 hw_p->rx[i].data_ptr = (char *) NetRxPackets[i];
890 if ((NUM_RX_BUFF - 1) == i)
891 hw_p->rx[i].ctrl |= MAL_RX_CTRL_WRAP;
892 hw_p->rx[i].ctrl |= MAL_RX_CTRL_EMPTY | MAL_RX_CTRL_INTR;
893 hw_p->rx_ready[i] = -1;
895 printf ("RX_BUFF %d @ 0x%08lx\n", i, (ulong) hw_p->rx[i].data_ptr);
901 reg |= dev->enetaddr[0]; /* set high address */
903 reg |= dev->enetaddr[1];
905 out32 (EMAC_IAH + hw_p->hw_addr, reg);
908 reg |= dev->enetaddr[2]; /* set low address */
910 reg |= dev->enetaddr[3];
912 reg |= dev->enetaddr[4];
914 reg |= dev->enetaddr[5];
916 out32 (EMAC_IAL + hw_p->hw_addr, reg);
920 /* setup MAL tx & rx channel pointers */
921 #if defined (CONFIG_405EP) || defined (CONFIG_440EP) || defined (CONFIG_440GR)
922 mtdcr (maltxctp2r, hw_p->tx);
924 mtdcr (maltxctp1r, hw_p->tx);
926 #if defined(CONFIG_440)
927 mtdcr (maltxbattr, 0x0);
928 mtdcr (malrxbattr, 0x0);
930 mtdcr (malrxctp1r, hw_p->rx);
931 /* set RX buffer size */
932 mtdcr (malrcbs1, ENET_MAX_MTU_ALIGNED / 16);
934 #if defined (CONFIG_440GX)
936 /* setup MAL tx & rx channel pointers */
937 mtdcr (maltxbattr, 0x0);
938 mtdcr (malrxbattr, 0x0);
939 mtdcr (maltxctp2r, hw_p->tx);
940 mtdcr (malrxctp2r, hw_p->rx);
941 /* set RX buffer size */
942 mtdcr (malrcbs2, ENET_MAX_MTU_ALIGNED / 16);
945 /* setup MAL tx & rx channel pointers */
946 mtdcr (maltxbattr, 0x0);
947 mtdcr (maltxctp3r, hw_p->tx);
948 mtdcr (malrxbattr, 0x0);
949 mtdcr (malrxctp3r, hw_p->rx);
950 /* set RX buffer size */
951 mtdcr (malrcbs3, ENET_MAX_MTU_ALIGNED / 16);
953 #endif /* CONFIG_440GX */
956 /* setup MAL tx & rx channel pointers */
957 #if defined(CONFIG_440)
958 mtdcr (maltxbattr, 0x0);
959 mtdcr (malrxbattr, 0x0);
961 mtdcr (maltxctp0r, hw_p->tx);
962 mtdcr (malrxctp0r, hw_p->rx);
963 /* set RX buffer size */
964 mtdcr (malrcbs0, ENET_MAX_MTU_ALIGNED / 16);
968 /* Enable MAL transmit and receive channels */
969 #if defined(CONFIG_405EP) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
970 mtdcr (maltxcasr, (MAL_TXRX_CASR >> (hw_p->devnum*2)));
972 mtdcr (maltxcasr, (MAL_TXRX_CASR >> hw_p->devnum));
974 mtdcr (malrxcasr, (MAL_TXRX_CASR >> hw_p->devnum));
976 /* set transmit enable & receive enable */
977 out32 (EMAC_M0 + hw_p->hw_addr, EMAC_M0_TXE | EMAC_M0_RXE);
979 /* set receive fifo to 4k and tx fifo to 2k */
980 mode_reg = in32 (EMAC_M1 + hw_p->hw_addr);
981 mode_reg |= EMAC_M1_RFS_4K | EMAC_M1_TX_FIFO_2K;
984 if (speed == _1000BASET) {
985 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
986 defined(CONFIG_440SP) || defined(CONFIG_440SPE)
989 mfsdr (sdr_pfc1, pfc1);
990 pfc1 |= SDR0_PFC1_EM_1000;
991 mtsdr (sdr_pfc1, pfc1);
993 mode_reg = mode_reg | EMAC_M1_MF_1000MBPS | EMAC_M1_IST;
994 } else if (speed == _100BASET)
995 mode_reg = mode_reg | EMAC_M1_MF_100MBPS | EMAC_M1_IST;
997 mode_reg = mode_reg & ~0x00C00000; /* 10 MBPS */
999 mode_reg = mode_reg | 0x80000000 | EMAC_M1_IST;
1001 out32 (EMAC_M1 + hw_p->hw_addr, mode_reg);
1003 /* Enable broadcast and indvidual address */
1004 /* TBS: enabling runts as some misbehaved nics will send runts */
1005 out32 (EMAC_RXM + hw_p->hw_addr, EMAC_RMR_BAE | EMAC_RMR_IAE);
1007 /* we probably need to set the tx mode1 reg? maybe at tx time */
1009 /* set transmit request threshold register */
1010 out32 (EMAC_TRTR + hw_p->hw_addr, 0x18000000); /* 256 byte threshold */
1012 /* set receive low/high water mark register */
1013 #if defined(CONFIG_440)
1014 /* 440s has a 64 byte burst length */
1015 out32 (EMAC_RX_HI_LO_WMARK + hw_p->hw_addr, 0x80009000);
1017 /* 405s have a 16 byte burst length */
1018 out32 (EMAC_RX_HI_LO_WMARK + hw_p->hw_addr, 0x0f002000);
1019 #endif /* defined(CONFIG_440) */
1020 out32 (EMAC_TXM1 + hw_p->hw_addr, 0xf8640000);
1022 /* Set fifo limit entry in tx mode 0 */
1023 out32 (EMAC_TXM0 + hw_p->hw_addr, 0x00000003);
1025 out32 (EMAC_I_FRAME_GAP_REG + hw_p->hw_addr, 0x00000008);
1028 hw_p->emac_ier = EMAC_ISR_PTLE | EMAC_ISR_BFCS | EMAC_ISR_ORE | EMAC_ISR_IRE;
1029 if (speed == _100BASET)
1030 hw_p->emac_ier = hw_p->emac_ier | EMAC_ISR_SYE;
1032 out32 (EMAC_ISR + hw_p->hw_addr, 0xffffffff); /* clear pending interrupts */
1033 out32 (EMAC_IER + hw_p->hw_addr, hw_p->emac_ier);
1035 if (hw_p->first_init == 0) {
1037 * Connect interrupt service routines
1039 irq_install_handler(ETH_IRQ_NUM(hw_p->devnum),
1040 (interrupt_handler_t *) enetInt, dev);
1043 mtmsr (msr); /* enable interrupts again */
1046 hw_p->first_init = 1;
1052 static int ppc_4xx_eth_send (struct eth_device *dev, volatile void *ptr,
1055 struct enet_frame *ef_ptr;
1056 ulong time_start, time_now;
1057 unsigned long temp_txm0;
1058 EMAC_4XX_HW_PST hw_p = dev->priv;
1060 ef_ptr = (struct enet_frame *) ptr;
1062 /*-----------------------------------------------------------------------+
1063 * Copy in our address into the frame.
1064 *-----------------------------------------------------------------------*/
1065 (void) memcpy (ef_ptr->source_addr, dev->enetaddr, ENET_ADDR_LENGTH);
1067 /*-----------------------------------------------------------------------+
1068 * If frame is too long or too short, modify length.
1069 *-----------------------------------------------------------------------*/
1070 /* TBS: where does the fragment go???? */
1071 if (len > ENET_MAX_MTU)
1074 /* memcpy ((void *) &tx_buff[tx_slot], (const void *) ptr, len); */
1075 memcpy ((void *) hw_p->txbuf_ptr, (const void *) ptr, len);
1077 /*-----------------------------------------------------------------------+
1078 * set TX Buffer busy, and send it
1079 *-----------------------------------------------------------------------*/
1080 hw_p->tx[hw_p->tx_slot].ctrl = (MAL_TX_CTRL_LAST |
1081 EMAC_TX_CTRL_GFCS | EMAC_TX_CTRL_GP) &
1082 ~(EMAC_TX_CTRL_ISA | EMAC_TX_CTRL_RSA);
1083 if ((NUM_TX_BUFF - 1) == hw_p->tx_slot)
1084 hw_p->tx[hw_p->tx_slot].ctrl |= MAL_TX_CTRL_WRAP;
1086 hw_p->tx[hw_p->tx_slot].data_len = (short) len;
1087 hw_p->tx[hw_p->tx_slot].ctrl |= MAL_TX_CTRL_READY;
1089 __asm__ volatile ("eieio");
1091 out32 (EMAC_TXM0 + hw_p->hw_addr,
1092 in32 (EMAC_TXM0 + hw_p->hw_addr) | EMAC_TXM0_GNP0);
1093 #ifdef INFO_4XX_ENET
1094 hw_p->stats.pkts_tx++;
1097 /*-----------------------------------------------------------------------+
1098 * poll unitl the packet is sent and then make sure it is OK
1099 *-----------------------------------------------------------------------*/
1100 time_start = get_timer (0);
1102 temp_txm0 = in32 (EMAC_TXM0 + hw_p->hw_addr);
1103 /* loop until either TINT turns on or 3 seconds elapse */
1104 if ((temp_txm0 & EMAC_TXM0_GNP0) != 0) {
1105 /* transmit is done, so now check for errors
1106 * If there is an error, an interrupt should
1107 * happen when we return
1109 time_now = get_timer (0);
1110 if ((time_now - time_start) > 3000) {
1120 #if defined (CONFIG_440) || defined(CONFIG_405EX)
1122 #if defined(CONFIG_440SP) || defined(CONFIG_440SPE)
1124 * Hack: On 440SP all enet irq sources are located on UIC1
1125 * Needs some cleanup. --sr
1127 #define UIC0MSR uic1msr
1128 #define UIC0SR uic1sr
1130 #define UIC0MSR uic0msr
1131 #define UIC0SR uic0sr
1134 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
1135 defined(CONFIG_405EX)
1136 #define UICMSR_ETHX uic0msr
1137 #define UICSR_ETHX uic0sr
1139 #define UICMSR_ETHX uic1msr
1140 #define UICSR_ETHX uic1sr
1143 int enetInt (struct eth_device *dev)
1146 int rc = -1; /* default to not us */
1147 unsigned long mal_isr;
1148 unsigned long emac_isr = 0;
1149 unsigned long mal_rx_eob;
1150 unsigned long my_uic0msr, my_uic1msr;
1151 unsigned long my_uicmsr_ethx;
1153 #if defined(CONFIG_440GX)
1154 unsigned long my_uic2msr;
1156 EMAC_4XX_HW_PST hw_p;
1159 * Because the mal is generic, we need to get the current
1162 #if defined(CONFIG_NET_MULTI)
1163 dev = eth_get_dev();
1170 /* enter loop that stays in interrupt code until nothing to service */
1174 my_uic0msr = mfdcr (UIC0MSR);
1175 my_uic1msr = mfdcr (uic1msr);
1176 #if defined(CONFIG_440GX)
1177 my_uic2msr = mfdcr (uic2msr);
1179 my_uicmsr_ethx = mfdcr (UICMSR_ETHX);
1181 if (!(my_uic0msr & (UIC_MRE | UIC_MTE))
1182 && !(my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))
1183 && !(my_uicmsr_ethx & (UIC_ETH0 | UIC_ETH1))) {
1187 #if defined (CONFIG_440GX)
1188 if (!(my_uic0msr & (UIC_MRE | UIC_MTE))
1189 && !(my_uic2msr & (UIC_ETH2 | UIC_ETH3))) {
1194 /* get and clear controller status interrupts */
1195 /* look at Mal and EMAC interrupts */
1196 if ((my_uic0msr & (UIC_MRE | UIC_MTE))
1197 || (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) {
1198 /* we have a MAL interrupt */
1199 mal_isr = mfdcr (malesr);
1200 /* look for mal error */
1201 if (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE)) {
1202 mal_err (dev, mal_isr, my_uic1msr, MAL_UIC_DEF, MAL_UIC_ERR);
1208 /* port by port dispatch of emac interrupts */
1209 if (hw_p->devnum == 0) {
1210 if (UIC_ETH0 & my_uicmsr_ethx) { /* look for EMAC errors */
1211 emac_isr = in32 (EMAC_ISR + hw_p->hw_addr);
1212 if ((hw_p->emac_ier & emac_isr) != 0) {
1213 emac_err (dev, emac_isr);
1218 if ((hw_p->emac_ier & emac_isr)
1219 || (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) {
1220 mtdcr (UIC0SR, UIC_MRE | UIC_MTE); /* Clear */
1221 mtdcr (uic1sr, UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */
1222 mtdcr (UICSR_ETHX, UIC_ETH0); /* Clear */
1223 return (rc); /* we had errors so get out */
1227 #if !defined(CONFIG_440SP)
1228 if (hw_p->devnum == 1) {
1229 if (UIC_ETH1 & my_uicmsr_ethx) { /* look for EMAC errors */
1230 emac_isr = in32 (EMAC_ISR + hw_p->hw_addr);
1231 if ((hw_p->emac_ier & emac_isr) != 0) {
1232 emac_err (dev, emac_isr);
1237 if ((hw_p->emac_ier & emac_isr)
1238 || (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) {
1239 mtdcr (UIC0SR, UIC_MRE | UIC_MTE); /* Clear */
1240 mtdcr (uic1sr, UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */
1241 mtdcr (UICSR_ETHX, UIC_ETH1); /* Clear */
1242 return (rc); /* we had errors so get out */
1245 #if defined (CONFIG_440GX)
1246 if (hw_p->devnum == 2) {
1247 if (UIC_ETH2 & my_uic2msr) { /* look for EMAC errors */
1248 emac_isr = in32 (EMAC_ISR + hw_p->hw_addr);
1249 if ((hw_p->emac_ier & emac_isr) != 0) {
1250 emac_err (dev, emac_isr);
1255 if ((hw_p->emac_ier & emac_isr)
1256 || (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) {
1257 mtdcr (UIC0SR, UIC_MRE | UIC_MTE); /* Clear */
1258 mtdcr (uic1sr, UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */
1259 mtdcr (uic2sr, UIC_ETH2);
1260 return (rc); /* we had errors so get out */
1264 if (hw_p->devnum == 3) {
1265 if (UIC_ETH3 & my_uic2msr) { /* look for EMAC errors */
1266 emac_isr = in32 (EMAC_ISR + hw_p->hw_addr);
1267 if ((hw_p->emac_ier & emac_isr) != 0) {
1268 emac_err (dev, emac_isr);
1273 if ((hw_p->emac_ier & emac_isr)
1274 || (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) {
1275 mtdcr (UIC0SR, UIC_MRE | UIC_MTE); /* Clear */
1276 mtdcr (uic1sr, UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */
1277 mtdcr (uic2sr, UIC_ETH3);
1278 return (rc); /* we had errors so get out */
1281 #endif /* CONFIG_440GX */
1282 #endif /* !CONFIG_440SP */
1284 /* handle MAX TX EOB interrupt from a tx */
1285 if (my_uic0msr & UIC_MTE) {
1286 mal_rx_eob = mfdcr (maltxeobisr);
1287 mtdcr (maltxeobisr, mal_rx_eob);
1288 mtdcr (UIC0SR, UIC_MTE);
1290 /* handle MAL RX EOB interupt from a receive */
1291 /* check for EOB on valid channels */
1292 if (my_uic0msr & UIC_MRE) {
1293 mal_rx_eob = mfdcr (malrxeobisr);
1294 if ((mal_rx_eob & (0x80000000 >> hw_p->devnum)) != 0) { /* call emac routine for channel x */
1296 mtdcr(malrxeobisr, mal_rx_eob); */
1297 enet_rcv (dev, emac_isr);
1298 /* indicate that we serviced an interrupt */
1304 mtdcr (UIC0SR, UIC_MRE); /* Clear */
1305 mtdcr (uic1sr, UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */
1306 switch (hw_p->devnum) {
1308 mtdcr (UICSR_ETHX, UIC_ETH0);
1311 mtdcr (UICSR_ETHX, UIC_ETH1);
1313 #if defined (CONFIG_440GX)
1315 mtdcr (uic2sr, UIC_ETH2);
1318 mtdcr (uic2sr, UIC_ETH3);
1320 #endif /* CONFIG_440GX */
1329 #else /* CONFIG_440 */
1331 int enetInt (struct eth_device *dev)
1334 int rc = -1; /* default to not us */
1335 unsigned long mal_isr;
1336 unsigned long emac_isr = 0;
1337 unsigned long mal_rx_eob;
1338 unsigned long my_uicmsr;
1340 EMAC_4XX_HW_PST hw_p;
1343 * Because the mal is generic, we need to get the current
1346 #if defined(CONFIG_NET_MULTI)
1347 dev = eth_get_dev();
1354 /* enter loop that stays in interrupt code until nothing to service */
1358 my_uicmsr = mfdcr (uicmsr);
1360 if ((my_uicmsr & (MAL_UIC_DEF | EMAC_UIC_DEF)) == 0) { /* not for us */
1363 /* get and clear controller status interrupts */
1364 /* look at Mal and EMAC interrupts */
1365 if ((MAL_UIC_DEF & my_uicmsr) != 0) { /* we have a MAL interrupt */
1366 mal_isr = mfdcr (malesr);
1367 /* look for mal error */
1368 if ((my_uicmsr & MAL_UIC_ERR) != 0) {
1369 mal_err (dev, mal_isr, my_uicmsr, MAL_UIC_DEF, MAL_UIC_ERR);
1375 /* port by port dispatch of emac interrupts */
1377 if ((SEL_UIC_DEF(hw_p->devnum) & my_uicmsr) != 0) { /* look for EMAC errors */
1378 emac_isr = in32 (EMAC_ISR + hw_p->hw_addr);
1379 if ((hw_p->emac_ier & emac_isr) != 0) {
1380 emac_err (dev, emac_isr);
1385 if (((hw_p->emac_ier & emac_isr) != 0) || ((MAL_UIC_ERR & my_uicmsr) != 0)) {
1386 mtdcr (uicsr, MAL_UIC_DEF | SEL_UIC_DEF(hw_p->devnum)); /* Clear */
1387 return (rc); /* we had errors so get out */
1390 /* handle MAX TX EOB interrupt from a tx */
1391 if (my_uicmsr & UIC_MAL_TXEOB) {
1392 mal_rx_eob = mfdcr (maltxeobisr);
1393 mtdcr (maltxeobisr, mal_rx_eob);
1394 mtdcr (uicsr, UIC_MAL_TXEOB);
1396 /* handle MAL RX EOB interupt from a receive */
1397 /* check for EOB on valid channels */
1398 if (my_uicmsr & UIC_MAL_RXEOB)
1400 mal_rx_eob = mfdcr (malrxeobisr);
1401 if ((mal_rx_eob & (0x80000000 >> hw_p->devnum)) != 0) { /* call emac routine for channel x */
1403 mtdcr(malrxeobisr, mal_rx_eob); */
1404 enet_rcv (dev, emac_isr);
1405 /* indicate that we serviced an interrupt */
1410 mtdcr (uicsr, MAL_UIC_DEF|EMAC_UIC_DEF|EMAC_UIC_DEF1); /* Clear */
1411 #if defined(CONFIG_405EZ)
1412 mtsdr (sdricintstat, SDR_ICRX_STAT | SDR_ICTX0_STAT | SDR_ICTX1_STAT);
1413 #endif /* defined(CONFIG_405EZ) */
1420 #endif /* CONFIG_440 */
1422 /*-----------------------------------------------------------------------------+
1424 *-----------------------------------------------------------------------------*/
1425 static void mal_err (struct eth_device *dev, unsigned long isr,
1426 unsigned long uic, unsigned long maldef,
1427 unsigned long mal_errr)
1429 EMAC_4XX_HW_PST hw_p = dev->priv;
1431 mtdcr (malesr, isr); /* clear interrupt */
1433 /* clear DE interrupt */
1434 mtdcr (maltxdeir, 0xC0000000);
1435 mtdcr (malrxdeir, 0x80000000);
1437 #ifdef INFO_4XX_ENET
1438 printf ("\nMAL error occured.... ISR = %lx UIC = = %lx MAL_DEF = %lx MAL_ERR= %lx \n", isr, uic, maldef, mal_errr);
1441 eth_init (hw_p->bis); /* start again... */
1444 /*-----------------------------------------------------------------------------+
1445 * EMAC Error Routine
1446 *-----------------------------------------------------------------------------*/
1447 static void emac_err (struct eth_device *dev, unsigned long isr)
1449 EMAC_4XX_HW_PST hw_p = dev->priv;
1451 printf ("EMAC%d error occured.... ISR = %lx\n", hw_p->devnum, isr);
1452 out32 (EMAC_ISR + hw_p->hw_addr, isr);
1455 /*-----------------------------------------------------------------------------+
1456 * enet_rcv() handles the ethernet receive data
1457 *-----------------------------------------------------------------------------*/
1458 static void enet_rcv (struct eth_device *dev, unsigned long malisr)
1460 struct enet_frame *ef_ptr;
1461 unsigned long data_len;
1462 unsigned long rx_eob_isr;
1463 EMAC_4XX_HW_PST hw_p = dev->priv;
1469 rx_eob_isr = mfdcr (malrxeobisr);
1470 if ((0x80000000 >> hw_p->devnum) & rx_eob_isr) {
1472 mtdcr (malrxeobisr, rx_eob_isr);
1475 while (1) { /* do all */
1478 if ((MAL_RX_CTRL_EMPTY & hw_p->rx[i].ctrl)
1479 || (loop_count >= NUM_RX_BUFF))
1484 data_len = (unsigned long) hw_p->rx[i].data_len; /* Get len */
1486 if (data_len > ENET_MAX_MTU) /* Check len */
1489 if (EMAC_RX_ERRORS & hw_p->rx[i].ctrl) { /* Check Errors */
1491 hw_p->stats.rx_err_log[hw_p->
1494 hw_p->rx_err_index++;
1495 if (hw_p->rx_err_index ==
1497 hw_p->rx_err_index =
1500 } /* data_len < max mtu */
1502 if (!data_len) { /* no data */
1503 hw_p->rx[i].ctrl |= MAL_RX_CTRL_EMPTY; /* Free Recv Buffer */
1505 hw_p->stats.data_len_err++; /* Error at Rx */
1510 /* Check if user has already eaten buffer */
1511 /* if not => ERROR */
1512 else if (hw_p->rx_ready[hw_p->rx_i_index] != -1) {
1513 if (hw_p->is_receiving)
1514 printf ("ERROR : Receive buffers are full!\n");
1517 hw_p->stats.rx_frames++;
1518 hw_p->stats.rx += data_len;
1519 ef_ptr = (struct enet_frame *) hw_p->rx[i].
1521 #ifdef INFO_4XX_ENET
1522 hw_p->stats.pkts_rx++;
1527 hw_p->rx_ready[hw_p->rx_i_index] = i;
1529 if (NUM_RX_BUFF == hw_p->rx_i_index)
1530 hw_p->rx_i_index = 0;
1533 if (NUM_RX_BUFF == hw_p->rx_slot)
1537 * free receive buffer only when
1538 * buffer has been handled (eth_rx)
1539 rx[i].ctrl |= MAL_RX_CTRL_EMPTY;
1543 } /* if EMACK_RXCHL */
1547 static int ppc_4xx_eth_rx (struct eth_device *dev)
1552 EMAC_4XX_HW_PST hw_p = dev->priv;
1554 hw_p->is_receiving = 1; /* tell driver */
1558 * use ring buffer and
1559 * get index from rx buffer desciptor queue
1561 user_index = hw_p->rx_ready[hw_p->rx_u_index];
1562 if (user_index == -1) {
1564 break; /* nothing received - leave for() loop */
1568 mtmsr (msr & ~(MSR_EE));
1570 length = hw_p->rx[user_index].data_len;
1572 /* Pass the packet up to the protocol layers. */
1573 /* NetReceive(NetRxPackets[rxIdx], length - 4); */
1574 /* NetReceive(NetRxPackets[i], length); */
1575 NetReceive (NetRxPackets[user_index], length - 4);
1576 /* Free Recv Buffer */
1577 hw_p->rx[user_index].ctrl |= MAL_RX_CTRL_EMPTY;
1578 /* Free rx buffer descriptor queue */
1579 hw_p->rx_ready[hw_p->rx_u_index] = -1;
1581 if (NUM_RX_BUFF == hw_p->rx_u_index)
1582 hw_p->rx_u_index = 0;
1584 #ifdef INFO_4XX_ENET
1585 hw_p->stats.pkts_handled++;
1588 mtmsr (msr); /* Enable IRQ's */
1591 hw_p->is_receiving = 0; /* tell driver */
1596 int ppc_4xx_eth_initialize (bd_t * bis)
1598 static int virgin = 0;
1599 struct eth_device *dev;
1601 EMAC_4XX_HW_PST hw = NULL;
1602 u8 ethaddr[4 + CONFIG_EMAC_NR_START][6];
1605 #if defined(CONFIG_440GX)
1608 mfsdr (sdr_pfc1, pfc1);
1609 pfc1 &= ~(0x01e00000);
1611 mtsdr (sdr_pfc1, pfc1);
1614 /* first clear all mac-addresses */
1615 for (eth_num = 0; eth_num < LAST_EMAC_NUM; eth_num++)
1616 memcpy(ethaddr[eth_num], "\0\0\0\0\0\0", 6);
1618 for (eth_num = 0; eth_num < LAST_EMAC_NUM; eth_num++) {
1620 default: /* fall through */
1622 memcpy(ethaddr[eth_num + CONFIG_EMAC_NR_START],
1623 bis->bi_enetaddr, 6);
1624 hw_addr[eth_num] = 0x0;
1626 #ifdef CONFIG_HAS_ETH1
1628 memcpy(ethaddr[eth_num + CONFIG_EMAC_NR_START],
1629 bis->bi_enet1addr, 6);
1630 hw_addr[eth_num] = 0x100;
1633 #ifdef CONFIG_HAS_ETH2
1635 memcpy(ethaddr[eth_num + CONFIG_EMAC_NR_START],
1636 bis->bi_enet2addr, 6);
1637 hw_addr[eth_num] = 0x400;
1640 #ifdef CONFIG_HAS_ETH3
1642 memcpy(ethaddr[eth_num + CONFIG_EMAC_NR_START],
1643 bis->bi_enet3addr, 6);
1644 hw_addr[eth_num] = 0x600;
1650 /* set phy num and mode */
1651 bis->bi_phynum[0] = CONFIG_PHY_ADDR;
1652 bis->bi_phymode[0] = 0;
1654 #if defined(CONFIG_PHY1_ADDR)
1655 bis->bi_phynum[1] = CONFIG_PHY1_ADDR;
1656 bis->bi_phymode[1] = 0;
1658 #if defined(CONFIG_440GX)
1659 bis->bi_phynum[2] = CONFIG_PHY2_ADDR;
1660 bis->bi_phynum[3] = CONFIG_PHY3_ADDR;
1661 bis->bi_phymode[2] = 2;
1662 bis->bi_phymode[3] = 2;
1665 #if defined(CONFIG_440GX) || \
1666 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
1667 defined(CONFIG_405EX)
1668 ppc_4xx_eth_setup_bridge(0, bis);
1671 for (eth_num = 0; eth_num < LAST_EMAC_NUM; eth_num++) {
1673 * See if we can actually bring up the interface,
1674 * otherwise, skip it
1676 if (memcmp (ethaddr[eth_num], "\0\0\0\0\0\0", 6) == 0) {
1677 bis->bi_phymode[eth_num] = BI_PHYMODE_NONE;
1681 /* Allocate device structure */
1682 dev = (struct eth_device *) malloc (sizeof (*dev));
1684 printf ("ppc_4xx_eth_initialize: "
1685 "Cannot allocate eth_device %d\n", eth_num);
1688 memset(dev, 0, sizeof(*dev));
1690 /* Allocate our private use data */
1691 hw = (EMAC_4XX_HW_PST) malloc (sizeof (*hw));
1693 printf ("ppc_4xx_eth_initialize: "
1694 "Cannot allocate private hw data for eth_device %d",
1699 memset(hw, 0, sizeof(*hw));
1701 hw->hw_addr = hw_addr[eth_num];
1702 memcpy (dev->enetaddr, ethaddr[eth_num], 6);
1703 hw->devnum = eth_num;
1704 hw->print_speed = 1;
1706 sprintf (dev->name, "ppc_4xx_eth%d", eth_num - CONFIG_EMAC_NR_START);
1707 dev->priv = (void *) hw;
1708 dev->init = ppc_4xx_eth_init;
1709 dev->halt = ppc_4xx_eth_halt;
1710 dev->send = ppc_4xx_eth_send;
1711 dev->recv = ppc_4xx_eth_rx;
1714 /* set the MAL IER ??? names may change with new spec ??? */
1715 #if defined(CONFIG_440SPE) || \
1716 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
1717 defined(CONFIG_405EX)
1719 MAL_IER_PT | MAL_IER_PRE | MAL_IER_PWE |
1720 MAL_IER_DE | MAL_IER_OTE | MAL_IER_OE | MAL_IER_PE ;
1723 MAL_IER_DE | MAL_IER_NE | MAL_IER_TE |
1724 MAL_IER_OPBE | MAL_IER_PLBE;
1726 mtdcr (malesr, 0xffffffff); /* clear pending interrupts */
1727 mtdcr (maltxdeir, 0xffffffff); /* clear pending interrupts */
1728 mtdcr (malrxdeir, 0xffffffff); /* clear pending interrupts */
1729 mtdcr (malier, mal_ier);
1731 /* install MAL interrupt handler */
1732 irq_install_handler (VECNUM_MS,
1733 (interrupt_handler_t *) enetInt,
1735 irq_install_handler (VECNUM_MTE,
1736 (interrupt_handler_t *) enetInt,
1738 irq_install_handler (VECNUM_MRE,
1739 (interrupt_handler_t *) enetInt,
1741 irq_install_handler (VECNUM_TXDE,
1742 (interrupt_handler_t *) enetInt,
1744 irq_install_handler (VECNUM_RXDE,
1745 (interrupt_handler_t *) enetInt,
1750 #if defined(CONFIG_NET_MULTI)
1756 #if defined(CONFIG_NET_MULTI)
1757 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
1758 miiphy_register (dev->name,
1759 emac4xx_miiphy_read, emac4xx_miiphy_write);
1762 } /* end for each supported device */
1766 #if !defined(CONFIG_NET_MULTI)
1767 void eth_halt (void) {
1769 ppc_4xx_eth_halt(emac0_dev);
1775 int eth_init (bd_t *bis)
1777 ppc_4xx_eth_initialize(bis);
1779 return ppc_4xx_eth_init(emac0_dev, bis);
1781 printf("ERROR: ethaddr not set!\n");
1786 int eth_send(volatile void *packet, int length)
1788 return (ppc_4xx_eth_send(emac0_dev, packet, length));
1793 return (ppc_4xx_eth_rx(emac0_dev));
1796 int emac4xx_miiphy_initialize (bd_t * bis)
1798 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
1799 miiphy_register ("ppc_4xx_eth0",
1800 emac4xx_miiphy_read, emac4xx_miiphy_write);
1805 #endif /* !defined(CONFIG_NET_MULTI) */