1 /*-----------------------------------------------------------------------------+
3 * This source code has been made available to you by IBM on an AS-IS
4 * basis. Anyone receiving this source is licensed under IBM
5 * copyrights to use it in any way he or she deems fit, including
6 * copying it, modifying it, compiling it, and redistributing it either
7 * with or without modifications. No license under IBM patents or
8 * patent applications is to be implied by the copyright license.
10 * Any user of this software should understand that IBM cannot provide
11 * technical support for this software and will not be responsible for
12 * any consequences resulting from the use of this software.
14 * Any person who transfers this source code or any derivative work
15 * must include the IBM copyright notice, this paragraph, and the
16 * preceding two paragraphs in the transferred software.
18 * COPYRIGHT I B M CORPORATION 1995
19 * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
20 *-----------------------------------------------------------------------------*/
21 /*-----------------------------------------------------------------------------+
23 * File Name: enetemac.c
25 * Function: Device driver for the ethernet EMAC3 macro on the 405GP.
31 * Date Description of Change BY
32 * --------- --------------------- ---
33 * 05-May-99 Created MKW
34 * 27-Jun-99 Clean up JWB
35 * 16-Jul-99 Added MAL error recovery and better IP packet handling MKW
36 * 29-Jul-99 Added Full duplex support MKW
37 * 06-Aug-99 Changed names for Mal CR reg MKW
38 * 23-Aug-99 Turned off SYE when running at 10Mbs MKW
39 * 24-Aug-99 Marked descriptor empty after call_xlc MKW
40 * 07-Sep-99 Set MAL RX buffer size reg to ENET_MAX_MTU_ALIGNED / 16 MCG
41 * to avoid chaining maximum sized packets. Push starting
42 * RX descriptor address up to the next cache line boundary.
43 * 16-Jan-00 Added support for booting with IP of 0x0 MKW
44 * 15-Mar-00 Updated enetInit() to enable broadcast addresses in the
45 * EMAC_RXM register. JWB
46 * 12-Mar-01 anne-sophie.harnois@nextream.fr
47 * - Variables are compatible with those already defined in
49 * - Receive buffer descriptor ring is used to send buffers
51 * - Info print about send/received/handled packet number if
52 * INFO_405_ENET is set
53 * 17-Apr-01 stefan.roese@esd-electronics.com
54 * - MAL reset in "eth_halt" included
55 * - Enet speed and duplex output now in one line
56 * 08-May-01 stefan.roese@esd-electronics.com
57 * - MAL error handling added (eth_init called again)
58 * 13-Nov-01 stefan.roese@esd-electronics.com
59 * - Set IST bit in EMAC_M1 reg upon 100MBit or full duplex
60 * 04-Jan-02 stefan.roese@esd-electronics.com
61 * - Wait for PHY auto negotiation to complete added
62 * 06-Feb-02 stefan.roese@esd-electronics.com
63 * - Bug fixed in waiting for auto negotiation to complete
64 * 26-Feb-02 stefan.roese@esd-electronics.com
65 * - rx and tx buffer descriptors now allocated (no fixed address
67 * 17-Jun-02 stefan.roese@esd-electronics.com
68 * - MAL error debug printf 'M' removed (rx de interrupt may
69 * occur upon many incoming packets with only 4 rx buffers).
70 *-----------------------------------------------------------------------------*
71 * 17-Nov-03 travis.sawyer@sandburst.com
72 * - ported from 405gp_enet.c to utilized upto 4 EMAC ports
73 * in the 440GX. This port should work with the 440GP
75 * 15-Aug-05 sr@denx.de
76 * - merged 405gp_enet.c and 440gx_enet.c to generic 4xx_enet.c
77 now handling all 4xx cpu's.
78 *-----------------------------------------------------------------------------*/
83 #include <asm/processor.h>
86 #include <ppc4xx_enet.h>
93 * Only compile for platform with AMCC EMAC ethernet controller and
94 * network support enabled.
95 * Remark: CONFIG_405 describes Xilinx PPC405 FPGA without EMAC controller!
97 #if (CONFIG_COMMANDS & CFG_CMD_NET) && !defined(CONFIG_405) && !defined(CONFIG_IOP480)
99 #if !(defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII))
100 #error "CONFIG_MII has to be defined!"
103 #if defined(CONFIG_NETCONSOLE) && !defined(CONFIG_NET_MULTI)
104 #error "CONFIG_NET_MULTI has to be defined for NetConsole"
107 #define EMAC_RESET_TIMEOUT 1000 /* 1000 ms reset timeout */
108 #define PHY_AUTONEGOTIATE_TIMEOUT 4000 /* 4000 ms autonegotiate timeout */
110 /* Ethernet Transmit and Receive Buffers */
112 * In the same way ENET_MAX_MTU and ENET_MAX_MTU_ALIGNED are set from
113 * PKTSIZE and PKTSIZE_ALIGN (include/net.h)
115 #define ENET_MAX_MTU PKTSIZE
116 #define ENET_MAX_MTU_ALIGNED PKTSIZE_ALIGN
118 /*-----------------------------------------------------------------------------+
119 * Defines for MAL/EMAC interrupt conditions as reported in the UIC (Universal
120 * Interrupt Controller).
121 *-----------------------------------------------------------------------------*/
122 #define MAL_UIC_ERR ( UIC_MAL_SERR | UIC_MAL_TXDE | UIC_MAL_RXDE)
123 #define MAL_UIC_DEF (UIC_MAL_RXEOB | MAL_UIC_ERR)
124 #define EMAC_UIC_DEF UIC_ENET
125 #define EMAC_UIC_DEF1 UIC_ENET1
126 #define SEL_UIC_DEF(p) (p ? UIC_ENET1 : UIC_ENET )
130 #define BI_PHYMODE_NONE 0
131 #define BI_PHYMODE_ZMII 1
132 #define BI_PHYMODE_RGMII 2
133 #define BI_PHYMODE_GMII 3
134 #define BI_PHYMODE_RTBI 4
135 #define BI_PHYMODE_TBI 5
136 #if defined (CONFIG_440EPX)
137 #define BI_PHYMODE_SMII 6
138 #define BI_PHYMODE_MII 7
141 #if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
142 #define SDR0_MFR_ETH_CLK_SEL_V(n) ((0x01<<27) / (n+1))
145 /*-----------------------------------------------------------------------------+
146 * Global variables. TX and RX descriptors and buffers.
147 *-----------------------------------------------------------------------------*/
149 static uint32_t mal_ier;
151 #if !defined(CONFIG_NET_MULTI)
152 struct eth_device *emac0_dev = NULL;
156 * Get count of EMAC devices (doesn't have to be the max. possible number
157 * supported by the cpu)
159 #if defined(CONFIG_HAS_ETH3)
160 #define LAST_EMAC_NUM 4
161 #elif defined(CONFIG_HAS_ETH2)
162 #define LAST_EMAC_NUM 3
163 #elif defined(CONFIG_HAS_ETH1)
164 #define LAST_EMAC_NUM 2
166 #define LAST_EMAC_NUM 1
169 /*-----------------------------------------------------------------------------+
170 * Prototypes and externals.
171 *-----------------------------------------------------------------------------*/
172 static void enet_rcv (struct eth_device *dev, unsigned long malisr);
174 int enetInt (struct eth_device *dev);
175 static void mal_err (struct eth_device *dev, unsigned long isr,
176 unsigned long uic, unsigned long maldef,
177 unsigned long mal_errr);
178 static void emac_err (struct eth_device *dev, unsigned long isr);
180 extern int phy_setup_aneg (char *devname, unsigned char addr);
181 extern int emac4xx_miiphy_read (char *devname, unsigned char addr,
182 unsigned char reg, unsigned short *value);
183 extern int emac4xx_miiphy_write (char *devname, unsigned char addr,
184 unsigned char reg, unsigned short value);
186 /*-----------------------------------------------------------------------------+
188 | Disable MAL channel, and EMACn
189 +-----------------------------------------------------------------------------*/
190 static void ppc_4xx_eth_halt (struct eth_device *dev)
192 EMAC_4XX_HW_PST hw_p = dev->priv;
193 uint32_t failsafe = 10000;
194 #if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
198 out32 (EMAC_IER + hw_p->hw_addr, 0x00000000); /* disable emac interrupts */
200 /* 1st reset MAL channel */
201 /* Note: writing a 0 to a channel has no effect */
202 #if defined(CONFIG_405EP) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
203 mtdcr (maltxcarr, (MAL_CR_MMSR >> (hw_p->devnum * 2)));
205 mtdcr (maltxcarr, (MAL_CR_MMSR >> hw_p->devnum));
207 mtdcr (malrxcarr, (MAL_CR_MMSR >> hw_p->devnum));
210 while (mfdcr (malrxcasr) & (MAL_CR_MMSR >> hw_p->devnum)) {
211 udelay (1000); /* Delay 1 MS so as not to hammer the register */
218 #if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
219 /* provide clocks for EMAC internal loopback */
220 mfsdr (sdr_mfr, mfr);
221 mfr |= SDR0_MFR_ETH_CLK_SEL_V(hw_p->devnum);
225 out32 (EMAC_M0 + hw_p->hw_addr, EMAC_M0_SRST);
227 #if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
228 /* remove clocks for EMAC internal loopback */
229 mfsdr (sdr_mfr, mfr);
230 mfr &= ~SDR0_MFR_ETH_CLK_SEL_V(hw_p->devnum);
235 #ifndef CONFIG_NETCONSOLE
236 hw_p->print_speed = 1; /* print speed message again next time */
242 #if defined (CONFIG_440GX)
243 int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis)
246 unsigned long zmiifer;
247 unsigned long rmiifer;
249 mfsdr(sdr_pfc1, pfc1);
250 pfc1 = SDR0_PFC1_EPS_DECODE(pfc1);
257 zmiifer |= ZMII_FER_RMII << ZMII_FER_V(0);
258 zmiifer |= ZMII_FER_RMII << ZMII_FER_V(1);
259 zmiifer |= ZMII_FER_RMII << ZMII_FER_V(2);
260 zmiifer |= ZMII_FER_RMII << ZMII_FER_V(3);
261 bis->bi_phymode[0] = BI_PHYMODE_ZMII;
262 bis->bi_phymode[1] = BI_PHYMODE_ZMII;
263 bis->bi_phymode[2] = BI_PHYMODE_ZMII;
264 bis->bi_phymode[3] = BI_PHYMODE_ZMII;
267 zmiifer = ZMII_FER_SMII << ZMII_FER_V(0);
268 zmiifer = ZMII_FER_SMII << ZMII_FER_V(1);
269 zmiifer = ZMII_FER_SMII << ZMII_FER_V(2);
270 zmiifer = ZMII_FER_SMII << ZMII_FER_V(3);
271 bis->bi_phymode[0] = BI_PHYMODE_ZMII;
272 bis->bi_phymode[1] = BI_PHYMODE_ZMII;
273 bis->bi_phymode[2] = BI_PHYMODE_ZMII;
274 bis->bi_phymode[3] = BI_PHYMODE_ZMII;
277 zmiifer |= ZMII_FER_RMII << ZMII_FER_V(0);
278 rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(2);
279 bis->bi_phymode[0] = BI_PHYMODE_ZMII;
280 bis->bi_phymode[1] = BI_PHYMODE_NONE;
281 bis->bi_phymode[2] = BI_PHYMODE_RGMII;
282 bis->bi_phymode[3] = BI_PHYMODE_NONE;
285 zmiifer |= ZMII_FER_SMII << ZMII_FER_V(0);
286 zmiifer |= ZMII_FER_SMII << ZMII_FER_V(1);
287 rmiifer |= RGMII_FER_RGMII << RGMII_FER_V (2);
288 rmiifer |= RGMII_FER_RGMII << RGMII_FER_V (3);
289 bis->bi_phymode[0] = BI_PHYMODE_ZMII;
290 bis->bi_phymode[1] = BI_PHYMODE_ZMII;
291 bis->bi_phymode[2] = BI_PHYMODE_RGMII;
292 bis->bi_phymode[3] = BI_PHYMODE_RGMII;
295 zmiifer |= ZMII_FER_SMII << ZMII_FER_V (0);
296 zmiifer |= ZMII_FER_SMII << ZMII_FER_V (1);
297 zmiifer |= ZMII_FER_SMII << ZMII_FER_V (2);
298 rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(3);
299 bis->bi_phymode[0] = BI_PHYMODE_ZMII;
300 bis->bi_phymode[1] = BI_PHYMODE_ZMII;
301 bis->bi_phymode[2] = BI_PHYMODE_ZMII;
302 bis->bi_phymode[3] = BI_PHYMODE_RGMII;
305 zmiifer |= ZMII_FER_SMII << ZMII_FER_V (0);
306 zmiifer |= ZMII_FER_SMII << ZMII_FER_V (1);
307 rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(2);
308 bis->bi_phymode[0] = BI_PHYMODE_ZMII;
309 bis->bi_phymode[1] = BI_PHYMODE_ZMII;
310 bis->bi_phymode[2] = BI_PHYMODE_RGMII;
314 zmiifer = ZMII_FER_MII << ZMII_FER_V(devnum);
316 bis->bi_phymode[0] = BI_PHYMODE_ZMII;
317 bis->bi_phymode[1] = BI_PHYMODE_ZMII;
318 bis->bi_phymode[2] = BI_PHYMODE_ZMII;
319 bis->bi_phymode[3] = BI_PHYMODE_ZMII;
323 /* Ensure we setup mdio for this devnum and ONLY this devnum */
324 zmiifer |= (ZMII_FER_MDI) << ZMII_FER_V(devnum);
326 out32 (ZMII_FER, zmiifer);
327 out32 (RGMII_FER, rmiifer);
331 #endif /* CONFIG_440_GX */
333 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
334 int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis)
336 unsigned long zmiifer=0x0;
339 * Right now only 2*RGMII is supported. Please extend when needed.
345 out32 (ZMII_FER, 0x00);
346 out32 (RGMII_FER, 0x00000037);
347 bis->bi_phymode[0] = BI_PHYMODE_GMII;
348 bis->bi_phymode[1] = BI_PHYMODE_NONE;
351 /* 2 x RGMII ports */
352 out32 (ZMII_FER, 0x00);
353 out32 (RGMII_FER, 0x00000055);
354 bis->bi_phymode[0] = BI_PHYMODE_RGMII;
355 bis->bi_phymode[1] = BI_PHYMODE_RGMII;
365 /* Ensure we setup mdio for this devnum and ONLY this devnum */
366 zmiifer = in32 (ZMII_FER);
367 zmiifer |= (ZMII_FER_MDI) << ZMII_FER_V(devnum);
368 out32 (ZMII_FER, zmiifer);
372 #endif /* CONFIG_440EPX */
374 static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
377 unsigned long reg = 0;
380 unsigned long duplex;
381 unsigned long failsafe;
383 unsigned short devnum;
384 unsigned short reg_short;
385 #if defined(CONFIG_440GX) || \
386 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
387 defined(CONFIG_440SP) || defined(CONFIG_440SPE)
389 #if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \
390 defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
394 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || defined(CONFIG_440SPE)
399 EMAC_4XX_HW_PST hw_p = dev->priv;
401 /* before doing anything, figure out if we have a MAC address */
403 if (memcmp (dev->enetaddr, "\0\0\0\0\0\0", 6) == 0) {
404 printf("ERROR: ethaddr not set!\n");
408 #if defined(CONFIG_440GX) || \
409 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
410 defined(CONFIG_440SP) || defined(CONFIG_440SPE)
411 /* Need to get the OPB frequency so we can access the PHY */
412 get_sys_info (&sysinfo);
416 mtmsr (msr & ~(MSR_EE)); /* disable interrupts */
418 devnum = hw_p->devnum;
423 * hw_p->stats.pkts_handled <= hw_p->stats.pkts_rx <= hw_p->stats.pkts_handled+PKTBUFSRX
424 * In the most cases hw_p->stats.pkts_handled = hw_p->stats.pkts_rx, but it
425 * is possible that new packets (without relationship with
426 * current transfer) have got the time to arrived before
427 * netloop calls eth_halt
429 printf ("About preceeding transfer (eth%d):\n"
430 "- Sent packet number %d\n"
431 "- Received packet number %d\n"
432 "- Handled packet number %d\n",
435 hw_p->stats.pkts_rx, hw_p->stats.pkts_handled);
437 hw_p->stats.pkts_tx = 0;
438 hw_p->stats.pkts_rx = 0;
439 hw_p->stats.pkts_handled = 0;
440 hw_p->print_speed = 1; /* print speed message again next time */
443 hw_p->tx_err_index = 0; /* Transmit Error Index for tx_err_log */
444 hw_p->rx_err_index = 0; /* Receive Error Index for rx_err_log */
446 hw_p->rx_slot = 0; /* MAL Receive Slot */
447 hw_p->rx_i_index = 0; /* Receive Interrupt Queue Index */
448 hw_p->rx_u_index = 0; /* Receive User Queue Index */
450 hw_p->tx_slot = 0; /* MAL Transmit Slot */
451 hw_p->tx_i_index = 0; /* Transmit Interrupt Queue Index */
452 hw_p->tx_u_index = 0; /* Transmit User Queue Index */
454 #if defined(CONFIG_440) && !defined(CONFIG_440SP) && !defined(CONFIG_440SPE)
456 /* NOTE: 440GX spec states that mode is mutually exclusive */
457 /* NOTE: Therefore, disable all other EMACS, since we handle */
458 /* NOTE: only one emac at a time */
463 #if defined(CONFIG_440EP) || defined(CONFIG_440GR)
464 out32 (ZMII_FER, (ZMII_FER_RMII | ZMII_FER_MDI) << ZMII_FER_V (devnum));
465 #elif defined(CONFIG_440GX) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
466 ethgroup = ppc_4xx_eth_setup_bridge(devnum, bis);
467 #elif defined(CONFIG_440GP)
469 out32 (ZMII_FER, ZMII_RMII | ZMII_MDI0);
471 if ((devnum == 0) || (devnum == 1)) {
472 out32 (ZMII_FER, (ZMII_FER_SMII | ZMII_FER_MDI) << ZMII_FER_V (devnum));
474 else { /* ((devnum == 2) || (devnum == 3)) */
475 out32 (ZMII_FER, ZMII_FER_MDI << ZMII_FER_V (devnum));
476 out32 (RGMII_FER, ((RGMII_FER_RGMII << RGMII_FER_V (2)) |
477 (RGMII_FER_RGMII << RGMII_FER_V (3))));
481 out32 (ZMII_SSR, ZMII_SSR_SP << ZMII_SSR_V(devnum));
482 #endif /* defined(CONFIG_440) && !defined(CONFIG_440SP) */
484 __asm__ volatile ("eieio");
486 /* reset emac so we have access to the phy */
487 #if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
488 /* provide clocks for EMAC internal loopback */
489 mfsdr (sdr_mfr, mfr);
490 mfr |= SDR0_MFR_ETH_CLK_SEL_V(devnum);
494 out32 (EMAC_M0 + hw_p->hw_addr, EMAC_M0_SRST);
495 __asm__ volatile ("eieio");
498 while ((in32 (EMAC_M0 + hw_p->hw_addr) & (EMAC_M0_SRST)) && failsafe) {
503 printf("\nProblem resetting EMAC!\n");
505 #if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
506 /* remove clocks for EMAC internal loopback */
507 mfsdr (sdr_mfr, mfr);
508 mfr &= ~SDR0_MFR_ETH_CLK_SEL_V(devnum);
512 #if defined(CONFIG_440GX) || \
513 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
514 defined(CONFIG_440SP) || defined(CONFIG_440SPE)
515 /* Whack the M1 register */
517 mode_reg &= ~0x00000038;
518 if (sysinfo.freqOPB <= 50000000);
519 else if (sysinfo.freqOPB <= 66666667)
520 mode_reg |= EMAC_M1_OBCI_66;
521 else if (sysinfo.freqOPB <= 83333333)
522 mode_reg |= EMAC_M1_OBCI_83;
523 else if (sysinfo.freqOPB <= 100000000)
524 mode_reg |= EMAC_M1_OBCI_100;
526 mode_reg |= EMAC_M1_OBCI_GT100;
528 out32 (EMAC_M1 + hw_p->hw_addr, mode_reg);
529 #endif /* defined(CONFIG_440GX) || defined(CONFIG_440SP) */
531 /* wait for PHY to complete auto negotiation */
533 #ifndef CONFIG_CS8952_PHY
536 reg = CONFIG_PHY_ADDR;
538 #if defined (CONFIG_PHY1_ADDR)
540 reg = CONFIG_PHY1_ADDR;
543 #if defined (CONFIG_440GX)
545 reg = CONFIG_PHY2_ADDR;
548 reg = CONFIG_PHY3_ADDR;
552 reg = CONFIG_PHY_ADDR;
556 bis->bi_phynum[devnum] = reg;
558 #if defined(CONFIG_PHY_RESET)
560 * Reset the phy, only if its the first time through
561 * otherwise, just check the speeds & feeds
563 if (hw_p->first_init == 0) {
564 #if defined(CONFIG_88E1111_CLK_DELAY)
566 * On some boards (e.g. ALPR) the Marvell 88E1111 PHY needs
567 * the "RGMII transmit timing control" and "RGMII receive
568 * timing control" bits set, so that Gbit communication works
570 * Also set the "Transmitter disable" to 1 to enable the
572 * After setting these bits a soft-reset must occur for this
573 * change to become active.
575 miiphy_read (dev->name, reg, 0x14, ®_short);
576 reg_short |= (1 << 7) | (1 << 1) | (1 << 0);
577 miiphy_write (dev->name, reg, 0x14, reg_short);
579 #if defined(CONFIG_M88E1111_PHY) /* test-only: merge with CONFIG_88E1111_CLK_DELAY !!! */
580 miiphy_write (dev->name, reg, 0x14, 0x0ce3);
581 miiphy_write (dev->name, reg, 0x18, 0x4101);
582 miiphy_write (dev->name, reg, 0x09, 0x0e00);
583 miiphy_write (dev->name, reg, 0x04, 0x01e1);
585 miiphy_reset (dev->name, reg);
587 #if defined(CONFIG_440GX) || \
588 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
589 defined(CONFIG_440SP) || defined(CONFIG_440SPE)
591 #if defined(CONFIG_CIS8201_PHY)
593 * Cicada 8201 PHY needs to have an extended register whacked
596 if (((devnum == 2) || (devnum == 3)) && (4 == ethgroup)) {
597 #if defined(CONFIG_CIS8201_SHORT_ETCH)
598 miiphy_write (dev->name, reg, 23, 0x1300);
600 miiphy_write (dev->name, reg, 23, 0x1000);
603 * Vitesse VSC8201/Cicada CIS8201 errata:
604 * Interoperability problem with Intel 82547EI phys
605 * This work around (provided by Vitesse) changes
606 * the default timer convergence from 8ms to 12ms
608 miiphy_write (dev->name, reg, 0x1f, 0x2a30);
609 miiphy_write (dev->name, reg, 0x08, 0x0200);
610 miiphy_write (dev->name, reg, 0x1f, 0x52b5);
611 miiphy_write (dev->name, reg, 0x02, 0x0004);
612 miiphy_write (dev->name, reg, 0x01, 0x0671);
613 miiphy_write (dev->name, reg, 0x00, 0x8fae);
614 miiphy_write (dev->name, reg, 0x1f, 0x2a30);
615 miiphy_write (dev->name, reg, 0x08, 0x0000);
616 miiphy_write (dev->name, reg, 0x1f, 0x0000);
617 /* end Vitesse/Cicada errata */
621 /* Start/Restart autonegotiation */
622 phy_setup_aneg (dev->name, reg);
625 #endif /* defined(CONFIG_PHY_RESET) */
627 miiphy_read (dev->name, reg, PHY_BMSR, ®_short);
630 * Wait if PHY is capable of autonegotiation and autonegotiation is not complete
632 if ((reg_short & PHY_BMSR_AUTN_ABLE)
633 && !(reg_short & PHY_BMSR_AUTN_COMP)) {
634 puts ("Waiting for PHY auto negotiation to complete");
636 while (!(reg_short & PHY_BMSR_AUTN_COMP)) {
640 if (i > PHY_AUTONEGOTIATE_TIMEOUT) {
641 puts (" TIMEOUT !\n");
645 if ((i++ % 1000) == 0) {
648 udelay (1000); /* 1 ms */
649 miiphy_read (dev->name, reg, PHY_BMSR, ®_short);
653 udelay (500000); /* another 500 ms (results in faster booting) */
655 #endif /* #ifndef CONFIG_CS8952_PHY */
657 speed = miiphy_speed (dev->name, reg);
658 duplex = miiphy_duplex (dev->name, reg);
660 if (hw_p->print_speed) {
661 hw_p->print_speed = 0;
662 printf ("ENET Speed is %d Mbps - %s duplex connection\n",
663 (int) speed, (duplex == HALF) ? "HALF" : "FULL");
666 #if defined(CONFIG_440) && !defined(CONFIG_440SP) && !defined(CONFIG_440SPE) && \
667 !defined(CONFIG_440EPX) && !defined(CONFIG_440GRX)
668 #if defined(CONFIG_440EP) || defined(CONFIG_440GR)
671 reg = (reg & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_RMII_100M;
673 reg = (reg & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_RMII_10M;
678 /* Set ZMII/RGMII speed according to the phy link speed */
679 reg = in32 (ZMII_SSR);
680 if ( (speed == 100) || (speed == 1000) )
681 out32 (ZMII_SSR, reg | (ZMII_SSR_SP << ZMII_SSR_V (devnum)));
683 out32 (ZMII_SSR, reg & (~(ZMII_SSR_SP << ZMII_SSR_V (devnum))));
685 if ((devnum == 2) || (devnum == 3)) {
687 reg = (RGMII_SSR_SP_1000MBPS << RGMII_SSR_V (devnum));
688 else if (speed == 100)
689 reg = (RGMII_SSR_SP_100MBPS << RGMII_SSR_V (devnum));
690 else if (speed == 10)
691 reg = (RGMII_SSR_SP_10MBPS << RGMII_SSR_V (devnum));
693 printf("Error in RGMII Speed\n");
696 out32 (RGMII_SSR, reg);
698 #endif /* defined(CONFIG_440) && !defined(CONFIG_440SP) */
700 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
702 reg = (RGMII_SSR_SP_1000MBPS << RGMII_SSR_V (devnum));
703 else if (speed == 100)
704 reg = (RGMII_SSR_SP_100MBPS << RGMII_SSR_V (devnum));
705 else if (speed == 10)
706 reg = (RGMII_SSR_SP_10MBPS << RGMII_SSR_V (devnum));
708 printf("Error in RGMII Speed\n");
711 out32 (RGMII_SSR, reg);
714 /* set the Mal configuration reg */
715 #if defined(CONFIG_440GX) || \
716 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
717 defined(CONFIG_440SP) || defined(CONFIG_440SPE)
718 mtdcr (malmcr, MAL_CR_PLBB | MAL_CR_OPBBL | MAL_CR_LEA |
719 MAL_CR_PLBLT_DEFAULT | MAL_CR_EOPIE | 0x00330000);
721 mtdcr (malmcr, MAL_CR_PLBB | MAL_CR_OPBBL | MAL_CR_LEA | MAL_CR_PLBLT_DEFAULT);
722 /* Errata 1.12: MAL_1 -- Disable MAL bursting */
723 if (get_pvr() == PVR_440GP_RB) {
724 mtdcr (malmcr, mfdcr(malmcr) & ~MAL_CR_PLBB);
728 /* Free "old" buffers */
729 if (hw_p->alloc_tx_buf)
730 free (hw_p->alloc_tx_buf);
731 if (hw_p->alloc_rx_buf)
732 free (hw_p->alloc_rx_buf);
735 * Malloc MAL buffer desciptors, make sure they are
736 * aligned on cache line boundary size
737 * (401/403/IOP480 = 16, 405 = 32)
738 * and doesn't cross cache block boundaries.
741 (mal_desc_t *) malloc ((sizeof (mal_desc_t) * NUM_TX_BUFF) +
742 ((2 * CFG_CACHELINE_SIZE) - 2));
743 if (NULL == hw_p->alloc_tx_buf)
745 if (((int) hw_p->alloc_tx_buf & CACHELINE_MASK) != 0) {
747 (mal_desc_t *) ((int) hw_p->alloc_tx_buf +
750 alloc_tx_buf & CACHELINE_MASK));
752 hw_p->tx = hw_p->alloc_tx_buf;
756 (mal_desc_t *) malloc ((sizeof (mal_desc_t) * NUM_RX_BUFF) +
757 ((2 * CFG_CACHELINE_SIZE) - 2));
758 if (NULL == hw_p->alloc_rx_buf) {
759 free(hw_p->alloc_tx_buf);
760 hw_p->alloc_tx_buf = NULL;
764 if (((int) hw_p->alloc_rx_buf & CACHELINE_MASK) != 0) {
766 (mal_desc_t *) ((int) hw_p->alloc_rx_buf +
769 alloc_rx_buf & CACHELINE_MASK));
771 hw_p->rx = hw_p->alloc_rx_buf;
774 for (i = 0; i < NUM_TX_BUFF; i++) {
775 hw_p->tx[i].ctrl = 0;
776 hw_p->tx[i].data_len = 0;
777 if (hw_p->first_init == 0) {
779 (char *) malloc (ENET_MAX_MTU_ALIGNED);
780 if (NULL == hw_p->txbuf_ptr) {
781 free(hw_p->alloc_rx_buf);
782 free(hw_p->alloc_tx_buf);
783 hw_p->alloc_rx_buf = NULL;
784 hw_p->alloc_tx_buf = NULL;
785 for(j = 0; j < i; j++) {
786 free(hw_p->tx[i].data_ptr);
787 hw_p->tx[i].data_ptr = NULL;
791 hw_p->tx[i].data_ptr = hw_p->txbuf_ptr;
792 if ((NUM_TX_BUFF - 1) == i)
793 hw_p->tx[i].ctrl |= MAL_TX_CTRL_WRAP;
794 hw_p->tx_run[i] = -1;
796 printf ("TX_BUFF %d @ 0x%08lx\n", i,
797 (ulong) hw_p->tx[i].data_ptr);
801 for (i = 0; i < NUM_RX_BUFF; i++) {
802 hw_p->rx[i].ctrl = 0;
803 hw_p->rx[i].data_len = 0;
804 /* rx[i].data_ptr = (char *) &rx_buff[i]; */
805 hw_p->rx[i].data_ptr = (char *) NetRxPackets[i];
806 if ((NUM_RX_BUFF - 1) == i)
807 hw_p->rx[i].ctrl |= MAL_RX_CTRL_WRAP;
808 hw_p->rx[i].ctrl |= MAL_RX_CTRL_EMPTY | MAL_RX_CTRL_INTR;
809 hw_p->rx_ready[i] = -1;
811 printf ("RX_BUFF %d @ 0x%08lx\n", i, (ulong) rx[i].data_ptr);
817 reg |= dev->enetaddr[0]; /* set high address */
819 reg |= dev->enetaddr[1];
821 out32 (EMAC_IAH + hw_p->hw_addr, reg);
824 reg |= dev->enetaddr[2]; /* set low address */
826 reg |= dev->enetaddr[3];
828 reg |= dev->enetaddr[4];
830 reg |= dev->enetaddr[5];
832 out32 (EMAC_IAL + hw_p->hw_addr, reg);
836 /* setup MAL tx & rx channel pointers */
837 #if defined (CONFIG_405EP) || defined (CONFIG_440EP) || defined (CONFIG_440GR)
838 mtdcr (maltxctp2r, hw_p->tx);
840 mtdcr (maltxctp1r, hw_p->tx);
842 #if defined(CONFIG_440)
843 mtdcr (maltxbattr, 0x0);
844 mtdcr (malrxbattr, 0x0);
846 mtdcr (malrxctp1r, hw_p->rx);
847 /* set RX buffer size */
848 mtdcr (malrcbs1, ENET_MAX_MTU_ALIGNED / 16);
850 #if defined (CONFIG_440GX)
852 /* setup MAL tx & rx channel pointers */
853 mtdcr (maltxbattr, 0x0);
854 mtdcr (malrxbattr, 0x0);
855 mtdcr (maltxctp2r, hw_p->tx);
856 mtdcr (malrxctp2r, hw_p->rx);
857 /* set RX buffer size */
858 mtdcr (malrcbs2, ENET_MAX_MTU_ALIGNED / 16);
861 /* setup MAL tx & rx channel pointers */
862 mtdcr (maltxbattr, 0x0);
863 mtdcr (maltxctp3r, hw_p->tx);
864 mtdcr (malrxbattr, 0x0);
865 mtdcr (malrxctp3r, hw_p->rx);
866 /* set RX buffer size */
867 mtdcr (malrcbs3, ENET_MAX_MTU_ALIGNED / 16);
869 #endif /* CONFIG_440GX */
872 /* setup MAL tx & rx channel pointers */
873 #if defined(CONFIG_440)
874 mtdcr (maltxbattr, 0x0);
875 mtdcr (malrxbattr, 0x0);
877 mtdcr (maltxctp0r, hw_p->tx);
878 mtdcr (malrxctp0r, hw_p->rx);
879 /* set RX buffer size */
880 mtdcr (malrcbs0, ENET_MAX_MTU_ALIGNED / 16);
884 /* Enable MAL transmit and receive channels */
885 #if defined(CONFIG_405EP) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
886 mtdcr (maltxcasr, (MAL_TXRX_CASR >> (hw_p->devnum*2)));
888 mtdcr (maltxcasr, (MAL_TXRX_CASR >> hw_p->devnum));
890 mtdcr (malrxcasr, (MAL_TXRX_CASR >> hw_p->devnum));
892 /* set transmit enable & receive enable */
893 out32 (EMAC_M0 + hw_p->hw_addr, EMAC_M0_TXE | EMAC_M0_RXE);
895 /* set receive fifo to 4k and tx fifo to 2k */
896 mode_reg = in32 (EMAC_M1 + hw_p->hw_addr);
897 mode_reg |= EMAC_M1_RFS_4K | EMAC_M1_TX_FIFO_2K;
900 if (speed == _1000BASET) {
901 #if defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
902 defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
905 mfsdr (sdr_pfc1, pfc1);
906 pfc1 |= SDR0_PFC1_EM_1000;
907 mtsdr (sdr_pfc1, pfc1);
909 mode_reg = mode_reg | EMAC_M1_MF_1000MBPS | EMAC_M1_IST;
910 } else if (speed == _100BASET)
911 mode_reg = mode_reg | EMAC_M1_MF_100MBPS | EMAC_M1_IST;
913 mode_reg = mode_reg & ~0x00C00000; /* 10 MBPS */
915 mode_reg = mode_reg | 0x80000000 | EMAC_M1_IST;
917 out32 (EMAC_M1 + hw_p->hw_addr, mode_reg);
919 /* Enable broadcast and indvidual address */
920 /* TBS: enabling runts as some misbehaved nics will send runts */
921 out32 (EMAC_RXM + hw_p->hw_addr, EMAC_RMR_BAE | EMAC_RMR_IAE);
923 /* we probably need to set the tx mode1 reg? maybe at tx time */
925 /* set transmit request threshold register */
926 out32 (EMAC_TRTR + hw_p->hw_addr, 0x18000000); /* 256 byte threshold */
928 /* set receive low/high water mark register */
929 #if defined(CONFIG_440)
930 /* 440s has a 64 byte burst length */
931 out32 (EMAC_RX_HI_LO_WMARK + hw_p->hw_addr, 0x80009000);
933 /* 405s have a 16 byte burst length */
934 out32 (EMAC_RX_HI_LO_WMARK + hw_p->hw_addr, 0x0f002000);
935 #endif /* defined(CONFIG_440) */
936 out32 (EMAC_TXM1 + hw_p->hw_addr, 0xf8640000);
938 /* Set fifo limit entry in tx mode 0 */
939 out32 (EMAC_TXM0 + hw_p->hw_addr, 0x00000003);
941 out32 (EMAC_I_FRAME_GAP_REG + hw_p->hw_addr, 0x00000008);
944 hw_p->emac_ier = EMAC_ISR_PTLE | EMAC_ISR_BFCS | EMAC_ISR_ORE | EMAC_ISR_IRE;
945 if (speed == _100BASET)
946 hw_p->emac_ier = hw_p->emac_ier | EMAC_ISR_SYE;
948 out32 (EMAC_ISR + hw_p->hw_addr, 0xffffffff); /* clear pending interrupts */
949 out32 (EMAC_IER + hw_p->hw_addr, hw_p->emac_ier);
951 if (hw_p->first_init == 0) {
953 * Connect interrupt service routines
955 irq_install_handler (VECNUM_ETH0 + (hw_p->devnum * 2),
956 (interrupt_handler_t *) enetInt, dev);
959 mtmsr (msr); /* enable interrupts again */
962 hw_p->first_init = 1;
968 static int ppc_4xx_eth_send (struct eth_device *dev, volatile void *ptr,
971 struct enet_frame *ef_ptr;
972 ulong time_start, time_now;
973 unsigned long temp_txm0;
974 EMAC_4XX_HW_PST hw_p = dev->priv;
976 ef_ptr = (struct enet_frame *) ptr;
978 /*-----------------------------------------------------------------------+
979 * Copy in our address into the frame.
980 *-----------------------------------------------------------------------*/
981 (void) memcpy (ef_ptr->source_addr, dev->enetaddr, ENET_ADDR_LENGTH);
983 /*-----------------------------------------------------------------------+
984 * If frame is too long or too short, modify length.
985 *-----------------------------------------------------------------------*/
986 /* TBS: where does the fragment go???? */
987 if (len > ENET_MAX_MTU)
990 /* memcpy ((void *) &tx_buff[tx_slot], (const void *) ptr, len); */
991 memcpy ((void *) hw_p->txbuf_ptr, (const void *) ptr, len);
993 /*-----------------------------------------------------------------------+
994 * set TX Buffer busy, and send it
995 *-----------------------------------------------------------------------*/
996 hw_p->tx[hw_p->tx_slot].ctrl = (MAL_TX_CTRL_LAST |
997 EMAC_TX_CTRL_GFCS | EMAC_TX_CTRL_GP) &
998 ~(EMAC_TX_CTRL_ISA | EMAC_TX_CTRL_RSA);
999 if ((NUM_TX_BUFF - 1) == hw_p->tx_slot)
1000 hw_p->tx[hw_p->tx_slot].ctrl |= MAL_TX_CTRL_WRAP;
1002 hw_p->tx[hw_p->tx_slot].data_len = (short) len;
1003 hw_p->tx[hw_p->tx_slot].ctrl |= MAL_TX_CTRL_READY;
1005 __asm__ volatile ("eieio");
1007 out32 (EMAC_TXM0 + hw_p->hw_addr,
1008 in32 (EMAC_TXM0 + hw_p->hw_addr) | EMAC_TXM0_GNP0);
1009 #ifdef INFO_4XX_ENET
1010 hw_p->stats.pkts_tx++;
1013 /*-----------------------------------------------------------------------+
1014 * poll unitl the packet is sent and then make sure it is OK
1015 *-----------------------------------------------------------------------*/
1016 time_start = get_timer (0);
1018 temp_txm0 = in32 (EMAC_TXM0 + hw_p->hw_addr);
1019 /* loop until either TINT turns on or 3 seconds elapse */
1020 if ((temp_txm0 & EMAC_TXM0_GNP0) != 0) {
1021 /* transmit is done, so now check for errors
1022 * If there is an error, an interrupt should
1023 * happen when we return
1025 time_now = get_timer (0);
1026 if ((time_now - time_start) > 3000) {
1036 #if defined (CONFIG_440)
1038 #if defined(CONFIG_440SP) || defined(CONFIG_440SPE)
1040 * Hack: On 440SP all enet irq sources are located on UIC1
1041 * Needs some cleanup. --sr
1043 #define UIC0MSR uic1msr
1044 #define UIC0SR uic1sr
1046 #define UIC0MSR uic0msr
1047 #define UIC0SR uic0sr
1050 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
1051 #define UICMSR_ETHX uic0msr
1052 #define UICSR_ETHX uic0sr
1054 #define UICMSR_ETHX uic1msr
1055 #define UICSR_ETHX uic1sr
1058 int enetInt (struct eth_device *dev)
1061 int rc = -1; /* default to not us */
1062 unsigned long mal_isr;
1063 unsigned long emac_isr = 0;
1064 unsigned long mal_rx_eob;
1065 unsigned long my_uic0msr, my_uic1msr;
1066 unsigned long my_uicmsr_ethx;
1068 #if defined(CONFIG_440GX)
1069 unsigned long my_uic2msr;
1071 EMAC_4XX_HW_PST hw_p;
1074 * Because the mal is generic, we need to get the current
1077 #if defined(CONFIG_NET_MULTI)
1078 dev = eth_get_dev();
1085 /* enter loop that stays in interrupt code until nothing to service */
1089 my_uic0msr = mfdcr (UIC0MSR);
1090 my_uic1msr = mfdcr (uic1msr);
1091 #if defined(CONFIG_440GX)
1092 my_uic2msr = mfdcr (uic2msr);
1094 my_uicmsr_ethx = mfdcr (UICMSR_ETHX);
1096 if (!(my_uic0msr & (UIC_MRE | UIC_MTE))
1097 && !(my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))
1098 && !(my_uicmsr_ethx & (UIC_ETH0 | UIC_ETH1))) {
1102 #if defined (CONFIG_440GX)
1103 if (!(my_uic0msr & (UIC_MRE | UIC_MTE))
1104 && !(my_uic2msr & (UIC_ETH2 | UIC_ETH3))) {
1109 /* get and clear controller status interrupts */
1110 /* look at Mal and EMAC interrupts */
1111 if ((my_uic0msr & (UIC_MRE | UIC_MTE))
1112 || (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) {
1113 /* we have a MAL interrupt */
1114 mal_isr = mfdcr (malesr);
1115 /* look for mal error */
1116 if (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE)) {
1117 mal_err (dev, mal_isr, my_uic1msr, MAL_UIC_DEF, MAL_UIC_ERR);
1123 /* port by port dispatch of emac interrupts */
1124 if (hw_p->devnum == 0) {
1125 if (UIC_ETH0 & my_uicmsr_ethx) { /* look for EMAC errors */
1126 emac_isr = in32 (EMAC_ISR + hw_p->hw_addr);
1127 if ((hw_p->emac_ier & emac_isr) != 0) {
1128 emac_err (dev, emac_isr);
1133 if ((hw_p->emac_ier & emac_isr)
1134 || (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) {
1135 mtdcr (UIC0SR, UIC_MRE | UIC_MTE); /* Clear */
1136 mtdcr (uic1sr, UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */
1137 mtdcr (UICSR_ETHX, UIC_ETH0); /* Clear */
1138 return (rc); /* we had errors so get out */
1142 #if !defined(CONFIG_440SP)
1143 if (hw_p->devnum == 1) {
1144 if (UIC_ETH1 & my_uicmsr_ethx) { /* look for EMAC errors */
1145 emac_isr = in32 (EMAC_ISR + hw_p->hw_addr);
1146 if ((hw_p->emac_ier & emac_isr) != 0) {
1147 emac_err (dev, emac_isr);
1152 if ((hw_p->emac_ier & emac_isr)
1153 || (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) {
1154 mtdcr (UIC0SR, UIC_MRE | UIC_MTE); /* Clear */
1155 mtdcr (uic1sr, UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */
1156 mtdcr (UICSR_ETHX, UIC_ETH1); /* Clear */
1157 return (rc); /* we had errors so get out */
1160 #if defined (CONFIG_440GX)
1161 if (hw_p->devnum == 2) {
1162 if (UIC_ETH2 & my_uic2msr) { /* look for EMAC errors */
1163 emac_isr = in32 (EMAC_ISR + hw_p->hw_addr);
1164 if ((hw_p->emac_ier & emac_isr) != 0) {
1165 emac_err (dev, emac_isr);
1170 if ((hw_p->emac_ier & emac_isr)
1171 || (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) {
1172 mtdcr (UIC0SR, UIC_MRE | UIC_MTE); /* Clear */
1173 mtdcr (uic1sr, UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */
1174 mtdcr (uic2sr, UIC_ETH2);
1175 return (rc); /* we had errors so get out */
1179 if (hw_p->devnum == 3) {
1180 if (UIC_ETH3 & my_uic2msr) { /* look for EMAC errors */
1181 emac_isr = in32 (EMAC_ISR + hw_p->hw_addr);
1182 if ((hw_p->emac_ier & emac_isr) != 0) {
1183 emac_err (dev, emac_isr);
1188 if ((hw_p->emac_ier & emac_isr)
1189 || (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) {
1190 mtdcr (UIC0SR, UIC_MRE | UIC_MTE); /* Clear */
1191 mtdcr (uic1sr, UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */
1192 mtdcr (uic2sr, UIC_ETH3);
1193 return (rc); /* we had errors so get out */
1196 #endif /* CONFIG_440GX */
1197 #endif /* !CONFIG_440SP */
1199 /* handle MAX TX EOB interrupt from a tx */
1200 if (my_uic0msr & UIC_MTE) {
1201 mal_rx_eob = mfdcr (maltxeobisr);
1202 mtdcr (maltxeobisr, mal_rx_eob);
1203 mtdcr (UIC0SR, UIC_MTE);
1205 /* handle MAL RX EOB interupt from a receive */
1206 /* check for EOB on valid channels */
1207 if (my_uic0msr & UIC_MRE) {
1208 mal_rx_eob = mfdcr (malrxeobisr);
1209 if ((mal_rx_eob & (0x80000000 >> hw_p->devnum)) != 0) { /* call emac routine for channel x */
1211 mtdcr(malrxeobisr, mal_rx_eob); */
1212 enet_rcv (dev, emac_isr);
1213 /* indicate that we serviced an interrupt */
1219 mtdcr (UIC0SR, UIC_MRE); /* Clear */
1220 mtdcr (uic1sr, UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */
1221 switch (hw_p->devnum) {
1223 mtdcr (UICSR_ETHX, UIC_ETH0);
1226 mtdcr (UICSR_ETHX, UIC_ETH1);
1228 #if defined (CONFIG_440GX)
1230 mtdcr (uic2sr, UIC_ETH2);
1233 mtdcr (uic2sr, UIC_ETH3);
1235 #endif /* CONFIG_440GX */
1244 #else /* CONFIG_440 */
1246 int enetInt (struct eth_device *dev)
1249 int rc = -1; /* default to not us */
1250 unsigned long mal_isr;
1251 unsigned long emac_isr = 0;
1252 unsigned long mal_rx_eob;
1253 unsigned long my_uicmsr;
1255 EMAC_4XX_HW_PST hw_p;
1258 * Because the mal is generic, we need to get the current
1261 #if defined(CONFIG_NET_MULTI)
1262 dev = eth_get_dev();
1269 /* enter loop that stays in interrupt code until nothing to service */
1273 my_uicmsr = mfdcr (uicmsr);
1275 if ((my_uicmsr & (MAL_UIC_DEF | EMAC_UIC_DEF)) == 0) { /* not for us */
1278 /* get and clear controller status interrupts */
1279 /* look at Mal and EMAC interrupts */
1280 if ((MAL_UIC_DEF & my_uicmsr) != 0) { /* we have a MAL interrupt */
1281 mal_isr = mfdcr (malesr);
1282 /* look for mal error */
1283 if ((my_uicmsr & MAL_UIC_ERR) != 0) {
1284 mal_err (dev, mal_isr, my_uicmsr, MAL_UIC_DEF, MAL_UIC_ERR);
1290 /* port by port dispatch of emac interrupts */
1292 if ((SEL_UIC_DEF(hw_p->devnum) & my_uicmsr) != 0) { /* look for EMAC errors */
1293 emac_isr = in32 (EMAC_ISR + hw_p->hw_addr);
1294 if ((hw_p->emac_ier & emac_isr) != 0) {
1295 emac_err (dev, emac_isr);
1300 if (((hw_p->emac_ier & emac_isr) != 0) || ((MAL_UIC_ERR & my_uicmsr) != 0)) {
1301 mtdcr (uicsr, MAL_UIC_DEF | SEL_UIC_DEF(hw_p->devnum)); /* Clear */
1302 return (rc); /* we had errors so get out */
1305 /* handle MAX TX EOB interrupt from a tx */
1306 if (my_uicmsr & UIC_MAL_TXEOB) {
1307 mal_rx_eob = mfdcr (maltxeobisr);
1308 mtdcr (maltxeobisr, mal_rx_eob);
1309 mtdcr (uicsr, UIC_MAL_TXEOB);
1311 /* handle MAL RX EOB interupt from a receive */
1312 /* check for EOB on valid channels */
1313 if (my_uicmsr & UIC_MAL_RXEOB)
1315 mal_rx_eob = mfdcr (malrxeobisr);
1316 if ((mal_rx_eob & (0x80000000 >> hw_p->devnum)) != 0) { /* call emac routine for channel x */
1318 mtdcr(malrxeobisr, mal_rx_eob); */
1319 enet_rcv (dev, emac_isr);
1320 /* indicate that we serviced an interrupt */
1325 mtdcr (uicsr, MAL_UIC_DEF|EMAC_UIC_DEF|EMAC_UIC_DEF1); /* Clear */
1332 #endif /* CONFIG_440 */
1334 /*-----------------------------------------------------------------------------+
1336 *-----------------------------------------------------------------------------*/
1337 static void mal_err (struct eth_device *dev, unsigned long isr,
1338 unsigned long uic, unsigned long maldef,
1339 unsigned long mal_errr)
1341 EMAC_4XX_HW_PST hw_p = dev->priv;
1343 mtdcr (malesr, isr); /* clear interrupt */
1345 /* clear DE interrupt */
1346 mtdcr (maltxdeir, 0xC0000000);
1347 mtdcr (malrxdeir, 0x80000000);
1349 #ifdef INFO_4XX_ENET
1350 printf ("\nMAL error occured.... ISR = %lx UIC = = %lx MAL_DEF = %lx MAL_ERR= %lx \n", isr, uic, maldef, mal_errr);
1353 eth_init (hw_p->bis); /* start again... */
1356 /*-----------------------------------------------------------------------------+
1357 * EMAC Error Routine
1358 *-----------------------------------------------------------------------------*/
1359 static void emac_err (struct eth_device *dev, unsigned long isr)
1361 EMAC_4XX_HW_PST hw_p = dev->priv;
1363 printf ("EMAC%d error occured.... ISR = %lx\n", hw_p->devnum, isr);
1364 out32 (EMAC_ISR + hw_p->hw_addr, isr);
1367 /*-----------------------------------------------------------------------------+
1368 * enet_rcv() handles the ethernet receive data
1369 *-----------------------------------------------------------------------------*/
1370 static void enet_rcv (struct eth_device *dev, unsigned long malisr)
1372 struct enet_frame *ef_ptr;
1373 unsigned long data_len;
1374 unsigned long rx_eob_isr;
1375 EMAC_4XX_HW_PST hw_p = dev->priv;
1381 rx_eob_isr = mfdcr (malrxeobisr);
1382 if ((0x80000000 >> hw_p->devnum) & rx_eob_isr) {
1384 mtdcr (malrxeobisr, rx_eob_isr);
1387 while (1) { /* do all */
1390 if ((MAL_RX_CTRL_EMPTY & hw_p->rx[i].ctrl)
1391 || (loop_count >= NUM_RX_BUFF))
1395 if (NUM_RX_BUFF == hw_p->rx_slot)
1398 data_len = (unsigned long) hw_p->rx[i].data_len; /* Get len */
1400 if (data_len > ENET_MAX_MTU) /* Check len */
1403 if (EMAC_RX_ERRORS & hw_p->rx[i].ctrl) { /* Check Errors */
1405 hw_p->stats.rx_err_log[hw_p->
1408 hw_p->rx_err_index++;
1409 if (hw_p->rx_err_index ==
1411 hw_p->rx_err_index =
1414 } /* data_len < max mtu */
1416 if (!data_len) { /* no data */
1417 hw_p->rx[i].ctrl |= MAL_RX_CTRL_EMPTY; /* Free Recv Buffer */
1419 hw_p->stats.data_len_err++; /* Error at Rx */
1424 /* Check if user has already eaten buffer */
1425 /* if not => ERROR */
1426 else if (hw_p->rx_ready[hw_p->rx_i_index] != -1) {
1427 if (hw_p->is_receiving)
1428 printf ("ERROR : Receive buffers are full!\n");
1431 hw_p->stats.rx_frames++;
1432 hw_p->stats.rx += data_len;
1433 ef_ptr = (struct enet_frame *) hw_p->rx[i].
1435 #ifdef INFO_4XX_ENET
1436 hw_p->stats.pkts_rx++;
1441 hw_p->rx_ready[hw_p->rx_i_index] = i;
1443 if (NUM_RX_BUFF == hw_p->rx_i_index)
1444 hw_p->rx_i_index = 0;
1447 * free receive buffer only when
1448 * buffer has been handled (eth_rx)
1449 rx[i].ctrl |= MAL_RX_CTRL_EMPTY;
1453 } /* if EMACK_RXCHL */
1457 static int ppc_4xx_eth_rx (struct eth_device *dev)
1462 EMAC_4XX_HW_PST hw_p = dev->priv;
1464 hw_p->is_receiving = 1; /* tell driver */
1468 * use ring buffer and
1469 * get index from rx buffer desciptor queue
1471 user_index = hw_p->rx_ready[hw_p->rx_u_index];
1472 if (user_index == -1) {
1474 break; /* nothing received - leave for() loop */
1478 mtmsr (msr & ~(MSR_EE));
1480 length = hw_p->rx[user_index].data_len;
1482 /* Pass the packet up to the protocol layers. */
1483 /* NetReceive(NetRxPackets[rxIdx], length - 4); */
1484 /* NetReceive(NetRxPackets[i], length); */
1485 NetReceive (NetRxPackets[user_index], length - 4);
1486 /* Free Recv Buffer */
1487 hw_p->rx[user_index].ctrl |= MAL_RX_CTRL_EMPTY;
1488 /* Free rx buffer descriptor queue */
1489 hw_p->rx_ready[hw_p->rx_u_index] = -1;
1491 if (NUM_RX_BUFF == hw_p->rx_u_index)
1492 hw_p->rx_u_index = 0;
1494 #ifdef INFO_4XX_ENET
1495 hw_p->stats.pkts_handled++;
1498 mtmsr (msr); /* Enable IRQ's */
1501 hw_p->is_receiving = 0; /* tell driver */
1506 int ppc_4xx_eth_initialize (bd_t * bis)
1508 static int virgin = 0;
1509 struct eth_device *dev;
1511 EMAC_4XX_HW_PST hw = NULL;
1513 #if defined(CONFIG_440GX)
1516 mfsdr (sdr_pfc1, pfc1);
1517 pfc1 &= ~(0x01e00000);
1519 mtsdr (sdr_pfc1, pfc1);
1521 /* set phy num and mode */
1522 bis->bi_phynum[0] = CONFIG_PHY_ADDR;
1523 bis->bi_phymode[0] = 0;
1525 #if defined(CONFIG_PHY1_ADDR)
1526 bis->bi_phynum[1] = CONFIG_PHY1_ADDR;
1527 bis->bi_phymode[1] = 0;
1529 #if defined(CONFIG_440GX)
1530 bis->bi_phynum[2] = CONFIG_PHY2_ADDR;
1531 bis->bi_phynum[3] = CONFIG_PHY3_ADDR;
1532 bis->bi_phymode[2] = 2;
1533 bis->bi_phymode[3] = 2;
1535 ppc_4xx_eth_setup_bridge(0, bis);
1538 for (eth_num = 0; eth_num < LAST_EMAC_NUM; eth_num++) {
1540 /* See if we can actually bring up the interface, otherwise, skip it */
1542 default: /* fall through */
1544 if (memcmp (bis->bi_enetaddr, "\0\0\0\0\0\0", 6) == 0) {
1545 bis->bi_phymode[eth_num] = BI_PHYMODE_NONE;
1549 #ifdef CONFIG_HAS_ETH1
1551 if (memcmp (bis->bi_enet1addr, "\0\0\0\0\0\0", 6) == 0) {
1552 bis->bi_phymode[eth_num] = BI_PHYMODE_NONE;
1557 #ifdef CONFIG_HAS_ETH2
1559 if (memcmp (bis->bi_enet2addr, "\0\0\0\0\0\0", 6) == 0) {
1560 bis->bi_phymode[eth_num] = BI_PHYMODE_NONE;
1565 #ifdef CONFIG_HAS_ETH3
1567 if (memcmp (bis->bi_enet3addr, "\0\0\0\0\0\0", 6) == 0) {
1568 bis->bi_phymode[eth_num] = BI_PHYMODE_NONE;
1575 /* Allocate device structure */
1576 dev = (struct eth_device *) malloc (sizeof (*dev));
1578 printf ("ppc_4xx_eth_initialize: "
1579 "Cannot allocate eth_device %d\n", eth_num);
1582 memset(dev, 0, sizeof(*dev));
1584 /* Allocate our private use data */
1585 hw = (EMAC_4XX_HW_PST) malloc (sizeof (*hw));
1587 printf ("ppc_4xx_eth_initialize: "
1588 "Cannot allocate private hw data for eth_device %d",
1593 memset(hw, 0, sizeof(*hw));
1596 default: /* fall through */
1599 memcpy (dev->enetaddr, bis->bi_enetaddr, 6);
1601 #ifdef CONFIG_HAS_ETH1
1603 hw->hw_addr = 0x100;
1604 memcpy (dev->enetaddr, bis->bi_enet1addr, 6);
1607 #ifdef CONFIG_HAS_ETH2
1609 hw->hw_addr = 0x400;
1610 memcpy (dev->enetaddr, bis->bi_enet2addr, 6);
1613 #ifdef CONFIG_HAS_ETH3
1615 hw->hw_addr = 0x600;
1616 memcpy (dev->enetaddr, bis->bi_enet3addr, 6);
1621 hw->devnum = eth_num;
1622 hw->print_speed = 1;
1624 sprintf (dev->name, "ppc_4xx_eth%d", eth_num);
1625 dev->priv = (void *) hw;
1626 dev->init = ppc_4xx_eth_init;
1627 dev->halt = ppc_4xx_eth_halt;
1628 dev->send = ppc_4xx_eth_send;
1629 dev->recv = ppc_4xx_eth_rx;
1632 /* set the MAL IER ??? names may change with new spec ??? */
1633 #if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
1635 MAL_IER_PT | MAL_IER_PRE | MAL_IER_PWE |
1636 MAL_IER_DE | MAL_IER_OTE | MAL_IER_OE | MAL_IER_PE ;
1639 MAL_IER_DE | MAL_IER_NE | MAL_IER_TE |
1640 MAL_IER_OPBE | MAL_IER_PLBE;
1642 mtdcr (malesr, 0xffffffff); /* clear pending interrupts */
1643 mtdcr (maltxdeir, 0xffffffff); /* clear pending interrupts */
1644 mtdcr (malrxdeir, 0xffffffff); /* clear pending interrupts */
1645 mtdcr (malier, mal_ier);
1647 /* install MAL interrupt handler */
1648 irq_install_handler (VECNUM_MS,
1649 (interrupt_handler_t *) enetInt,
1651 irq_install_handler (VECNUM_MTE,
1652 (interrupt_handler_t *) enetInt,
1654 irq_install_handler (VECNUM_MRE,
1655 (interrupt_handler_t *) enetInt,
1657 irq_install_handler (VECNUM_TXDE,
1658 (interrupt_handler_t *) enetInt,
1660 irq_install_handler (VECNUM_RXDE,
1661 (interrupt_handler_t *) enetInt,
1666 #if defined(CONFIG_NET_MULTI)
1672 #if defined(CONFIG_NET_MULTI)
1673 #if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)
1674 miiphy_register (dev->name,
1675 emac4xx_miiphy_read, emac4xx_miiphy_write);
1678 } /* end for each supported device */
1683 #if !defined(CONFIG_NET_MULTI)
1684 void eth_halt (void) {
1686 ppc_4xx_eth_halt(emac0_dev);
1692 int eth_init (bd_t *bis)
1694 ppc_4xx_eth_initialize(bis);
1696 return ppc_4xx_eth_init(emac0_dev, bis);
1698 printf("ERROR: ethaddr not set!\n");
1703 int eth_send(volatile void *packet, int length)
1705 return (ppc_4xx_eth_send(emac0_dev, packet, length));
1710 return (ppc_4xx_eth_rx(emac0_dev));
1713 int emac4xx_miiphy_initialize (bd_t * bis)
1715 #if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)
1716 miiphy_register ("ppc_4xx_eth0",
1717 emac4xx_miiphy_read, emac4xx_miiphy_write);
1722 #endif /* !defined(CONFIG_NET_MULTI) */
1724 #endif /* #if (CONFIG_COMMANDS & CFG_CMD_NET) */