1 /*-----------------------------------------------------------------------------+
3 * This source code has been made available to you by IBM on an AS-IS
4 * basis. Anyone receiving this source is licensed under IBM
5 * copyrights to use it in any way he or she deems fit, including
6 * copying it, modifying it, compiling it, and redistributing it either
7 * with or without modifications. No license under IBM patents or
8 * patent applications is to be implied by the copyright license.
10 * Any user of this software should understand that IBM cannot provide
11 * technical support for this software and will not be responsible for
12 * any consequences resulting from the use of this software.
14 * Any person who transfers this source code or any derivative work
15 * must include the IBM copyright notice, this paragraph, and the
16 * preceding two paragraphs in the transferred software.
18 * COPYRIGHT I B M CORPORATION 1995
19 * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
20 *-----------------------------------------------------------------------------*/
21 /*-----------------------------------------------------------------------------+
23 * File Name: enetemac.c
25 * Function: Device driver for the ethernet EMAC3 macro on the 405GP.
31 * Date Description of Change BY
32 * --------- --------------------- ---
33 * 05-May-99 Created MKW
34 * 27-Jun-99 Clean up JWB
35 * 16-Jul-99 Added MAL error recovery and better IP packet handling MKW
36 * 29-Jul-99 Added Full duplex support MKW
37 * 06-Aug-99 Changed names for Mal CR reg MKW
38 * 23-Aug-99 Turned off SYE when running at 10Mbs MKW
39 * 24-Aug-99 Marked descriptor empty after call_xlc MKW
40 * 07-Sep-99 Set MAL RX buffer size reg to ENET_MAX_MTU_ALIGNED / 16 MCG
41 * to avoid chaining maximum sized packets. Push starting
42 * RX descriptor address up to the next cache line boundary.
43 * 16-Jan-00 Added support for booting with IP of 0x0 MKW
44 * 15-Mar-00 Updated enetInit() to enable broadcast addresses in the
45 * EMAC_RXM register. JWB
46 * 12-Mar-01 anne-sophie.harnois@nextream.fr
47 * - Variables are compatible with those already defined in
49 * - Receive buffer descriptor ring is used to send buffers
51 * - Info print about send/received/handled packet number if
52 * INFO_405_ENET is set
53 * 17-Apr-01 stefan.roese@esd-electronics.com
54 * - MAL reset in "eth_halt" included
55 * - Enet speed and duplex output now in one line
56 * 08-May-01 stefan.roese@esd-electronics.com
57 * - MAL error handling added (eth_init called again)
58 * 13-Nov-01 stefan.roese@esd-electronics.com
59 * - Set IST bit in EMAC_M1 reg upon 100MBit or full duplex
60 * 04-Jan-02 stefan.roese@esd-electronics.com
61 * - Wait for PHY auto negotiation to complete added
62 * 06-Feb-02 stefan.roese@esd-electronics.com
63 * - Bug fixed in waiting for auto negotiation to complete
64 * 26-Feb-02 stefan.roese@esd-electronics.com
65 * - rx and tx buffer descriptors now allocated (no fixed address
67 * 17-Jun-02 stefan.roese@esd-electronics.com
68 * - MAL error debug printf 'M' removed (rx de interrupt may
69 * occur upon many incoming packets with only 4 rx buffers).
70 *-----------------------------------------------------------------------------*
71 * 17-Nov-03 travis.sawyer@sandburst.com
72 * - ported from 405gp_enet.c to utilized upto 4 EMAC ports
73 * in the 440GX. This port should work with the 440GP
75 * 15-Aug-05 sr@denx.de
76 * - merged 405gp_enet.c and 440gx_enet.c to generic 4xx_enet.c
77 now handling all 4xx cpu's.
78 *-----------------------------------------------------------------------------*/
83 #include <asm/processor.h>
85 #include <asm/cache.h>
89 #include <ppc4xx_enet.h>
93 #include <asm/ppc4xx-intvec.h>
96 * Only compile for platform with AMCC EMAC ethernet controller and
97 * network support enabled.
98 * Remark: CONFIG_405 describes Xilinx PPC405 FPGA without EMAC controller!
100 #if defined(CONFIG_CMD_NET) && !defined(CONFIG_405) && !defined(CONFIG_IOP480)
102 #if !(defined(CONFIG_MII) || defined(CONFIG_CMD_MII))
103 #error "CONFIG_MII has to be defined!"
106 #if defined(CONFIG_NETCONSOLE) && !defined(CONFIG_NET_MULTI)
107 #error "CONFIG_NET_MULTI has to be defined for NetConsole"
110 #define EMAC_RESET_TIMEOUT 1000 /* 1000 ms reset timeout */
111 #define PHY_AUTONEGOTIATE_TIMEOUT 5000 /* 5000 ms autonegotiate timeout */
113 /* Ethernet Transmit and Receive Buffers */
115 * In the same way ENET_MAX_MTU and ENET_MAX_MTU_ALIGNED are set from
116 * PKTSIZE and PKTSIZE_ALIGN (include/net.h)
118 #define ENET_MAX_MTU PKTSIZE
119 #define ENET_MAX_MTU_ALIGNED PKTSIZE_ALIGN
121 /*-----------------------------------------------------------------------------+
122 * Defines for MAL/EMAC interrupt conditions as reported in the UIC (Universal
123 * Interrupt Controller).
124 *-----------------------------------------------------------------------------*/
125 #define MAL_UIC_ERR ( UIC_MAL_SERR | UIC_MAL_TXDE | UIC_MAL_RXDE)
126 #define MAL_UIC_DEF (UIC_MAL_RXEOB | MAL_UIC_ERR)
127 #define EMAC_UIC_DEF UIC_ENET
128 #define EMAC_UIC_DEF1 UIC_ENET1
129 #define SEL_UIC_DEF(p) (p ? UIC_ENET1 : UIC_ENET )
133 #define BI_PHYMODE_NONE 0
134 #define BI_PHYMODE_ZMII 1
135 #define BI_PHYMODE_RGMII 2
136 #define BI_PHYMODE_GMII 3
137 #define BI_PHYMODE_RTBI 4
138 #define BI_PHYMODE_TBI 5
139 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
140 defined(CONFIG_405EX)
141 #define BI_PHYMODE_SMII 6
142 #define BI_PHYMODE_MII 7
145 #if defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
146 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
147 defined(CONFIG_405EX)
148 #define SDR0_MFR_ETH_CLK_SEL_V(n) ((0x01<<27) / (n+1))
151 /*-----------------------------------------------------------------------------+
152 * Global variables. TX and RX descriptors and buffers.
153 *-----------------------------------------------------------------------------*/
155 static uint32_t mal_ier;
157 #if !defined(CONFIG_NET_MULTI)
158 struct eth_device *emac0_dev = NULL;
162 * Get count of EMAC devices (doesn't have to be the max. possible number
163 * supported by the cpu)
165 * CONFIG_BOARD_EMAC_COUNT added so now a "dynamic" way to configure the
166 * EMAC count is possible. As it is needed for the Kilauea/Haleakala
167 * 405EX/405EXr eval board, using the same binary.
169 #if defined(CONFIG_BOARD_EMAC_COUNT)
170 #define LAST_EMAC_NUM board_emac_count()
171 #else /* CONFIG_BOARD_EMAC_COUNT */
172 #if defined(CONFIG_HAS_ETH3)
173 #define LAST_EMAC_NUM 4
174 #elif defined(CONFIG_HAS_ETH2)
175 #define LAST_EMAC_NUM 3
176 #elif defined(CONFIG_HAS_ETH1)
177 #define LAST_EMAC_NUM 2
179 #define LAST_EMAC_NUM 1
181 #endif /* CONFIG_BOARD_EMAC_COUNT */
183 /* normal boards start with EMAC0 */
184 #if !defined(CONFIG_EMAC_NR_START)
185 #define CONFIG_EMAC_NR_START 0
188 #if defined(CONFIG_405EX) || defined(CONFIG_440EPX)
189 #define ETH_IRQ_NUM(dev) (VECNUM_ETH0 + ((dev)))
191 #define ETH_IRQ_NUM(dev) (VECNUM_ETH0 + ((dev) * 2))
194 #define MAL_RX_DESC_SIZE 2048
195 #define MAL_TX_DESC_SIZE 2048
196 #define MAL_ALLOC_SIZE (MAL_TX_DESC_SIZE + MAL_RX_DESC_SIZE)
198 /*-----------------------------------------------------------------------------+
199 * Prototypes and externals.
200 *-----------------------------------------------------------------------------*/
201 static void enet_rcv (struct eth_device *dev, unsigned long malisr);
203 int enetInt (struct eth_device *dev);
204 static void mal_err (struct eth_device *dev, unsigned long isr,
205 unsigned long uic, unsigned long maldef,
206 unsigned long mal_errr);
207 static void emac_err (struct eth_device *dev, unsigned long isr);
209 extern int phy_setup_aneg (char *devname, unsigned char addr);
210 extern int emac4xx_miiphy_read (char *devname, unsigned char addr,
211 unsigned char reg, unsigned short *value);
212 extern int emac4xx_miiphy_write (char *devname, unsigned char addr,
213 unsigned char reg, unsigned short value);
215 int board_emac_count(void);
217 /*-----------------------------------------------------------------------------+
219 | Disable MAL channel, and EMACn
220 +-----------------------------------------------------------------------------*/
221 static void ppc_4xx_eth_halt (struct eth_device *dev)
223 EMAC_4XX_HW_PST hw_p = dev->priv;
224 uint32_t failsafe = 10000;
225 #if defined(CONFIG_440SPE) || \
226 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
227 defined(CONFIG_405EX)
231 out_be32((void *)EMAC_IER + hw_p->hw_addr, 0x00000000); /* disable emac interrupts */
233 /* 1st reset MAL channel */
234 /* Note: writing a 0 to a channel has no effect */
235 #if defined(CONFIG_405EP) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
236 mtdcr (maltxcarr, (MAL_CR_MMSR >> (hw_p->devnum * 2)));
238 mtdcr (maltxcarr, (MAL_CR_MMSR >> hw_p->devnum));
240 mtdcr (malrxcarr, (MAL_CR_MMSR >> hw_p->devnum));
243 while (mfdcr (malrxcasr) & (MAL_CR_MMSR >> hw_p->devnum)) {
244 udelay (1000); /* Delay 1 MS so as not to hammer the register */
251 #if defined(CONFIG_440SPE) || \
252 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
253 defined(CONFIG_405EX)
254 /* provide clocks for EMAC internal loopback */
255 mfsdr (sdr_mfr, mfr);
256 mfr |= SDR0_MFR_ETH_CLK_SEL_V(hw_p->devnum);
260 out_be32((void *)EMAC_M0 + hw_p->hw_addr, EMAC_M0_SRST);
262 #if defined(CONFIG_440SPE) || \
263 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
264 defined(CONFIG_405EX)
265 /* remove clocks for EMAC internal loopback */
266 mfsdr (sdr_mfr, mfr);
267 mfr &= ~SDR0_MFR_ETH_CLK_SEL_V(hw_p->devnum);
272 #ifndef CONFIG_NETCONSOLE
273 hw_p->print_speed = 1; /* print speed message again next time */
279 #if defined (CONFIG_440GX)
280 int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis)
283 unsigned long zmiifer;
284 unsigned long rmiifer;
286 mfsdr(sdr_pfc1, pfc1);
287 pfc1 = SDR0_PFC1_EPS_DECODE(pfc1);
294 zmiifer |= ZMII_FER_RMII << ZMII_FER_V(0);
295 zmiifer |= ZMII_FER_RMII << ZMII_FER_V(1);
296 zmiifer |= ZMII_FER_RMII << ZMII_FER_V(2);
297 zmiifer |= ZMII_FER_RMII << ZMII_FER_V(3);
298 bis->bi_phymode[0] = BI_PHYMODE_ZMII;
299 bis->bi_phymode[1] = BI_PHYMODE_ZMII;
300 bis->bi_phymode[2] = BI_PHYMODE_ZMII;
301 bis->bi_phymode[3] = BI_PHYMODE_ZMII;
304 zmiifer |= ZMII_FER_SMII << ZMII_FER_V(0);
305 zmiifer |= ZMII_FER_SMII << ZMII_FER_V(1);
306 zmiifer |= ZMII_FER_SMII << ZMII_FER_V(2);
307 zmiifer |= ZMII_FER_SMII << ZMII_FER_V(3);
308 bis->bi_phymode[0] = BI_PHYMODE_ZMII;
309 bis->bi_phymode[1] = BI_PHYMODE_ZMII;
310 bis->bi_phymode[2] = BI_PHYMODE_ZMII;
311 bis->bi_phymode[3] = BI_PHYMODE_ZMII;
314 zmiifer |= ZMII_FER_RMII << ZMII_FER_V(0);
315 rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(2);
316 bis->bi_phymode[0] = BI_PHYMODE_ZMII;
317 bis->bi_phymode[1] = BI_PHYMODE_NONE;
318 bis->bi_phymode[2] = BI_PHYMODE_RGMII;
319 bis->bi_phymode[3] = BI_PHYMODE_NONE;
322 zmiifer |= ZMII_FER_SMII << ZMII_FER_V(0);
323 zmiifer |= ZMII_FER_SMII << ZMII_FER_V(1);
324 rmiifer |= RGMII_FER_RGMII << RGMII_FER_V (2);
325 rmiifer |= RGMII_FER_RGMII << RGMII_FER_V (3);
326 bis->bi_phymode[0] = BI_PHYMODE_ZMII;
327 bis->bi_phymode[1] = BI_PHYMODE_ZMII;
328 bis->bi_phymode[2] = BI_PHYMODE_RGMII;
329 bis->bi_phymode[3] = BI_PHYMODE_RGMII;
332 zmiifer |= ZMII_FER_SMII << ZMII_FER_V (0);
333 zmiifer |= ZMII_FER_SMII << ZMII_FER_V (1);
334 zmiifer |= ZMII_FER_SMII << ZMII_FER_V (2);
335 rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(3);
336 bis->bi_phymode[0] = BI_PHYMODE_ZMII;
337 bis->bi_phymode[1] = BI_PHYMODE_ZMII;
338 bis->bi_phymode[2] = BI_PHYMODE_ZMII;
339 bis->bi_phymode[3] = BI_PHYMODE_RGMII;
342 zmiifer |= ZMII_FER_SMII << ZMII_FER_V (0);
343 zmiifer |= ZMII_FER_SMII << ZMII_FER_V (1);
344 rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(2);
345 bis->bi_phymode[0] = BI_PHYMODE_ZMII;
346 bis->bi_phymode[1] = BI_PHYMODE_ZMII;
347 bis->bi_phymode[2] = BI_PHYMODE_RGMII;
351 zmiifer = ZMII_FER_MII << ZMII_FER_V(devnum);
353 bis->bi_phymode[0] = BI_PHYMODE_ZMII;
354 bis->bi_phymode[1] = BI_PHYMODE_ZMII;
355 bis->bi_phymode[2] = BI_PHYMODE_ZMII;
356 bis->bi_phymode[3] = BI_PHYMODE_ZMII;
360 /* Ensure we setup mdio for this devnum and ONLY this devnum */
361 zmiifer |= (ZMII_FER_MDI) << ZMII_FER_V(devnum);
363 out_be32((void *)ZMII_FER, zmiifer);
364 out_be32((void *)RGMII_FER, rmiifer);
368 #endif /* CONFIG_440_GX */
370 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
371 int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis)
373 unsigned long zmiifer=0x0;
376 mfsdr(sdr_pfc1, pfc1);
377 pfc1 &= SDR0_PFC1_SELECT_MASK;
380 case SDR0_PFC1_SELECT_CONFIG_2:
382 out_be32((void *)ZMII_FER, 0x00);
383 out_be32((void *)RGMII_FER, 0x00000037);
384 bis->bi_phymode[0] = BI_PHYMODE_GMII;
385 bis->bi_phymode[1] = BI_PHYMODE_NONE;
387 case SDR0_PFC1_SELECT_CONFIG_4:
388 /* 2 x RGMII ports */
389 out_be32((void *)ZMII_FER, 0x00);
390 out_be32((void *)RGMII_FER, 0x00000055);
391 bis->bi_phymode[0] = BI_PHYMODE_RGMII;
392 bis->bi_phymode[1] = BI_PHYMODE_RGMII;
394 case SDR0_PFC1_SELECT_CONFIG_6:
396 out_be32((void *)ZMII_FER,
397 ((ZMII_FER_SMII) << ZMII_FER_V(0)) |
398 ((ZMII_FER_SMII) << ZMII_FER_V(1)));
399 out_be32((void *)RGMII_FER, 0x00000000);
400 bis->bi_phymode[0] = BI_PHYMODE_SMII;
401 bis->bi_phymode[1] = BI_PHYMODE_SMII;
403 case SDR0_PFC1_SELECT_CONFIG_1_2:
404 /* only 1 x MII supported */
405 out_be32((void *)ZMII_FER, (ZMII_FER_MII) << ZMII_FER_V(0));
406 out_be32((void *)RGMII_FER, 0x00000000);
407 bis->bi_phymode[0] = BI_PHYMODE_MII;
408 bis->bi_phymode[1] = BI_PHYMODE_NONE;
414 /* Ensure we setup mdio for this devnum and ONLY this devnum */
415 zmiifer = in_be32((void *)ZMII_FER);
416 zmiifer |= (ZMII_FER_MDI) << ZMII_FER_V(devnum);
417 out_be32((void *)ZMII_FER, zmiifer);
421 #endif /* CONFIG_440EPX */
423 #if defined(CONFIG_405EX)
424 int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis)
429 * Right now only 2*RGMII is supported. Please extend when needed.
434 /* 2 x RGMII ports */
435 out_be32((void *)RGMII_FER, 0x00000055);
436 bis->bi_phymode[0] = BI_PHYMODE_RGMII;
437 bis->bi_phymode[1] = BI_PHYMODE_RGMII;
446 /* Ensure we setup mdio for this devnum and ONLY this devnum */
447 gmiifer = in_be32((void *)RGMII_FER);
448 gmiifer |= (1 << (19-devnum));
449 out_be32((void *)RGMII_FER, gmiifer);
453 #endif /* CONFIG_405EX */
455 static inline void *malloc_aligned(u32 size, u32 align)
457 return (void *)(((u32)malloc(size + align) + align - 1) &
461 static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
464 unsigned long reg = 0;
467 unsigned long duplex;
468 unsigned long failsafe;
470 unsigned short devnum;
471 unsigned short reg_short;
472 #if defined(CONFIG_440GX) || \
473 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
474 defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
475 defined(CONFIG_405EX)
477 #if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \
478 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
479 defined(CONFIG_405EX)
483 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
484 defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
485 defined(CONFIG_405EX)
490 #ifdef CONFIG_4xx_DCACHE
491 static u32 last_used_ea = 0;
494 EMAC_4XX_HW_PST hw_p = dev->priv;
496 /* before doing anything, figure out if we have a MAC address */
498 if (memcmp (dev->enetaddr, "\0\0\0\0\0\0", 6) == 0) {
499 printf("ERROR: ethaddr not set!\n");
503 #if defined(CONFIG_440GX) || \
504 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
505 defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
506 defined(CONFIG_405EX)
507 /* Need to get the OPB frequency so we can access the PHY */
508 get_sys_info (&sysinfo);
512 mtmsr (msr & ~(MSR_EE)); /* disable interrupts */
514 devnum = hw_p->devnum;
519 * hw_p->stats.pkts_handled <= hw_p->stats.pkts_rx <= hw_p->stats.pkts_handled+PKTBUFSRX
520 * In the most cases hw_p->stats.pkts_handled = hw_p->stats.pkts_rx, but it
521 * is possible that new packets (without relationship with
522 * current transfer) have got the time to arrived before
523 * netloop calls eth_halt
525 printf ("About preceeding transfer (eth%d):\n"
526 "- Sent packet number %d\n"
527 "- Received packet number %d\n"
528 "- Handled packet number %d\n",
531 hw_p->stats.pkts_rx, hw_p->stats.pkts_handled);
533 hw_p->stats.pkts_tx = 0;
534 hw_p->stats.pkts_rx = 0;
535 hw_p->stats.pkts_handled = 0;
536 hw_p->print_speed = 1; /* print speed message again next time */
539 hw_p->tx_err_index = 0; /* Transmit Error Index for tx_err_log */
540 hw_p->rx_err_index = 0; /* Receive Error Index for rx_err_log */
542 hw_p->rx_slot = 0; /* MAL Receive Slot */
543 hw_p->rx_i_index = 0; /* Receive Interrupt Queue Index */
544 hw_p->rx_u_index = 0; /* Receive User Queue Index */
546 hw_p->tx_slot = 0; /* MAL Transmit Slot */
547 hw_p->tx_i_index = 0; /* Transmit Interrupt Queue Index */
548 hw_p->tx_u_index = 0; /* Transmit User Queue Index */
550 #if defined(CONFIG_440) && !defined(CONFIG_440SP) && !defined(CONFIG_440SPE)
552 /* NOTE: 440GX spec states that mode is mutually exclusive */
553 /* NOTE: Therefore, disable all other EMACS, since we handle */
554 /* NOTE: only one emac at a time */
556 out_be32((void *)ZMII_FER, 0);
559 #if defined(CONFIG_440EP) || defined(CONFIG_440GR)
560 out_be32((void *)ZMII_FER, (ZMII_FER_RMII | ZMII_FER_MDI) << ZMII_FER_V (devnum));
561 #elif defined(CONFIG_440GX) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
562 ethgroup = ppc_4xx_eth_setup_bridge(devnum, bis);
563 #elif defined(CONFIG_440GP)
565 out_be32((void *)ZMII_FER, ZMII_RMII | ZMII_MDI0);
567 if ((devnum == 0) || (devnum == 1)) {
568 out_be32((void *)ZMII_FER, (ZMII_FER_SMII | ZMII_FER_MDI) << ZMII_FER_V (devnum));
569 } else { /* ((devnum == 2) || (devnum == 3)) */
570 out_be32((void *)ZMII_FER, ZMII_FER_MDI << ZMII_FER_V (devnum));
571 out_be32((void *)RGMII_FER, ((RGMII_FER_RGMII << RGMII_FER_V (2)) |
572 (RGMII_FER_RGMII << RGMII_FER_V (3))));
576 out_be32((void *)ZMII_SSR, ZMII_SSR_SP << ZMII_SSR_V(devnum));
577 #endif /* defined(CONFIG_440) && !defined(CONFIG_440SP) */
578 #if defined(CONFIG_405EX)
579 ethgroup = ppc_4xx_eth_setup_bridge(devnum, bis);
582 __asm__ volatile ("eieio");
584 /* reset emac so we have access to the phy */
585 #if defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
586 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
587 defined(CONFIG_405EX)
588 /* provide clocks for EMAC internal loopback */
589 mfsdr (sdr_mfr, mfr);
590 mfr |= SDR0_MFR_ETH_CLK_SEL_V(devnum);
594 out_be32((void *)EMAC_M0 + hw_p->hw_addr, EMAC_M0_SRST);
597 while ((in_be32((void *)EMAC_M0 + hw_p->hw_addr) & (EMAC_M0_SRST)) && failsafe) {
602 printf("\nProblem resetting EMAC!\n");
604 #if defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
605 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
606 defined(CONFIG_405EX)
607 /* remove clocks for EMAC internal loopback */
608 mfsdr (sdr_mfr, mfr);
609 mfr &= ~SDR0_MFR_ETH_CLK_SEL_V(devnum);
613 #if defined(CONFIG_440GX) || \
614 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
615 defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
616 defined(CONFIG_405EX)
617 /* Whack the M1 register */
619 mode_reg &= ~0x00000038;
620 if (sysinfo.freqOPB <= 50000000);
621 else if (sysinfo.freqOPB <= 66666667)
622 mode_reg |= EMAC_M1_OBCI_66;
623 else if (sysinfo.freqOPB <= 83333333)
624 mode_reg |= EMAC_M1_OBCI_83;
625 else if (sysinfo.freqOPB <= 100000000)
626 mode_reg |= EMAC_M1_OBCI_100;
628 mode_reg |= EMAC_M1_OBCI_GT100;
630 out_be32((void *)EMAC_M1 + hw_p->hw_addr, mode_reg);
631 #endif /* defined(CONFIG_440GX) || defined(CONFIG_440SP) */
633 /* wait for PHY to complete auto negotiation */
635 #ifndef CONFIG_CS8952_PHY
638 reg = CONFIG_PHY_ADDR;
640 #if defined (CONFIG_PHY1_ADDR)
642 reg = CONFIG_PHY1_ADDR;
645 #if defined (CONFIG_440GX)
647 reg = CONFIG_PHY2_ADDR;
650 reg = CONFIG_PHY3_ADDR;
654 reg = CONFIG_PHY_ADDR;
658 bis->bi_phynum[devnum] = reg;
660 #if defined(CONFIG_PHY_RESET)
662 * Reset the phy, only if its the first time through
663 * otherwise, just check the speeds & feeds
665 if (hw_p->first_init == 0) {
666 #if defined(CONFIG_M88E1111_PHY)
667 miiphy_write (dev->name, reg, 0x14, 0x0ce3);
668 miiphy_write (dev->name, reg, 0x18, 0x4101);
669 miiphy_write (dev->name, reg, 0x09, 0x0e00);
670 miiphy_write (dev->name, reg, 0x04, 0x01e1);
672 miiphy_reset (dev->name, reg);
674 #if defined(CONFIG_440GX) || \
675 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
676 defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
677 defined(CONFIG_405EX)
679 #if defined(CONFIG_CIS8201_PHY)
681 * Cicada 8201 PHY needs to have an extended register whacked
684 if (((devnum == 2) || (devnum == 3)) && (4 == ethgroup)) {
685 #if defined(CONFIG_CIS8201_SHORT_ETCH)
686 miiphy_write (dev->name, reg, 23, 0x1300);
688 miiphy_write (dev->name, reg, 23, 0x1000);
691 * Vitesse VSC8201/Cicada CIS8201 errata:
692 * Interoperability problem with Intel 82547EI phys
693 * This work around (provided by Vitesse) changes
694 * the default timer convergence from 8ms to 12ms
696 miiphy_write (dev->name, reg, 0x1f, 0x2a30);
697 miiphy_write (dev->name, reg, 0x08, 0x0200);
698 miiphy_write (dev->name, reg, 0x1f, 0x52b5);
699 miiphy_write (dev->name, reg, 0x02, 0x0004);
700 miiphy_write (dev->name, reg, 0x01, 0x0671);
701 miiphy_write (dev->name, reg, 0x00, 0x8fae);
702 miiphy_write (dev->name, reg, 0x1f, 0x2a30);
703 miiphy_write (dev->name, reg, 0x08, 0x0000);
704 miiphy_write (dev->name, reg, 0x1f, 0x0000);
705 /* end Vitesse/Cicada errata */
709 #if defined(CONFIG_ET1011C_PHY)
711 * Agere ET1011c PHY needs to have an extended register whacked
714 if (((devnum == 2) || (devnum ==3)) && (4 == ethgroup)) {
715 miiphy_read (dev->name, reg, 0x16, ®_short);
717 reg_short |= 0x6; /* RGMII DLL Delay*/
718 miiphy_write (dev->name, reg, 0x16, reg_short);
720 miiphy_read (dev->name, reg, 0x17, ®_short);
721 reg_short &= ~(0x40);
722 miiphy_write (dev->name, reg, 0x17, reg_short);
724 miiphy_write(dev->name, reg, 0x1c, 0x74f0);
729 /* Start/Restart autonegotiation */
730 phy_setup_aneg (dev->name, reg);
733 #endif /* defined(CONFIG_PHY_RESET) */
735 miiphy_read (dev->name, reg, PHY_BMSR, ®_short);
738 * Wait if PHY is capable of autonegotiation and autonegotiation is not complete
740 if ((reg_short & PHY_BMSR_AUTN_ABLE)
741 && !(reg_short & PHY_BMSR_AUTN_COMP)) {
742 puts ("Waiting for PHY auto negotiation to complete");
744 while (!(reg_short & PHY_BMSR_AUTN_COMP)) {
748 if (i > PHY_AUTONEGOTIATE_TIMEOUT) {
749 puts (" TIMEOUT !\n");
753 if ((i++ % 1000) == 0) {
756 udelay (1000); /* 1 ms */
757 miiphy_read (dev->name, reg, PHY_BMSR, ®_short);
761 udelay (500000); /* another 500 ms (results in faster booting) */
763 #endif /* #ifndef CONFIG_CS8952_PHY */
765 speed = miiphy_speed (dev->name, reg);
766 duplex = miiphy_duplex (dev->name, reg);
768 if (hw_p->print_speed) {
769 hw_p->print_speed = 0;
770 printf ("ENET Speed is %d Mbps - %s duplex connection (EMAC%d)\n",
771 (int) speed, (duplex == HALF) ? "HALF" : "FULL",
775 #if defined(CONFIG_440) && !defined(CONFIG_440SP) && !defined(CONFIG_440SPE) && \
776 !defined(CONFIG_440EPX) && !defined(CONFIG_440GRX)
777 #if defined(CONFIG_440EP) || defined(CONFIG_440GR)
780 reg = (reg & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_RMII_100M;
782 reg = (reg & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_RMII_10M;
787 /* Set ZMII/RGMII speed according to the phy link speed */
788 reg = in_be32((void *)ZMII_SSR);
789 if ( (speed == 100) || (speed == 1000) )
790 out_be32((void *)ZMII_SSR, reg | (ZMII_SSR_SP << ZMII_SSR_V (devnum)));
792 out_be32((void *)ZMII_SSR, reg & (~(ZMII_SSR_SP << ZMII_SSR_V (devnum))));
794 if ((devnum == 2) || (devnum == 3)) {
796 reg = (RGMII_SSR_SP_1000MBPS << RGMII_SSR_V (devnum));
797 else if (speed == 100)
798 reg = (RGMII_SSR_SP_100MBPS << RGMII_SSR_V (devnum));
799 else if (speed == 10)
800 reg = (RGMII_SSR_SP_10MBPS << RGMII_SSR_V (devnum));
802 printf("Error in RGMII Speed\n");
805 out_be32((void *)RGMII_SSR, reg);
807 #endif /* defined(CONFIG_440) && !defined(CONFIG_440SP) */
809 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
810 defined(CONFIG_405EX)
812 reg = (RGMII_SSR_SP_1000MBPS << RGMII_SSR_V (devnum));
813 else if (speed == 100)
814 reg = (RGMII_SSR_SP_100MBPS << RGMII_SSR_V (devnum));
815 else if (speed == 10)
816 reg = (RGMII_SSR_SP_10MBPS << RGMII_SSR_V (devnum));
818 printf("Error in RGMII Speed\n");
821 out_be32((void *)RGMII_SSR, reg);
824 /* set the Mal configuration reg */
825 #if defined(CONFIG_440GX) || \
826 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
827 defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
828 defined(CONFIG_405EX)
829 mtdcr (malmcr, MAL_CR_PLBB | MAL_CR_OPBBL | MAL_CR_LEA |
830 MAL_CR_PLBLT_DEFAULT | MAL_CR_EOPIE | 0x00330000);
832 mtdcr (malmcr, MAL_CR_PLBB | MAL_CR_OPBBL | MAL_CR_LEA | MAL_CR_PLBLT_DEFAULT);
833 /* Errata 1.12: MAL_1 -- Disable MAL bursting */
834 if (get_pvr() == PVR_440GP_RB) {
835 mtdcr (malmcr, mfdcr(malmcr) & ~MAL_CR_PLBB);
840 * Malloc MAL buffer desciptors, make sure they are
841 * aligned on cache line boundary size
842 * (401/403/IOP480 = 16, 405 = 32)
843 * and doesn't cross cache block boundaries.
845 if (hw_p->first_init == 0) {
846 debug("*** Allocating descriptor memory ***\n");
848 bd_cached = (u32)malloc_aligned(MAL_ALLOC_SIZE, 4096);
850 printf("%s: Error allocating MAL descriptor buffers!\n");
854 #ifdef CONFIG_4xx_DCACHE
855 flush_dcache_range(bd_cached, bd_cached + MAL_ALLOC_SIZE);
857 bd_uncached = bis->bi_memsize;
859 bd_uncached = last_used_ea + MAL_ALLOC_SIZE;
861 last_used_ea = bd_uncached;
862 program_tlb(bd_cached, bd_uncached, MAL_ALLOC_SIZE,
865 bd_uncached = bd_cached;
867 hw_p->tx_phys = bd_cached;
868 hw_p->rx_phys = bd_cached + MAL_TX_DESC_SIZE;
869 hw_p->tx = (mal_desc_t *)(bd_uncached);
870 hw_p->rx = (mal_desc_t *)(bd_uncached + MAL_TX_DESC_SIZE);
871 debug("hw_p->tx=%08x, hw_p->rx=%08x\n", hw_p->tx, hw_p->rx);
874 for (i = 0; i < NUM_TX_BUFF; i++) {
875 hw_p->tx[i].ctrl = 0;
876 hw_p->tx[i].data_len = 0;
877 if (hw_p->first_init == 0)
878 hw_p->txbuf_ptr = malloc_aligned(MAL_ALLOC_SIZE,
880 hw_p->tx[i].data_ptr = hw_p->txbuf_ptr;
881 if ((NUM_TX_BUFF - 1) == i)
882 hw_p->tx[i].ctrl |= MAL_TX_CTRL_WRAP;
883 hw_p->tx_run[i] = -1;
884 debug("TX_BUFF %d @ 0x%08lx\n", i, (u32)hw_p->tx[i].data_ptr);
887 for (i = 0; i < NUM_RX_BUFF; i++) {
888 hw_p->rx[i].ctrl = 0;
889 hw_p->rx[i].data_len = 0;
890 hw_p->rx[i].data_ptr = (char *)NetRxPackets[i];
891 if ((NUM_RX_BUFF - 1) == i)
892 hw_p->rx[i].ctrl |= MAL_RX_CTRL_WRAP;
893 hw_p->rx[i].ctrl |= MAL_RX_CTRL_EMPTY | MAL_RX_CTRL_INTR;
894 hw_p->rx_ready[i] = -1;
895 debug("RX_BUFF %d @ 0x%08lx\n", i, (u32)hw_p->rx[i].data_ptr);
900 reg |= dev->enetaddr[0]; /* set high address */
902 reg |= dev->enetaddr[1];
904 out_be32((void *)EMAC_IAH + hw_p->hw_addr, reg);
907 reg |= dev->enetaddr[2]; /* set low address */
909 reg |= dev->enetaddr[3];
911 reg |= dev->enetaddr[4];
913 reg |= dev->enetaddr[5];
915 out_be32((void *)EMAC_IAL + hw_p->hw_addr, reg);
919 /* setup MAL tx & rx channel pointers */
920 #if defined (CONFIG_405EP) || defined (CONFIG_440EP) || defined (CONFIG_440GR)
921 mtdcr (maltxctp2r, hw_p->tx_phys);
923 mtdcr (maltxctp1r, hw_p->tx_phys);
925 #if defined(CONFIG_440)
926 mtdcr (maltxbattr, 0x0);
927 mtdcr (malrxbattr, 0x0);
929 mtdcr (malrxctp1r, hw_p->rx_phys);
930 /* set RX buffer size */
931 mtdcr (malrcbs1, ENET_MAX_MTU_ALIGNED / 16);
933 #if defined (CONFIG_440GX)
935 /* setup MAL tx & rx channel pointers */
936 mtdcr (maltxbattr, 0x0);
937 mtdcr (malrxbattr, 0x0);
938 mtdcr (maltxctp2r, hw_p->tx_phys);
939 mtdcr (malrxctp2r, hw_p->rx_phys);
940 /* set RX buffer size */
941 mtdcr (malrcbs2, ENET_MAX_MTU_ALIGNED / 16);
944 /* setup MAL tx & rx channel pointers */
945 mtdcr (maltxbattr, 0x0);
946 mtdcr (maltxctp3r, hw_p->tx_phys);
947 mtdcr (malrxbattr, 0x0);
948 mtdcr (malrxctp3r, hw_p->rx_phys);
949 /* set RX buffer size */
950 mtdcr (malrcbs3, ENET_MAX_MTU_ALIGNED / 16);
952 #endif /* CONFIG_440GX */
955 /* setup MAL tx & rx channel pointers */
956 #if defined(CONFIG_440)
957 mtdcr (maltxbattr, 0x0);
958 mtdcr (malrxbattr, 0x0);
960 mtdcr (maltxctp0r, hw_p->tx_phys);
961 mtdcr (malrxctp0r, hw_p->rx_phys);
962 /* set RX buffer size */
963 mtdcr (malrcbs0, ENET_MAX_MTU_ALIGNED / 16);
967 /* Enable MAL transmit and receive channels */
968 #if defined(CONFIG_405EP) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
969 mtdcr (maltxcasr, (MAL_TXRX_CASR >> (hw_p->devnum*2)));
971 mtdcr (maltxcasr, (MAL_TXRX_CASR >> hw_p->devnum));
973 mtdcr (malrxcasr, (MAL_TXRX_CASR >> hw_p->devnum));
975 /* set transmit enable & receive enable */
976 out_be32((void *)EMAC_M0 + hw_p->hw_addr, EMAC_M0_TXE | EMAC_M0_RXE);
978 mode_reg = in_be32((void *)EMAC_M1 + hw_p->hw_addr);
980 /* set rx-/tx-fifo size */
981 mode_reg = (mode_reg & ~EMAC_MR1_FIFO_MASK) | EMAC_MR1_FIFO_SIZE;
984 if (speed == _1000BASET) {
985 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
986 defined(CONFIG_440SP) || defined(CONFIG_440SPE)
989 mfsdr (sdr_pfc1, pfc1);
990 pfc1 |= SDR0_PFC1_EM_1000;
991 mtsdr (sdr_pfc1, pfc1);
993 mode_reg = mode_reg | EMAC_M1_MF_1000MBPS | EMAC_M1_IST;
994 } else if (speed == _100BASET)
995 mode_reg = mode_reg | EMAC_M1_MF_100MBPS | EMAC_M1_IST;
997 mode_reg = mode_reg & ~0x00C00000; /* 10 MBPS */
999 mode_reg = mode_reg | 0x80000000 | EMAC_M1_IST;
1001 out_be32((void *)EMAC_M1 + hw_p->hw_addr, mode_reg);
1003 /* Enable broadcast and indvidual address */
1004 /* TBS: enabling runts as some misbehaved nics will send runts */
1005 out_be32((void *)EMAC_RXM + hw_p->hw_addr, EMAC_RMR_BAE | EMAC_RMR_IAE);
1007 /* we probably need to set the tx mode1 reg? maybe at tx time */
1009 /* set transmit request threshold register */
1010 out_be32((void *)EMAC_TRTR + hw_p->hw_addr, 0x18000000); /* 256 byte threshold */
1012 /* set receive low/high water mark register */
1013 #if defined(CONFIG_440)
1014 /* 440s has a 64 byte burst length */
1015 out_be32((void *)EMAC_RX_HI_LO_WMARK + hw_p->hw_addr, 0x80009000);
1017 /* 405s have a 16 byte burst length */
1018 out_be32((void *)EMAC_RX_HI_LO_WMARK + hw_p->hw_addr, 0x0f002000);
1019 #endif /* defined(CONFIG_440) */
1020 out_be32((void *)EMAC_TXM1 + hw_p->hw_addr, 0xf8640000);
1022 /* Set fifo limit entry in tx mode 0 */
1023 out_be32((void *)EMAC_TXM0 + hw_p->hw_addr, 0x00000003);
1025 out_be32((void *)EMAC_I_FRAME_GAP_REG + hw_p->hw_addr, 0x00000008);
1028 hw_p->emac_ier = EMAC_ISR_PTLE | EMAC_ISR_BFCS | EMAC_ISR_ORE | EMAC_ISR_IRE;
1029 if (speed == _100BASET)
1030 hw_p->emac_ier = hw_p->emac_ier | EMAC_ISR_SYE;
1032 out_be32((void *)EMAC_ISR + hw_p->hw_addr, 0xffffffff); /* clear pending interrupts */
1033 out_be32((void *)EMAC_IER + hw_p->hw_addr, hw_p->emac_ier);
1035 if (hw_p->first_init == 0) {
1037 * Connect interrupt service routines
1039 irq_install_handler(ETH_IRQ_NUM(hw_p->devnum),
1040 (interrupt_handler_t *) enetInt, dev);
1043 mtmsr (msr); /* enable interrupts again */
1046 hw_p->first_init = 1;
1052 static int ppc_4xx_eth_send (struct eth_device *dev, volatile void *ptr,
1055 struct enet_frame *ef_ptr;
1056 ulong time_start, time_now;
1057 unsigned long temp_txm0;
1058 EMAC_4XX_HW_PST hw_p = dev->priv;
1060 ef_ptr = (struct enet_frame *) ptr;
1062 /*-----------------------------------------------------------------------+
1063 * Copy in our address into the frame.
1064 *-----------------------------------------------------------------------*/
1065 (void) memcpy (ef_ptr->source_addr, dev->enetaddr, ENET_ADDR_LENGTH);
1067 /*-----------------------------------------------------------------------+
1068 * If frame is too long or too short, modify length.
1069 *-----------------------------------------------------------------------*/
1070 /* TBS: where does the fragment go???? */
1071 if (len > ENET_MAX_MTU)
1074 /* memcpy ((void *) &tx_buff[tx_slot], (const void *) ptr, len); */
1075 memcpy ((void *) hw_p->txbuf_ptr, (const void *) ptr, len);
1076 flush_dcache_range((u32)hw_p->txbuf_ptr, (u32)hw_p->txbuf_ptr + len);
1078 /*-----------------------------------------------------------------------+
1079 * set TX Buffer busy, and send it
1080 *-----------------------------------------------------------------------*/
1081 hw_p->tx[hw_p->tx_slot].ctrl = (MAL_TX_CTRL_LAST |
1082 EMAC_TX_CTRL_GFCS | EMAC_TX_CTRL_GP) &
1083 ~(EMAC_TX_CTRL_ISA | EMAC_TX_CTRL_RSA);
1084 if ((NUM_TX_BUFF - 1) == hw_p->tx_slot)
1085 hw_p->tx[hw_p->tx_slot].ctrl |= MAL_TX_CTRL_WRAP;
1087 hw_p->tx[hw_p->tx_slot].data_len = (short) len;
1088 hw_p->tx[hw_p->tx_slot].ctrl |= MAL_TX_CTRL_READY;
1090 __asm__ volatile ("eieio");
1092 out_be32((void *)EMAC_TXM0 + hw_p->hw_addr,
1093 in_be32((void *)EMAC_TXM0 + hw_p->hw_addr) | EMAC_TXM0_GNP0);
1094 #ifdef INFO_4XX_ENET
1095 hw_p->stats.pkts_tx++;
1098 /*-----------------------------------------------------------------------+
1099 * poll unitl the packet is sent and then make sure it is OK
1100 *-----------------------------------------------------------------------*/
1101 time_start = get_timer (0);
1103 temp_txm0 = in_be32((void *)EMAC_TXM0 + hw_p->hw_addr);
1104 /* loop until either TINT turns on or 3 seconds elapse */
1105 if ((temp_txm0 & EMAC_TXM0_GNP0) != 0) {
1106 /* transmit is done, so now check for errors
1107 * If there is an error, an interrupt should
1108 * happen when we return
1110 time_now = get_timer (0);
1111 if ((time_now - time_start) > 3000) {
1121 #if defined (CONFIG_440) || defined(CONFIG_405EX)
1123 #if defined(CONFIG_440SP) || defined(CONFIG_440SPE)
1125 * Hack: On 440SP all enet irq sources are located on UIC1
1126 * Needs some cleanup. --sr
1128 #define UIC0MSR uic1msr
1129 #define UIC0SR uic1sr
1131 #define UIC0MSR uic0msr
1132 #define UIC0SR uic0sr
1135 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
1136 defined(CONFIG_405EX)
1137 #define UICMSR_ETHX uic0msr
1138 #define UICSR_ETHX uic0sr
1140 #define UICMSR_ETHX uic1msr
1141 #define UICSR_ETHX uic1sr
1144 int enetInt (struct eth_device *dev)
1147 int rc = -1; /* default to not us */
1148 unsigned long mal_isr;
1149 unsigned long emac_isr = 0;
1150 unsigned long mal_rx_eob;
1151 unsigned long my_uic0msr, my_uic1msr;
1152 unsigned long my_uicmsr_ethx;
1154 #if defined(CONFIG_440GX)
1155 unsigned long my_uic2msr;
1157 EMAC_4XX_HW_PST hw_p;
1160 * Because the mal is generic, we need to get the current
1163 #if defined(CONFIG_NET_MULTI)
1164 dev = eth_get_dev();
1171 /* enter loop that stays in interrupt code until nothing to service */
1175 my_uic0msr = mfdcr (UIC0MSR);
1176 my_uic1msr = mfdcr (uic1msr);
1177 #if defined(CONFIG_440GX)
1178 my_uic2msr = mfdcr (uic2msr);
1180 my_uicmsr_ethx = mfdcr (UICMSR_ETHX);
1182 if (!(my_uic0msr & (UIC_MRE | UIC_MTE))
1183 && !(my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))
1184 && !(my_uicmsr_ethx & (UIC_ETH0 | UIC_ETH1))) {
1188 #if defined (CONFIG_440GX)
1189 if (!(my_uic0msr & (UIC_MRE | UIC_MTE))
1190 && !(my_uic2msr & (UIC_ETH2 | UIC_ETH3))) {
1195 /* get and clear controller status interrupts */
1196 /* look at Mal and EMAC interrupts */
1197 if ((my_uic0msr & (UIC_MRE | UIC_MTE))
1198 || (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) {
1199 /* we have a MAL interrupt */
1200 mal_isr = mfdcr (malesr);
1201 /* look for mal error */
1202 if (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE)) {
1203 mal_err (dev, mal_isr, my_uic1msr, MAL_UIC_DEF, MAL_UIC_ERR);
1209 /* port by port dispatch of emac interrupts */
1210 if (hw_p->devnum == 0) {
1211 if (UIC_ETH0 & my_uicmsr_ethx) { /* look for EMAC errors */
1212 emac_isr = in_be32((void *)EMAC_ISR + hw_p->hw_addr);
1213 if ((hw_p->emac_ier & emac_isr) != 0) {
1214 emac_err (dev, emac_isr);
1219 if ((hw_p->emac_ier & emac_isr)
1220 || (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) {
1221 mtdcr (UIC0SR, UIC_MRE | UIC_MTE); /* Clear */
1222 mtdcr (uic1sr, UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */
1223 mtdcr (UICSR_ETHX, UIC_ETH0); /* Clear */
1224 return (rc); /* we had errors so get out */
1228 #if !defined(CONFIG_440SP)
1229 if (hw_p->devnum == 1) {
1230 if (UIC_ETH1 & my_uicmsr_ethx) { /* look for EMAC errors */
1231 emac_isr = in_be32((void *)EMAC_ISR + hw_p->hw_addr);
1232 if ((hw_p->emac_ier & emac_isr) != 0) {
1233 emac_err (dev, emac_isr);
1238 if ((hw_p->emac_ier & emac_isr)
1239 || (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) {
1240 mtdcr (UIC0SR, UIC_MRE | UIC_MTE); /* Clear */
1241 mtdcr (uic1sr, UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */
1242 mtdcr (UICSR_ETHX, UIC_ETH1); /* Clear */
1243 return (rc); /* we had errors so get out */
1246 #if defined (CONFIG_440GX)
1247 if (hw_p->devnum == 2) {
1248 if (UIC_ETH2 & my_uic2msr) { /* look for EMAC errors */
1249 emac_isr = in_be32((void *)EMAC_ISR + hw_p->hw_addr);
1250 if ((hw_p->emac_ier & emac_isr) != 0) {
1251 emac_err (dev, emac_isr);
1256 if ((hw_p->emac_ier & emac_isr)
1257 || (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) {
1258 mtdcr (UIC0SR, UIC_MRE | UIC_MTE); /* Clear */
1259 mtdcr (uic1sr, UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */
1260 mtdcr (uic2sr, UIC_ETH2);
1261 return (rc); /* we had errors so get out */
1265 if (hw_p->devnum == 3) {
1266 if (UIC_ETH3 & my_uic2msr) { /* look for EMAC errors */
1267 emac_isr = in_be32((void *)EMAC_ISR + hw_p->hw_addr);
1268 if ((hw_p->emac_ier & emac_isr) != 0) {
1269 emac_err (dev, emac_isr);
1274 if ((hw_p->emac_ier & emac_isr)
1275 || (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) {
1276 mtdcr (UIC0SR, UIC_MRE | UIC_MTE); /* Clear */
1277 mtdcr (uic1sr, UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */
1278 mtdcr (uic2sr, UIC_ETH3);
1279 return (rc); /* we had errors so get out */
1282 #endif /* CONFIG_440GX */
1283 #endif /* !CONFIG_440SP */
1285 /* handle MAX TX EOB interrupt from a tx */
1286 if (my_uic0msr & UIC_MTE) {
1287 mal_rx_eob = mfdcr (maltxeobisr);
1288 mtdcr (maltxeobisr, mal_rx_eob);
1289 mtdcr (UIC0SR, UIC_MTE);
1291 /* handle MAL RX EOB interupt from a receive */
1292 /* check for EOB on valid channels */
1293 if (my_uic0msr & UIC_MRE) {
1294 mal_rx_eob = mfdcr (malrxeobisr);
1295 if ((mal_rx_eob & (0x80000000 >> hw_p->devnum)) != 0) { /* call emac routine for channel x */
1297 mtdcr(malrxeobisr, mal_rx_eob); */
1298 enet_rcv (dev, emac_isr);
1299 /* indicate that we serviced an interrupt */
1305 mtdcr (UIC0SR, UIC_MRE); /* Clear */
1306 mtdcr (uic1sr, UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */
1307 switch (hw_p->devnum) {
1309 mtdcr (UICSR_ETHX, UIC_ETH0);
1312 mtdcr (UICSR_ETHX, UIC_ETH1);
1314 #if defined (CONFIG_440GX)
1316 mtdcr (uic2sr, UIC_ETH2);
1319 mtdcr (uic2sr, UIC_ETH3);
1321 #endif /* CONFIG_440GX */
1330 #else /* CONFIG_440 */
1332 int enetInt (struct eth_device *dev)
1335 int rc = -1; /* default to not us */
1336 unsigned long mal_isr;
1337 unsigned long emac_isr = 0;
1338 unsigned long mal_rx_eob;
1339 unsigned long my_uicmsr;
1341 EMAC_4XX_HW_PST hw_p;
1344 * Because the mal is generic, we need to get the current
1347 #if defined(CONFIG_NET_MULTI)
1348 dev = eth_get_dev();
1355 /* enter loop that stays in interrupt code until nothing to service */
1359 my_uicmsr = mfdcr (uicmsr);
1361 if ((my_uicmsr & (MAL_UIC_DEF | EMAC_UIC_DEF)) == 0) { /* not for us */
1364 /* get and clear controller status interrupts */
1365 /* look at Mal and EMAC interrupts */
1366 if ((MAL_UIC_DEF & my_uicmsr) != 0) { /* we have a MAL interrupt */
1367 mal_isr = mfdcr (malesr);
1368 /* look for mal error */
1369 if ((my_uicmsr & MAL_UIC_ERR) != 0) {
1370 mal_err (dev, mal_isr, my_uicmsr, MAL_UIC_DEF, MAL_UIC_ERR);
1376 /* port by port dispatch of emac interrupts */
1378 if ((SEL_UIC_DEF(hw_p->devnum) & my_uicmsr) != 0) { /* look for EMAC errors */
1379 emac_isr = in_be32((void *)EMAC_ISR + hw_p->hw_addr);
1380 if ((hw_p->emac_ier & emac_isr) != 0) {
1381 emac_err (dev, emac_isr);
1386 if (((hw_p->emac_ier & emac_isr) != 0) || ((MAL_UIC_ERR & my_uicmsr) != 0)) {
1387 mtdcr (uicsr, MAL_UIC_DEF | SEL_UIC_DEF(hw_p->devnum)); /* Clear */
1388 return (rc); /* we had errors so get out */
1391 /* handle MAX TX EOB interrupt from a tx */
1392 if (my_uicmsr & UIC_MAL_TXEOB) {
1393 mal_rx_eob = mfdcr (maltxeobisr);
1394 mtdcr (maltxeobisr, mal_rx_eob);
1395 mtdcr (uicsr, UIC_MAL_TXEOB);
1397 /* handle MAL RX EOB interupt from a receive */
1398 /* check for EOB on valid channels */
1399 if (my_uicmsr & UIC_MAL_RXEOB)
1401 mal_rx_eob = mfdcr (malrxeobisr);
1402 if ((mal_rx_eob & (0x80000000 >> hw_p->devnum)) != 0) { /* call emac routine for channel x */
1404 mtdcr(malrxeobisr, mal_rx_eob); */
1405 enet_rcv (dev, emac_isr);
1406 /* indicate that we serviced an interrupt */
1411 mtdcr (uicsr, MAL_UIC_DEF|EMAC_UIC_DEF|EMAC_UIC_DEF1); /* Clear */
1412 #if defined(CONFIG_405EZ)
1413 mtsdr (sdricintstat, SDR_ICRX_STAT | SDR_ICTX0_STAT | SDR_ICTX1_STAT);
1414 #endif /* defined(CONFIG_405EZ) */
1421 #endif /* CONFIG_440 */
1423 /*-----------------------------------------------------------------------------+
1425 *-----------------------------------------------------------------------------*/
1426 static void mal_err (struct eth_device *dev, unsigned long isr,
1427 unsigned long uic, unsigned long maldef,
1428 unsigned long mal_errr)
1430 EMAC_4XX_HW_PST hw_p = dev->priv;
1432 mtdcr (malesr, isr); /* clear interrupt */
1434 /* clear DE interrupt */
1435 mtdcr (maltxdeir, 0xC0000000);
1436 mtdcr (malrxdeir, 0x80000000);
1438 #ifdef INFO_4XX_ENET
1439 printf ("\nMAL error occured.... ISR = %lx UIC = = %lx MAL_DEF = %lx MAL_ERR= %lx \n", isr, uic, maldef, mal_errr);
1442 eth_init (hw_p->bis); /* start again... */
1445 /*-----------------------------------------------------------------------------+
1446 * EMAC Error Routine
1447 *-----------------------------------------------------------------------------*/
1448 static void emac_err (struct eth_device *dev, unsigned long isr)
1450 EMAC_4XX_HW_PST hw_p = dev->priv;
1452 printf ("EMAC%d error occured.... ISR = %lx\n", hw_p->devnum, isr);
1453 out_be32((void *)EMAC_ISR + hw_p->hw_addr, isr);
1456 /*-----------------------------------------------------------------------------+
1457 * enet_rcv() handles the ethernet receive data
1458 *-----------------------------------------------------------------------------*/
1459 static void enet_rcv (struct eth_device *dev, unsigned long malisr)
1461 struct enet_frame *ef_ptr;
1462 unsigned long data_len;
1463 unsigned long rx_eob_isr;
1464 EMAC_4XX_HW_PST hw_p = dev->priv;
1470 rx_eob_isr = mfdcr (malrxeobisr);
1471 if ((0x80000000 >> hw_p->devnum) & rx_eob_isr) {
1473 mtdcr (malrxeobisr, rx_eob_isr);
1476 while (1) { /* do all */
1479 if ((MAL_RX_CTRL_EMPTY & hw_p->rx[i].ctrl)
1480 || (loop_count >= NUM_RX_BUFF))
1485 data_len = (unsigned long) hw_p->rx[i].data_len; /* Get len */
1487 if (data_len > ENET_MAX_MTU) /* Check len */
1490 if (EMAC_RX_ERRORS & hw_p->rx[i].ctrl) { /* Check Errors */
1492 hw_p->stats.rx_err_log[hw_p->
1495 hw_p->rx_err_index++;
1496 if (hw_p->rx_err_index ==
1498 hw_p->rx_err_index =
1501 } /* data_len < max mtu */
1503 if (!data_len) { /* no data */
1504 hw_p->rx[i].ctrl |= MAL_RX_CTRL_EMPTY; /* Free Recv Buffer */
1506 hw_p->stats.data_len_err++; /* Error at Rx */
1511 /* Check if user has already eaten buffer */
1512 /* if not => ERROR */
1513 else if (hw_p->rx_ready[hw_p->rx_i_index] != -1) {
1514 if (hw_p->is_receiving)
1515 printf ("ERROR : Receive buffers are full!\n");
1518 hw_p->stats.rx_frames++;
1519 hw_p->stats.rx += data_len;
1520 ef_ptr = (struct enet_frame *) hw_p->rx[i].
1522 #ifdef INFO_4XX_ENET
1523 hw_p->stats.pkts_rx++;
1528 hw_p->rx_ready[hw_p->rx_i_index] = i;
1530 if (NUM_RX_BUFF == hw_p->rx_i_index)
1531 hw_p->rx_i_index = 0;
1534 if (NUM_RX_BUFF == hw_p->rx_slot)
1538 * free receive buffer only when
1539 * buffer has been handled (eth_rx)
1540 rx[i].ctrl |= MAL_RX_CTRL_EMPTY;
1544 } /* if EMACK_RXCHL */
1548 static int ppc_4xx_eth_rx (struct eth_device *dev)
1553 EMAC_4XX_HW_PST hw_p = dev->priv;
1555 hw_p->is_receiving = 1; /* tell driver */
1559 * use ring buffer and
1560 * get index from rx buffer desciptor queue
1562 user_index = hw_p->rx_ready[hw_p->rx_u_index];
1563 if (user_index == -1) {
1565 break; /* nothing received - leave for() loop */
1569 mtmsr (msr & ~(MSR_EE));
1571 length = hw_p->rx[user_index].data_len;
1573 /* Pass the packet up to the protocol layers. */
1574 /* NetReceive(NetRxPackets[rxIdx], length - 4); */
1575 /* NetReceive(NetRxPackets[i], length); */
1576 invalidate_dcache_range((u32)hw_p->rx[user_index].data_ptr,
1577 (u32)hw_p->rx[user_index].data_ptr +
1579 NetReceive (NetRxPackets[user_index], length - 4);
1580 /* Free Recv Buffer */
1581 hw_p->rx[user_index].ctrl |= MAL_RX_CTRL_EMPTY;
1582 /* Free rx buffer descriptor queue */
1583 hw_p->rx_ready[hw_p->rx_u_index] = -1;
1585 if (NUM_RX_BUFF == hw_p->rx_u_index)
1586 hw_p->rx_u_index = 0;
1588 #ifdef INFO_4XX_ENET
1589 hw_p->stats.pkts_handled++;
1592 mtmsr (msr); /* Enable IRQ's */
1595 hw_p->is_receiving = 0; /* tell driver */
1600 int ppc_4xx_eth_initialize (bd_t * bis)
1602 static int virgin = 0;
1603 struct eth_device *dev;
1605 EMAC_4XX_HW_PST hw = NULL;
1606 u8 ethaddr[4 + CONFIG_EMAC_NR_START][6];
1609 #if defined(CONFIG_440GX)
1612 mfsdr (sdr_pfc1, pfc1);
1613 pfc1 &= ~(0x01e00000);
1615 mtsdr (sdr_pfc1, pfc1);
1618 /* first clear all mac-addresses */
1619 for (eth_num = 0; eth_num < LAST_EMAC_NUM; eth_num++)
1620 memcpy(ethaddr[eth_num], "\0\0\0\0\0\0", 6);
1622 for (eth_num = 0; eth_num < LAST_EMAC_NUM; eth_num++) {
1624 default: /* fall through */
1626 memcpy(ethaddr[eth_num + CONFIG_EMAC_NR_START],
1627 bis->bi_enetaddr, 6);
1628 hw_addr[eth_num] = 0x0;
1630 #ifdef CONFIG_HAS_ETH1
1632 memcpy(ethaddr[eth_num + CONFIG_EMAC_NR_START],
1633 bis->bi_enet1addr, 6);
1634 hw_addr[eth_num] = 0x100;
1637 #ifdef CONFIG_HAS_ETH2
1639 memcpy(ethaddr[eth_num + CONFIG_EMAC_NR_START],
1640 bis->bi_enet2addr, 6);
1641 hw_addr[eth_num] = 0x400;
1644 #ifdef CONFIG_HAS_ETH3
1646 memcpy(ethaddr[eth_num + CONFIG_EMAC_NR_START],
1647 bis->bi_enet3addr, 6);
1648 hw_addr[eth_num] = 0x600;
1654 /* set phy num and mode */
1655 bis->bi_phynum[0] = CONFIG_PHY_ADDR;
1656 bis->bi_phymode[0] = 0;
1658 #if defined(CONFIG_PHY1_ADDR)
1659 bis->bi_phynum[1] = CONFIG_PHY1_ADDR;
1660 bis->bi_phymode[1] = 0;
1662 #if defined(CONFIG_440GX)
1663 bis->bi_phynum[2] = CONFIG_PHY2_ADDR;
1664 bis->bi_phynum[3] = CONFIG_PHY3_ADDR;
1665 bis->bi_phymode[2] = 2;
1666 bis->bi_phymode[3] = 2;
1669 #if defined(CONFIG_440GX) || \
1670 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
1671 defined(CONFIG_405EX)
1672 ppc_4xx_eth_setup_bridge(0, bis);
1675 for (eth_num = 0; eth_num < LAST_EMAC_NUM; eth_num++) {
1677 * See if we can actually bring up the interface,
1678 * otherwise, skip it
1680 if (memcmp (ethaddr[eth_num], "\0\0\0\0\0\0", 6) == 0) {
1681 bis->bi_phymode[eth_num] = BI_PHYMODE_NONE;
1685 /* Allocate device structure */
1686 dev = (struct eth_device *) malloc (sizeof (*dev));
1688 printf ("ppc_4xx_eth_initialize: "
1689 "Cannot allocate eth_device %d\n", eth_num);
1692 memset(dev, 0, sizeof(*dev));
1694 /* Allocate our private use data */
1695 hw = (EMAC_4XX_HW_PST) malloc (sizeof (*hw));
1697 printf ("ppc_4xx_eth_initialize: "
1698 "Cannot allocate private hw data for eth_device %d",
1703 memset(hw, 0, sizeof(*hw));
1705 hw->hw_addr = hw_addr[eth_num];
1706 memcpy (dev->enetaddr, ethaddr[eth_num], 6);
1707 hw->devnum = eth_num;
1708 hw->print_speed = 1;
1710 sprintf (dev->name, "ppc_4xx_eth%d", eth_num - CONFIG_EMAC_NR_START);
1711 dev->priv = (void *) hw;
1712 dev->init = ppc_4xx_eth_init;
1713 dev->halt = ppc_4xx_eth_halt;
1714 dev->send = ppc_4xx_eth_send;
1715 dev->recv = ppc_4xx_eth_rx;
1718 /* set the MAL IER ??? names may change with new spec ??? */
1719 #if defined(CONFIG_440SPE) || \
1720 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
1721 defined(CONFIG_405EX)
1723 MAL_IER_PT | MAL_IER_PRE | MAL_IER_PWE |
1724 MAL_IER_DE | MAL_IER_OTE | MAL_IER_OE | MAL_IER_PE ;
1727 MAL_IER_DE | MAL_IER_NE | MAL_IER_TE |
1728 MAL_IER_OPBE | MAL_IER_PLBE;
1730 mtdcr (malesr, 0xffffffff); /* clear pending interrupts */
1731 mtdcr (maltxdeir, 0xffffffff); /* clear pending interrupts */
1732 mtdcr (malrxdeir, 0xffffffff); /* clear pending interrupts */
1733 mtdcr (malier, mal_ier);
1735 /* install MAL interrupt handler */
1736 irq_install_handler (VECNUM_MS,
1737 (interrupt_handler_t *) enetInt,
1739 irq_install_handler (VECNUM_MTE,
1740 (interrupt_handler_t *) enetInt,
1742 irq_install_handler (VECNUM_MRE,
1743 (interrupt_handler_t *) enetInt,
1745 irq_install_handler (VECNUM_TXDE,
1746 (interrupt_handler_t *) enetInt,
1748 irq_install_handler (VECNUM_RXDE,
1749 (interrupt_handler_t *) enetInt,
1754 #if defined(CONFIG_NET_MULTI)
1760 #if defined(CONFIG_NET_MULTI)
1761 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
1762 miiphy_register (dev->name,
1763 emac4xx_miiphy_read, emac4xx_miiphy_write);
1766 } /* end for each supported device */
1771 #if !defined(CONFIG_NET_MULTI)
1772 void eth_halt (void) {
1774 ppc_4xx_eth_halt(emac0_dev);
1780 int eth_init (bd_t *bis)
1782 ppc_4xx_eth_initialize(bis);
1784 return ppc_4xx_eth_init(emac0_dev, bis);
1786 printf("ERROR: ethaddr not set!\n");
1791 int eth_send(volatile void *packet, int length)
1793 return (ppc_4xx_eth_send(emac0_dev, packet, length));
1798 return (ppc_4xx_eth_rx(emac0_dev));
1801 int emac4xx_miiphy_initialize (bd_t * bis)
1803 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
1804 miiphy_register ("ppc_4xx_eth0",
1805 emac4xx_miiphy_read, emac4xx_miiphy_write);
1810 #endif /* !defined(CONFIG_NET_MULTI) */