2 * cpu/ppc4xx/44x_spd_ddr2.c
3 * This SPD SDRAM detection code supports AMCC PPC44x cpu's with a
4 * DDR2 controller (non Denali Core). Those currently are:
7 * 440/460: 440SP/440SPe/460EX/460GT
9 * Copyright (c) 2008 Nuovation System Designs, LLC
10 * Grant Erickson <gerickson@nuovations.com>
12 * (C) Copyright 2007-2008
13 * Stefan Roese, DENX Software Engineering, sr@denx.de.
15 * COPYRIGHT AMCC CORPORATION 2004
17 * See file CREDITS for list of people who contributed to this
20 * This program is free software; you can redistribute it and/or
21 * modify it under the terms of the GNU General Public License as
22 * published by the Free Software Foundation; either version 2 of
23 * the License, or (at your option) any later version.
25 * This program is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU General Public License for more details.
30 * You should have received a copy of the GNU General Public License
31 * along with this program; if not, write to the Free Software
32 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
37 /* define DEBUG for debugging output (obviously ;-)) */
47 #include <asm/processor.h>
49 #include <asm/cache.h>
53 #if defined(CONFIG_SDRAM_PPC4xx_IBM_DDR2)
55 #define PPC4xx_IBM_DDR2_DUMP_REGISTER(mnemonic) \
58 mfsdram(SDRAM_##mnemonic, data); \
59 printf("%20s[%02x] = 0x%08X\n", \
60 "SDRAM_" #mnemonic, SDRAM_##mnemonic, data); \
63 static inline void ppc4xx_ibm_ddr2_register_dump(void);
65 #if defined(CONFIG_SPD_EEPROM)
67 /*-----------------------------------------------------------------------------+
69 *-----------------------------------------------------------------------------*/
84 #define MAX_SPD_BYTES 256 /* Max number of bytes on the DIMM's SPD EEPROM */
86 #define ONE_BILLION 1000000000
88 #define MULDIV64(m1, m2, d) (u32)(((u64)(m1) * (u64)(m2)) / (u64)(d))
90 #define CMD_NOP (7 << 19)
91 #define CMD_PRECHARGE (2 << 19)
92 #define CMD_REFRESH (1 << 19)
93 #define CMD_EMR (0 << 19)
94 #define CMD_READ (5 << 19)
95 #define CMD_WRITE (4 << 19)
97 #define SELECT_MR (0 << 16)
98 #define SELECT_EMR (1 << 16)
99 #define SELECT_EMR2 (2 << 16)
100 #define SELECT_EMR3 (3 << 16)
103 #define DLL_RESET 0x00000100
105 #define WRITE_RECOV_2 (1 << 9)
106 #define WRITE_RECOV_3 (2 << 9)
107 #define WRITE_RECOV_4 (3 << 9)
108 #define WRITE_RECOV_5 (4 << 9)
109 #define WRITE_RECOV_6 (5 << 9)
111 #define BURST_LEN_4 0x00000002
114 #define ODT_0_OHM 0x00000000
115 #define ODT_50_OHM 0x00000044
116 #define ODT_75_OHM 0x00000004
117 #define ODT_150_OHM 0x00000040
119 #define ODS_FULL 0x00000000
120 #define ODS_REDUCED 0x00000002
122 /* defines for ODT (On Die Termination) of the 440SP(e) DDR2 controller */
123 #define ODT_EB0R (0x80000000 >> 8)
124 #define ODT_EB0W (0x80000000 >> 7)
125 #define CALC_ODT_R(n) (ODT_EB0R << (n << 1))
126 #define CALC_ODT_W(n) (ODT_EB0W << (n << 1))
127 #define CALC_ODT_RW(n) (CALC_ODT_R(n) | CALC_ODT_W(n))
129 /* Defines for the Read Cycle Delay test */
130 #define NUMMEMTESTS 8
131 #define NUMMEMWORDS 8
132 #define NUMLOOPS 64 /* memory test loops */
135 * This DDR2 setup code can dynamically setup the TLB entries for the DDR2 memory
136 * region. Right now the cache should still be disabled in U-Boot because of the
137 * EMAC driver, that need it's buffer descriptor to be located in non cached
140 * If at some time this restriction doesn't apply anymore, just define
141 * CONFIG_4xx_DCACHE in the board config file and this code should setup
142 * everything correctly.
144 #ifdef CONFIG_4xx_DCACHE
145 #define MY_TLB_WORD2_I_ENABLE 0 /* enable caching on SDRAM */
147 #define MY_TLB_WORD2_I_ENABLE TLB_WORD2_I_ENABLE /* disable caching on SDRAM */
151 * Newer PPC's like 440SPe, 460EX/GT can be equipped with more than 2GB of SDRAM.
152 * To support such configurations, we "only" map the first 2GB via the TLB's. We
153 * need some free virtual address space for the remaining peripherals like, SoC
154 * devices, FLASH etc.
156 * Note that ECC is currently not supported on configurations with more than 2GB
157 * SDRAM. This is because we only map the first 2GB on such systems, and therefore
158 * the ECC parity byte of the remaining area can't be written.
160 #ifndef CONFIG_MAX_MEM_MAPPED
161 #define CONFIG_MAX_MEM_MAPPED ((phys_size_t)2 << 30)
165 * Board-specific Platform code can reimplement spd_ddr_init_hang () if needed
167 void __spd_ddr_init_hang (void)
171 void spd_ddr_init_hang (void) __attribute__((weak, alias("__spd_ddr_init_hang")));
174 * To provide an interface for board specific config values in this common
175 * DDR setup code, we implement he "weak" default functions here. They return
176 * the default value back to the caller.
178 * Please see include/configs/yucca.h for an example fora board specific
181 u32 __ddr_wrdtr(u32 default_val)
185 u32 ddr_wrdtr(u32) __attribute__((weak, alias("__ddr_wrdtr")));
187 u32 __ddr_clktr(u32 default_val)
191 u32 ddr_clktr(u32) __attribute__((weak, alias("__ddr_clktr")));
194 /* Private Structure Definitions */
196 /* enum only to ease code for cas latency setting */
197 typedef enum ddr_cas_id {
205 /*-----------------------------------------------------------------------------+
207 *-----------------------------------------------------------------------------*/
208 static phys_size_t sdram_memsize(void);
209 static void get_spd_info(unsigned long *dimm_populated,
210 unsigned char *iic0_dimm_addr,
211 unsigned long num_dimm_banks);
212 static void check_mem_type(unsigned long *dimm_populated,
213 unsigned char *iic0_dimm_addr,
214 unsigned long num_dimm_banks);
215 static void check_frequency(unsigned long *dimm_populated,
216 unsigned char *iic0_dimm_addr,
217 unsigned long num_dimm_banks);
218 static void check_rank_number(unsigned long *dimm_populated,
219 unsigned char *iic0_dimm_addr,
220 unsigned long num_dimm_banks);
221 static void check_voltage_type(unsigned long *dimm_populated,
222 unsigned char *iic0_dimm_addr,
223 unsigned long num_dimm_banks);
224 static void program_memory_queue(unsigned long *dimm_populated,
225 unsigned char *iic0_dimm_addr,
226 unsigned long num_dimm_banks);
227 static void program_codt(unsigned long *dimm_populated,
228 unsigned char *iic0_dimm_addr,
229 unsigned long num_dimm_banks);
230 static void program_mode(unsigned long *dimm_populated,
231 unsigned char *iic0_dimm_addr,
232 unsigned long num_dimm_banks,
233 ddr_cas_id_t *selected_cas,
234 int *write_recovery);
235 static void program_tr(unsigned long *dimm_populated,
236 unsigned char *iic0_dimm_addr,
237 unsigned long num_dimm_banks);
238 static void program_rtr(unsigned long *dimm_populated,
239 unsigned char *iic0_dimm_addr,
240 unsigned long num_dimm_banks);
241 static void program_bxcf(unsigned long *dimm_populated,
242 unsigned char *iic0_dimm_addr,
243 unsigned long num_dimm_banks);
244 static void program_copt1(unsigned long *dimm_populated,
245 unsigned char *iic0_dimm_addr,
246 unsigned long num_dimm_banks);
247 static void program_initplr(unsigned long *dimm_populated,
248 unsigned char *iic0_dimm_addr,
249 unsigned long num_dimm_banks,
250 ddr_cas_id_t selected_cas,
252 static unsigned long is_ecc_enabled(void);
253 #ifdef CONFIG_DDR_ECC
254 static void program_ecc(unsigned long *dimm_populated,
255 unsigned char *iic0_dimm_addr,
256 unsigned long num_dimm_banks,
257 unsigned long tlb_word2_i_value);
258 static void program_ecc_addr(unsigned long start_address,
259 unsigned long num_bytes,
260 unsigned long tlb_word2_i_value);
262 static void program_DQS_calibration(unsigned long *dimm_populated,
263 unsigned char *iic0_dimm_addr,
264 unsigned long num_dimm_banks);
265 #ifdef HARD_CODED_DQS /* calibration test with hardvalues */
266 static void test(void);
268 static void DQS_calibration_process(void);
270 int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
271 void dcbz_area(u32 start_address, u32 num_bytes);
273 static u32 mfdcr_any(u32 dcr)
278 case SDRAM_R0BAS + 0:
279 val = mfdcr(SDRAM_R0BAS + 0);
281 case SDRAM_R0BAS + 1:
282 val = mfdcr(SDRAM_R0BAS + 1);
284 case SDRAM_R0BAS + 2:
285 val = mfdcr(SDRAM_R0BAS + 2);
287 case SDRAM_R0BAS + 3:
288 val = mfdcr(SDRAM_R0BAS + 3);
291 printf("DCR %d not defined in case statement!!!\n", dcr);
292 val = 0; /* just to satisfy the compiler */
298 static void mtdcr_any(u32 dcr, u32 val)
301 case SDRAM_R0BAS + 0:
302 mtdcr(SDRAM_R0BAS + 0, val);
304 case SDRAM_R0BAS + 1:
305 mtdcr(SDRAM_R0BAS + 1, val);
307 case SDRAM_R0BAS + 2:
308 mtdcr(SDRAM_R0BAS + 2, val);
310 case SDRAM_R0BAS + 3:
311 mtdcr(SDRAM_R0BAS + 3, val);
314 printf("DCR %d not defined in case statement!!!\n", dcr);
318 static unsigned char spd_read(uchar chip, uint addr)
320 unsigned char data[2];
322 if (i2c_probe(chip) == 0)
323 if (i2c_read(chip, addr, 1, data, 1) == 0)
329 /*-----------------------------------------------------------------------------+
331 *-----------------------------------------------------------------------------*/
332 static phys_size_t sdram_memsize(void)
334 phys_size_t mem_size;
335 unsigned long mcopt2;
336 unsigned long mcstat;
343 mfsdram(SDRAM_MCOPT2, mcopt2);
344 mfsdram(SDRAM_MCSTAT, mcstat);
346 /* DDR controller must be enabled and not in self-refresh. */
347 /* Otherwise memsize is zero. */
348 if (((mcopt2 & SDRAM_MCOPT2_DCEN_MASK) == SDRAM_MCOPT2_DCEN_ENABLE)
349 && ((mcopt2 & SDRAM_MCOPT2_SREN_MASK) == SDRAM_MCOPT2_SREN_EXIT)
350 && ((mcstat & (SDRAM_MCSTAT_MIC_MASK | SDRAM_MCSTAT_SRMS_MASK))
351 == (SDRAM_MCSTAT_MIC_COMP | SDRAM_MCSTAT_SRMS_NOT_SF))) {
352 for (i = 0; i < MAXBXCF; i++) {
353 mfsdram(SDRAM_MB0CF + (i << 2), mb0cf);
355 if ((mb0cf & SDRAM_BXCF_M_BE_MASK) == SDRAM_BXCF_M_BE_ENABLE) {
356 sdsz = mfdcr_any(SDRAM_R0BAS + i) & SDRAM_RXBAS_SDSZ_MASK;
359 case SDRAM_RXBAS_SDSZ_8:
362 case SDRAM_RXBAS_SDSZ_16:
365 case SDRAM_RXBAS_SDSZ_32:
368 case SDRAM_RXBAS_SDSZ_64:
371 case SDRAM_RXBAS_SDSZ_128:
374 case SDRAM_RXBAS_SDSZ_256:
377 case SDRAM_RXBAS_SDSZ_512:
380 case SDRAM_RXBAS_SDSZ_1024:
383 case SDRAM_RXBAS_SDSZ_2048:
386 case SDRAM_RXBAS_SDSZ_4096:
390 printf("WARNING: Unsupported bank size (SDSZ=0x%lx)!\n"
399 return mem_size << 20;
402 /*-----------------------------------------------------------------------------+
403 * initdram. Initializes the 440SP Memory Queue and DDR SDRAM controller.
404 * Note: This routine runs from flash with a stack set up in the chip's
405 * sram space. It is important that the routine does not require .sbss, .bss or
406 * .data sections. It also cannot call routines that require these sections.
407 *-----------------------------------------------------------------------------*/
408 /*-----------------------------------------------------------------------------
410 * Description: Configures SDRAM memory banks for DDR operation.
411 * Auto Memory Configuration option reads the DDR SDRAM EEPROMs
412 * via the IIC bus and then configures the DDR SDRAM memory
413 * banks appropriately. If Auto Memory Configuration is
414 * not used, it is assumed that no DIMM is plugged
415 *-----------------------------------------------------------------------------*/
416 phys_size_t initdram(int board_type)
418 unsigned char iic0_dimm_addr[] = SPD_EEPROM_ADDRESS;
419 unsigned char spd0[MAX_SPD_BYTES];
420 unsigned char spd1[MAX_SPD_BYTES];
421 unsigned char *dimm_spd[MAXDIMMS];
422 unsigned long dimm_populated[MAXDIMMS];
423 unsigned long num_dimm_banks; /* on board dimm banks */
425 ddr_cas_id_t selected_cas = DDR_CAS_5; /* preset to silence compiler */
427 phys_size_t dram_size = 0;
429 num_dimm_banks = sizeof(iic0_dimm_addr);
431 /*------------------------------------------------------------------
432 * Set up an array of SPD matrixes.
433 *-----------------------------------------------------------------*/
437 /*------------------------------------------------------------------
438 * Reset the DDR-SDRAM controller.
439 *-----------------------------------------------------------------*/
440 mtsdr(SDR0_SRST, (0x80000000 >> 10));
441 mtsdr(SDR0_SRST, 0x00000000);
444 * Make sure I2C controller is initialized
448 /* switch to correct I2C bus */
449 I2C_SET_BUS(CFG_SPD_BUS_NUM);
450 i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE);
452 /*------------------------------------------------------------------
453 * Clear out the serial presence detect buffers.
454 * Perform IIC reads from the dimm. Fill in the spds.
455 * Check to see if the dimm slots are populated
456 *-----------------------------------------------------------------*/
457 get_spd_info(dimm_populated, iic0_dimm_addr, num_dimm_banks);
459 /*------------------------------------------------------------------
460 * Check the memory type for the dimms plugged.
461 *-----------------------------------------------------------------*/
462 check_mem_type(dimm_populated, iic0_dimm_addr, num_dimm_banks);
464 /*------------------------------------------------------------------
465 * Check the frequency supported for the dimms plugged.
466 *-----------------------------------------------------------------*/
467 check_frequency(dimm_populated, iic0_dimm_addr, num_dimm_banks);
469 /*------------------------------------------------------------------
470 * Check the total rank number.
471 *-----------------------------------------------------------------*/
472 check_rank_number(dimm_populated, iic0_dimm_addr, num_dimm_banks);
474 /*------------------------------------------------------------------
475 * Check the voltage type for the dimms plugged.
476 *-----------------------------------------------------------------*/
477 check_voltage_type(dimm_populated, iic0_dimm_addr, num_dimm_banks);
479 /*------------------------------------------------------------------
480 * Program SDRAM controller options 2 register
481 * Except Enabling of the memory controller.
482 *-----------------------------------------------------------------*/
483 mfsdram(SDRAM_MCOPT2, val);
484 mtsdram(SDRAM_MCOPT2,
486 ~(SDRAM_MCOPT2_SREN_MASK | SDRAM_MCOPT2_PMEN_MASK |
487 SDRAM_MCOPT2_IPTR_MASK | SDRAM_MCOPT2_XSRP_MASK |
488 SDRAM_MCOPT2_ISIE_MASK))
489 | (SDRAM_MCOPT2_SREN_ENTER | SDRAM_MCOPT2_PMEN_DISABLE |
490 SDRAM_MCOPT2_IPTR_IDLE | SDRAM_MCOPT2_XSRP_ALLOW |
491 SDRAM_MCOPT2_ISIE_ENABLE));
493 /*------------------------------------------------------------------
494 * Program SDRAM controller options 1 register
495 * Note: Does not enable the memory controller.
496 *-----------------------------------------------------------------*/
497 program_copt1(dimm_populated, iic0_dimm_addr, num_dimm_banks);
499 /*------------------------------------------------------------------
500 * Set the SDRAM Controller On Die Termination Register
501 *-----------------------------------------------------------------*/
502 program_codt(dimm_populated, iic0_dimm_addr, num_dimm_banks);
504 /*------------------------------------------------------------------
505 * Program SDRAM refresh register.
506 *-----------------------------------------------------------------*/
507 program_rtr(dimm_populated, iic0_dimm_addr, num_dimm_banks);
509 /*------------------------------------------------------------------
510 * Program SDRAM mode register.
511 *-----------------------------------------------------------------*/
512 program_mode(dimm_populated, iic0_dimm_addr, num_dimm_banks,
513 &selected_cas, &write_recovery);
515 /*------------------------------------------------------------------
516 * Set the SDRAM Write Data/DM/DQS Clock Timing Reg
517 *-----------------------------------------------------------------*/
518 mfsdram(SDRAM_WRDTR, val);
519 mtsdram(SDRAM_WRDTR, (val & ~(SDRAM_WRDTR_LLWP_MASK | SDRAM_WRDTR_WTR_MASK)) |
520 ddr_wrdtr(SDRAM_WRDTR_LLWP_1_CYC | SDRAM_WRDTR_WTR_90_DEG_ADV));
522 /*------------------------------------------------------------------
523 * Set the SDRAM Clock Timing Register
524 *-----------------------------------------------------------------*/
525 mfsdram(SDRAM_CLKTR, val);
526 mtsdram(SDRAM_CLKTR, (val & ~SDRAM_CLKTR_CLKP_MASK) |
527 ddr_clktr(SDRAM_CLKTR_CLKP_0_DEG));
529 /*------------------------------------------------------------------
530 * Program the BxCF registers.
531 *-----------------------------------------------------------------*/
532 program_bxcf(dimm_populated, iic0_dimm_addr, num_dimm_banks);
534 /*------------------------------------------------------------------
535 * Program SDRAM timing registers.
536 *-----------------------------------------------------------------*/
537 program_tr(dimm_populated, iic0_dimm_addr, num_dimm_banks);
539 /*------------------------------------------------------------------
540 * Set the Extended Mode register
541 *-----------------------------------------------------------------*/
542 mfsdram(SDRAM_MEMODE, val);
543 mtsdram(SDRAM_MEMODE,
544 (val & ~(SDRAM_MEMODE_DIC_MASK | SDRAM_MEMODE_DLL_MASK |
545 SDRAM_MEMODE_RTT_MASK | SDRAM_MEMODE_DQS_MASK)) |
546 (SDRAM_MEMODE_DIC_NORMAL | SDRAM_MEMODE_DLL_ENABLE
547 | SDRAM_MEMODE_RTT_150OHM | SDRAM_MEMODE_DQS_ENABLE));
549 /*------------------------------------------------------------------
550 * Program Initialization preload registers.
551 *-----------------------------------------------------------------*/
552 program_initplr(dimm_populated, iic0_dimm_addr, num_dimm_banks,
553 selected_cas, write_recovery);
555 /*------------------------------------------------------------------
556 * Delay to ensure 200usec have elapsed since reset.
557 *-----------------------------------------------------------------*/
560 /*------------------------------------------------------------------
561 * Set the memory queue core base addr.
562 *-----------------------------------------------------------------*/
563 program_memory_queue(dimm_populated, iic0_dimm_addr, num_dimm_banks);
565 /*------------------------------------------------------------------
566 * Program SDRAM controller options 2 register
567 * Enable the memory controller.
568 *-----------------------------------------------------------------*/
569 mfsdram(SDRAM_MCOPT2, val);
570 mtsdram(SDRAM_MCOPT2,
571 (val & ~(SDRAM_MCOPT2_SREN_MASK | SDRAM_MCOPT2_DCEN_MASK |
572 SDRAM_MCOPT2_IPTR_MASK | SDRAM_MCOPT2_ISIE_MASK)) |
573 (SDRAM_MCOPT2_DCEN_ENABLE | SDRAM_MCOPT2_IPTR_EXECUTE));
575 /*------------------------------------------------------------------
576 * Wait for SDRAM_CFG0_DC_EN to complete.
577 *-----------------------------------------------------------------*/
579 mfsdram(SDRAM_MCSTAT, val);
580 } while ((val & SDRAM_MCSTAT_MIC_MASK) == SDRAM_MCSTAT_MIC_NOTCOMP);
582 /* get installed memory size */
583 dram_size = sdram_memsize();
588 if (dram_size > CONFIG_MAX_MEM_MAPPED)
589 dram_size = CONFIG_MAX_MEM_MAPPED;
591 /* and program tlb entries for this size (dynamic) */
594 * Program TLB entries with caches enabled, for best performace
595 * while auto-calibrating and ECC generation
597 program_tlb(0, 0, dram_size, 0);
599 /*------------------------------------------------------------------
601 *-----------------------------------------------------------------*/
602 program_DQS_calibration(dimm_populated, iic0_dimm_addr, num_dimm_banks);
604 #ifdef CONFIG_DDR_ECC
605 /*------------------------------------------------------------------
606 * If ecc is enabled, initialize the parity bits.
607 *-----------------------------------------------------------------*/
608 program_ecc(dimm_populated, iic0_dimm_addr, num_dimm_banks, 0);
612 * Now after initialization (auto-calibration and ECC generation)
613 * remove the TLB entries with caches enabled and program again with
614 * desired cache functionality
616 remove_tlb(0, dram_size);
617 program_tlb(0, 0, dram_size, MY_TLB_WORD2_I_ENABLE);
619 ppc4xx_ibm_ddr2_register_dump();
622 * Clear potential errors resulting from auto-calibration.
623 * If not done, then we could get an interrupt later on when
624 * exceptions are enabled.
626 set_mcsr(get_mcsr());
628 return sdram_memsize();
631 static void get_spd_info(unsigned long *dimm_populated,
632 unsigned char *iic0_dimm_addr,
633 unsigned long num_dimm_banks)
635 unsigned long dimm_num;
636 unsigned long dimm_found;
637 unsigned char num_of_bytes;
638 unsigned char total_size;
641 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
645 num_of_bytes = spd_read(iic0_dimm_addr[dimm_num], 0);
646 debug("\nspd_read(0x%x) returned %d\n",
647 iic0_dimm_addr[dimm_num], num_of_bytes);
648 total_size = spd_read(iic0_dimm_addr[dimm_num], 1);
649 debug("spd_read(0x%x) returned %d\n",
650 iic0_dimm_addr[dimm_num], total_size);
652 if ((num_of_bytes != 0) && (total_size != 0)) {
653 dimm_populated[dimm_num] = TRUE;
655 debug("DIMM slot %lu: populated\n", dimm_num);
657 dimm_populated[dimm_num] = FALSE;
658 debug("DIMM slot %lu: Not populated\n", dimm_num);
662 if (dimm_found == FALSE) {
663 printf("ERROR - No memory installed. Install a DDR-SDRAM DIMM.\n\n");
664 spd_ddr_init_hang ();
668 void board_add_ram_info(int use_default)
670 PPC4xx_SYS_INFO board_cfg;
673 if (is_ecc_enabled())
678 get_sys_info(&board_cfg);
680 mfsdr(SDR0_DDR0, val);
681 val = MULDIV64((board_cfg.freqPLB), SDR0_DDR0_DDRM_DECODE(val), 1);
682 printf(" enabled, %d MHz", (val * 2) / 1000000);
684 mfsdram(SDRAM_MMODE, val);
685 val = (val & SDRAM_MMODE_DCL_MASK) >> 4;
686 printf(", CL%d)", val);
689 /*------------------------------------------------------------------
690 * For the memory DIMMs installed, this routine verifies that they
691 * really are DDR specific DIMMs.
692 *-----------------------------------------------------------------*/
693 static void check_mem_type(unsigned long *dimm_populated,
694 unsigned char *iic0_dimm_addr,
695 unsigned long num_dimm_banks)
697 unsigned long dimm_num;
698 unsigned long dimm_type;
700 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
701 if (dimm_populated[dimm_num] == TRUE) {
702 dimm_type = spd_read(iic0_dimm_addr[dimm_num], 2);
705 printf("ERROR: Standard Fast Page Mode DRAM DIMM detected in "
706 "slot %d.\n", (unsigned int)dimm_num);
707 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
708 printf("Replace the DIMM module with a supported DIMM.\n\n");
709 spd_ddr_init_hang ();
712 printf("ERROR: EDO DIMM detected in slot %d.\n",
713 (unsigned int)dimm_num);
714 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
715 printf("Replace the DIMM module with a supported DIMM.\n\n");
716 spd_ddr_init_hang ();
719 printf("ERROR: Pipelined Nibble DIMM detected in slot %d.\n",
720 (unsigned int)dimm_num);
721 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
722 printf("Replace the DIMM module with a supported DIMM.\n\n");
723 spd_ddr_init_hang ();
726 printf("ERROR: SDRAM DIMM detected in slot %d.\n",
727 (unsigned int)dimm_num);
728 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
729 printf("Replace the DIMM module with a supported DIMM.\n\n");
730 spd_ddr_init_hang ();
733 printf("ERROR: Multiplexed ROM DIMM detected in slot %d.\n",
734 (unsigned int)dimm_num);
735 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
736 printf("Replace the DIMM module with a supported DIMM.\n\n");
737 spd_ddr_init_hang ();
740 printf("ERROR: SGRAM DIMM detected in slot %d.\n",
741 (unsigned int)dimm_num);
742 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
743 printf("Replace the DIMM module with a supported DIMM.\n\n");
744 spd_ddr_init_hang ();
747 debug("DIMM slot %d: DDR1 SDRAM detected\n", dimm_num);
748 dimm_populated[dimm_num] = SDRAM_DDR1;
751 debug("DIMM slot %d: DDR2 SDRAM detected\n", dimm_num);
752 dimm_populated[dimm_num] = SDRAM_DDR2;
755 printf("ERROR: Unknown DIMM detected in slot %d.\n",
756 (unsigned int)dimm_num);
757 printf("Only DDR1 and DDR2 SDRAM DIMMs are supported.\n");
758 printf("Replace the DIMM module with a supported DIMM.\n\n");
759 spd_ddr_init_hang ();
764 for (dimm_num = 1; dimm_num < num_dimm_banks; dimm_num++) {
765 if ((dimm_populated[dimm_num-1] != SDRAM_NONE)
766 && (dimm_populated[dimm_num] != SDRAM_NONE)
767 && (dimm_populated[dimm_num-1] != dimm_populated[dimm_num])) {
768 printf("ERROR: DIMM's DDR1 and DDR2 type can not be mixed.\n");
769 spd_ddr_init_hang ();
774 /*------------------------------------------------------------------
775 * For the memory DIMMs installed, this routine verifies that
776 * frequency previously calculated is supported.
777 *-----------------------------------------------------------------*/
778 static void check_frequency(unsigned long *dimm_populated,
779 unsigned char *iic0_dimm_addr,
780 unsigned long num_dimm_banks)
782 unsigned long dimm_num;
783 unsigned long tcyc_reg;
784 unsigned long cycle_time;
785 unsigned long calc_cycle_time;
786 unsigned long sdram_freq;
787 unsigned long sdr_ddrpll;
788 PPC4xx_SYS_INFO board_cfg;
790 /*------------------------------------------------------------------
791 * Get the board configuration info.
792 *-----------------------------------------------------------------*/
793 get_sys_info(&board_cfg);
795 mfsdr(SDR0_DDR0, sdr_ddrpll);
796 sdram_freq = ((board_cfg.freqPLB) * SDR0_DDR0_DDRM_DECODE(sdr_ddrpll));
799 * calc_cycle_time is calculated from DDR frequency set by board/chip
800 * and is expressed in multiple of 10 picoseconds
801 * to match the way DIMM cycle time is calculated below.
803 calc_cycle_time = MULDIV64(ONE_BILLION, 100, sdram_freq);
805 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
806 if (dimm_populated[dimm_num] != SDRAM_NONE) {
807 tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 9);
809 * Byte 9, Cycle time for CAS Latency=X, is split into two nibbles:
810 * the higher order nibble (bits 4-7) designates the cycle time
811 * to a granularity of 1ns;
812 * the value presented by the lower order nibble (bits 0-3)
813 * has a granularity of .1ns and is added to the value designated
814 * by the higher nibble. In addition, four lines of the lower order
815 * nibble are assigned to support +.25,+.33, +.66 and +.75.
817 /* Convert from hex to decimal */
818 if ((tcyc_reg & 0x0F) == 0x0D)
819 cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) + 75;
820 else if ((tcyc_reg & 0x0F) == 0x0C)
821 cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) + 66;
822 else if ((tcyc_reg & 0x0F) == 0x0B)
823 cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) + 33;
824 else if ((tcyc_reg & 0x0F) == 0x0A)
825 cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) + 25;
827 cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) +
828 ((tcyc_reg & 0x0F)*10);
829 debug("cycle_time=%d [10 picoseconds]\n", cycle_time);
831 if (cycle_time > (calc_cycle_time + 10)) {
833 * the provided sdram cycle_time is too small
834 * for the available DIMM cycle_time.
835 * The additionnal 100ps is here to accept a small incertainty.
837 printf("ERROR: DRAM DIMM detected with cycle_time %d ps in "
838 "slot %d \n while calculated cycle time is %d ps.\n",
839 (unsigned int)(cycle_time*10),
840 (unsigned int)dimm_num,
841 (unsigned int)(calc_cycle_time*10));
842 printf("Replace the DIMM, or change DDR frequency via "
843 "strapping bits.\n\n");
844 spd_ddr_init_hang ();
850 /*------------------------------------------------------------------
851 * For the memory DIMMs installed, this routine verifies two
852 * ranks/banks maximum are availables.
853 *-----------------------------------------------------------------*/
854 static void check_rank_number(unsigned long *dimm_populated,
855 unsigned char *iic0_dimm_addr,
856 unsigned long num_dimm_banks)
858 unsigned long dimm_num;
859 unsigned long dimm_rank;
860 unsigned long total_rank = 0;
862 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
863 if (dimm_populated[dimm_num] != SDRAM_NONE) {
864 dimm_rank = spd_read(iic0_dimm_addr[dimm_num], 5);
865 if (((unsigned long)spd_read(iic0_dimm_addr[dimm_num], 2)) == 0x08)
866 dimm_rank = (dimm_rank & 0x0F) +1;
868 dimm_rank = dimm_rank & 0x0F;
871 if (dimm_rank > MAXRANKS) {
872 printf("ERROR: DRAM DIMM detected with %lu ranks in "
873 "slot %lu is not supported.\n", dimm_rank, dimm_num);
874 printf("Only %d ranks are supported for all DIMM.\n", MAXRANKS);
875 printf("Replace the DIMM module with a supported DIMM.\n\n");
876 spd_ddr_init_hang ();
878 total_rank += dimm_rank;
880 if (total_rank > MAXRANKS) {
881 printf("ERROR: DRAM DIMM detected with a total of %d ranks "
882 "for all slots.\n", (unsigned int)total_rank);
883 printf("Only %d ranks are supported for all DIMM.\n", MAXRANKS);
884 printf("Remove one of the DIMM modules.\n\n");
885 spd_ddr_init_hang ();
890 /*------------------------------------------------------------------
891 * only support 2.5V modules.
892 * This routine verifies this.
893 *-----------------------------------------------------------------*/
894 static void check_voltage_type(unsigned long *dimm_populated,
895 unsigned char *iic0_dimm_addr,
896 unsigned long num_dimm_banks)
898 unsigned long dimm_num;
899 unsigned long voltage_type;
901 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
902 if (dimm_populated[dimm_num] != SDRAM_NONE) {
903 voltage_type = spd_read(iic0_dimm_addr[dimm_num], 8);
904 switch (voltage_type) {
906 printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
907 printf("This DIMM is 5.0 Volt/TTL.\n");
908 printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
909 (unsigned int)dimm_num);
910 spd_ddr_init_hang ();
913 printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
914 printf("This DIMM is LVTTL.\n");
915 printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
916 (unsigned int)dimm_num);
917 spd_ddr_init_hang ();
920 printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
921 printf("This DIMM is 1.5 Volt.\n");
922 printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
923 (unsigned int)dimm_num);
924 spd_ddr_init_hang ();
927 printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
928 printf("This DIMM is 3.3 Volt/TTL.\n");
929 printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
930 (unsigned int)dimm_num);
931 spd_ddr_init_hang ();
934 /* 2.5 Voltage only for DDR1 */
937 /* 1.8 Voltage only for DDR2 */
940 printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
941 printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
942 (unsigned int)dimm_num);
943 spd_ddr_init_hang ();
950 /*-----------------------------------------------------------------------------+
952 *-----------------------------------------------------------------------------*/
953 static void program_copt1(unsigned long *dimm_populated,
954 unsigned char *iic0_dimm_addr,
955 unsigned long num_dimm_banks)
957 unsigned long dimm_num;
958 unsigned long mcopt1;
959 unsigned long ecc_enabled;
960 unsigned long ecc = 0;
961 unsigned long data_width = 0;
962 unsigned long dimm_32bit;
963 unsigned long dimm_64bit;
964 unsigned long registered = 0;
965 unsigned long attribute = 0;
966 unsigned long buf0, buf1; /* TODO: code to be changed for IOP1.6 to support 4 DIMMs */
967 unsigned long bankcount;
968 unsigned long ddrtype;
971 #ifdef CONFIG_DDR_ECC
981 /*------------------------------------------------------------------
982 * Set memory controller options reg 1, SDRAM_MCOPT1.
983 *-----------------------------------------------------------------*/
984 mfsdram(SDRAM_MCOPT1, val);
985 mcopt1 = val & ~(SDRAM_MCOPT1_MCHK_MASK | SDRAM_MCOPT1_RDEN_MASK |
986 SDRAM_MCOPT1_PMU_MASK | SDRAM_MCOPT1_DMWD_MASK |
987 SDRAM_MCOPT1_UIOS_MASK | SDRAM_MCOPT1_BCNT_MASK |
988 SDRAM_MCOPT1_DDR_TYPE_MASK | SDRAM_MCOPT1_RWOO_MASK |
989 SDRAM_MCOPT1_WOOO_MASK | SDRAM_MCOPT1_DCOO_MASK |
990 SDRAM_MCOPT1_DREF_MASK);
992 mcopt1 |= SDRAM_MCOPT1_QDEP;
993 mcopt1 |= SDRAM_MCOPT1_PMU_OPEN;
994 mcopt1 |= SDRAM_MCOPT1_RWOO_DISABLED;
995 mcopt1 |= SDRAM_MCOPT1_WOOO_DISABLED;
996 mcopt1 |= SDRAM_MCOPT1_DCOO_DISABLED;
997 mcopt1 |= SDRAM_MCOPT1_DREF_NORMAL;
999 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1000 if (dimm_populated[dimm_num] != SDRAM_NONE) {
1001 /* test ecc support */
1002 ecc = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 11);
1003 if (ecc != 0x02) /* ecc not supported */
1004 ecc_enabled = FALSE;
1006 /* test bank count */
1007 bankcount = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 17);
1008 if (bankcount == 0x04) /* bank count = 4 */
1009 mcopt1 |= SDRAM_MCOPT1_4_BANKS;
1010 else /* bank count = 8 */
1011 mcopt1 |= SDRAM_MCOPT1_8_BANKS;
1014 ddrtype = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 2);
1015 /* test for buffered/unbuffered, registered, differential clocks */
1016 registered = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 20);
1017 attribute = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 21);
1019 /* TODO: code to be changed for IOP1.6 to support 4 DIMMs */
1020 if (dimm_num == 0) {
1021 if (dimm_populated[dimm_num] == SDRAM_DDR1) /* DDR1 type */
1022 mcopt1 |= SDRAM_MCOPT1_DDR1_TYPE;
1023 if (dimm_populated[dimm_num] == SDRAM_DDR2) /* DDR2 type */
1024 mcopt1 |= SDRAM_MCOPT1_DDR2_TYPE;
1025 if (registered == 1) { /* DDR2 always buffered */
1026 /* TODO: what about above comments ? */
1027 mcopt1 |= SDRAM_MCOPT1_RDEN;
1030 /* TODO: the mask 0x02 doesn't match Samsung def for byte 21. */
1031 if ((attribute & 0x02) == 0x00) {
1032 /* buffered not supported */
1035 mcopt1 |= SDRAM_MCOPT1_RDEN;
1040 else if (dimm_num == 1) {
1041 if (dimm_populated[dimm_num] == SDRAM_DDR1) /* DDR1 type */
1042 mcopt1 |= SDRAM_MCOPT1_DDR1_TYPE;
1043 if (dimm_populated[dimm_num] == SDRAM_DDR2) /* DDR2 type */
1044 mcopt1 |= SDRAM_MCOPT1_DDR2_TYPE;
1045 if (registered == 1) {
1046 /* DDR2 always buffered */
1047 mcopt1 |= SDRAM_MCOPT1_RDEN;
1050 if ((attribute & 0x02) == 0x00) {
1051 /* buffered not supported */
1054 mcopt1 |= SDRAM_MCOPT1_RDEN;
1060 /* Note that for DDR2 the byte 7 is reserved, but OK to keep code as is. */
1061 data_width = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 6) +
1062 (((unsigned long)spd_read(iic0_dimm_addr[dimm_num], 7)) << 8);
1064 switch (data_width) {
1074 printf("WARNING: Detected a DIMM with a data width of %lu bits.\n",
1076 printf("Only DIMMs with 32 or 64 bit DDR-SDRAM widths are supported.\n");
1082 /* verify matching properties */
1083 if ((dimm_populated[0] != SDRAM_NONE) && (dimm_populated[1] != SDRAM_NONE)) {
1085 printf("ERROR: DIMM's buffered/unbuffered, registered, clocking don't match.\n");
1086 spd_ddr_init_hang ();
1090 if ((dimm_64bit == TRUE) && (dimm_32bit == TRUE)) {
1091 printf("ERROR: Cannot mix 32 bit and 64 bit DDR-SDRAM DIMMs together.\n");
1092 spd_ddr_init_hang ();
1094 else if ((dimm_64bit == TRUE) && (dimm_32bit == FALSE)) {
1095 mcopt1 |= SDRAM_MCOPT1_DMWD_64;
1096 } else if ((dimm_64bit == FALSE) && (dimm_32bit == TRUE)) {
1097 mcopt1 |= SDRAM_MCOPT1_DMWD_32;
1099 printf("ERROR: Please install only 32 or 64 bit DDR-SDRAM DIMMs.\n\n");
1100 spd_ddr_init_hang ();
1103 if (ecc_enabled == TRUE)
1104 mcopt1 |= SDRAM_MCOPT1_MCHK_GEN;
1106 mcopt1 |= SDRAM_MCOPT1_MCHK_NON;
1108 mtsdram(SDRAM_MCOPT1, mcopt1);
1111 /*-----------------------------------------------------------------------------+
1113 *-----------------------------------------------------------------------------*/
1114 static void program_codt(unsigned long *dimm_populated,
1115 unsigned char *iic0_dimm_addr,
1116 unsigned long num_dimm_banks)
1119 unsigned long modt0 = 0;
1120 unsigned long modt1 = 0;
1121 unsigned long modt2 = 0;
1122 unsigned long modt3 = 0;
1123 unsigned char dimm_num;
1124 unsigned char dimm_rank;
1125 unsigned char total_rank = 0;
1126 unsigned char total_dimm = 0;
1127 unsigned char dimm_type = 0;
1128 unsigned char firstSlot = 0;
1130 /*------------------------------------------------------------------
1131 * Set the SDRAM Controller On Die Termination Register
1132 *-----------------------------------------------------------------*/
1133 mfsdram(SDRAM_CODT, codt);
1134 codt |= (SDRAM_CODT_IO_NMODE
1135 & (~SDRAM_CODT_DQS_SINGLE_END
1136 & ~SDRAM_CODT_CKSE_SINGLE_END
1137 & ~SDRAM_CODT_FEEBBACK_RCV_SINGLE_END
1138 & ~SDRAM_CODT_FEEBBACK_DRV_SINGLE_END));
1140 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1141 if (dimm_populated[dimm_num] != SDRAM_NONE) {
1142 dimm_rank = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 5);
1143 if (((unsigned long)spd_read(iic0_dimm_addr[dimm_num], 2)) == 0x08) {
1144 dimm_rank = (dimm_rank & 0x0F) + 1;
1145 dimm_type = SDRAM_DDR2;
1147 dimm_rank = dimm_rank & 0x0F;
1148 dimm_type = SDRAM_DDR1;
1151 total_rank += dimm_rank;
1153 if ((dimm_num == 0) && (total_dimm == 1))
1159 if (dimm_type == SDRAM_DDR2) {
1160 codt |= SDRAM_CODT_DQS_1_8_V_DDR2;
1161 if ((total_dimm == 1) && (firstSlot == TRUE)) {
1162 if (total_rank == 1) { /* PUUU */
1163 codt |= CALC_ODT_R(0);
1164 modt0 = CALC_ODT_W(0);
1169 if (total_rank == 2) { /* PPUU */
1170 codt |= CALC_ODT_R(0) | CALC_ODT_R(1);
1171 modt0 = CALC_ODT_W(0) | CALC_ODT_W(1);
1176 } else if ((total_dimm == 1) && (firstSlot != TRUE)) {
1177 if (total_rank == 1) { /* UUPU */
1178 codt |= CALC_ODT_R(2);
1181 modt2 = CALC_ODT_W(2);
1184 if (total_rank == 2) { /* UUPP */
1185 codt |= CALC_ODT_R(2) | CALC_ODT_R(3);
1188 modt2 = CALC_ODT_W(2) | CALC_ODT_W(3);
1192 if (total_dimm == 2) {
1193 if (total_rank == 2) { /* PUPU */
1194 codt |= CALC_ODT_R(0) | CALC_ODT_R(2);
1195 modt0 = CALC_ODT_RW(2);
1197 modt2 = CALC_ODT_RW(0);
1200 if (total_rank == 4) { /* PPPP */
1201 codt |= CALC_ODT_R(0) | CALC_ODT_R(1) |
1202 CALC_ODT_R(2) | CALC_ODT_R(3);
1203 modt0 = CALC_ODT_RW(2) | CALC_ODT_RW(3);
1205 modt2 = CALC_ODT_RW(0) | CALC_ODT_RW(1);
1210 codt |= SDRAM_CODT_DQS_2_5_V_DDR1;
1216 if (total_dimm == 1) {
1217 if (total_rank == 1)
1219 if (total_rank == 2)
1222 if (total_dimm == 2) {
1223 if (total_rank == 2)
1225 if (total_rank == 4)
1230 debug("nb of dimm %d\n", total_dimm);
1231 debug("nb of rank %d\n", total_rank);
1232 if (total_dimm == 1)
1233 debug("dimm in slot %d\n", firstSlot);
1235 mtsdram(SDRAM_CODT, codt);
1236 mtsdram(SDRAM_MODT0, modt0);
1237 mtsdram(SDRAM_MODT1, modt1);
1238 mtsdram(SDRAM_MODT2, modt2);
1239 mtsdram(SDRAM_MODT3, modt3);
1242 /*-----------------------------------------------------------------------------+
1244 *-----------------------------------------------------------------------------*/
1245 static void program_initplr(unsigned long *dimm_populated,
1246 unsigned char *iic0_dimm_addr,
1247 unsigned long num_dimm_banks,
1248 ddr_cas_id_t selected_cas,
1262 /******************************************************
1263 ** Assumption: if more than one DIMM, all DIMMs are the same
1264 ** as already checked in check_memory_type
1265 ******************************************************/
1267 if ((dimm_populated[0] == SDRAM_DDR1) || (dimm_populated[1] == SDRAM_DDR1)) {
1268 mtsdram(SDRAM_INITPLR0, 0x81B80000);
1269 mtsdram(SDRAM_INITPLR1, 0x81900400);
1270 mtsdram(SDRAM_INITPLR2, 0x81810000);
1271 mtsdram(SDRAM_INITPLR3, 0xff800162);
1272 mtsdram(SDRAM_INITPLR4, 0x81900400);
1273 mtsdram(SDRAM_INITPLR5, 0x86080000);
1274 mtsdram(SDRAM_INITPLR6, 0x86080000);
1275 mtsdram(SDRAM_INITPLR7, 0x81000062);
1276 } else if ((dimm_populated[0] == SDRAM_DDR2) || (dimm_populated[1] == SDRAM_DDR2)) {
1277 switch (selected_cas) {
1288 printf("ERROR: ucode error on selected_cas value %d", selected_cas);
1289 spd_ddr_init_hang ();
1295 * ToDo - Still a problem with the write recovery:
1296 * On the Corsair CM2X512-5400C4 module, setting write recovery
1297 * in the INITPLR reg to the value calculated in program_mode()
1298 * results in not correctly working DDR2 memory (crash after
1301 * So for now, set the write recovery to 3. This seems to work
1302 * on the Corair module too.
1306 switch (write_recovery) {
1320 printf("ERROR: write recovery not support (%d)", write_recovery);
1321 spd_ddr_init_hang ();
1325 wr = WRITE_RECOV_3; /* test-only, see description above */
1328 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++)
1329 if (dimm_populated[dimm_num] != SDRAM_NONE)
1331 if (total_dimm == 1) {
1334 } else if (total_dimm == 2) {
1338 printf("ERROR: Unsupported number of DIMM's (%d)", total_dimm);
1339 spd_ddr_init_hang ();
1342 mr = CMD_EMR | SELECT_MR | BURST_LEN_4 | wr | cas;
1343 emr = CMD_EMR | SELECT_EMR | odt | ods;
1344 emr2 = CMD_EMR | SELECT_EMR2;
1345 emr3 = CMD_EMR | SELECT_EMR3;
1346 mtsdram(SDRAM_INITPLR0, 0xB5000000 | CMD_NOP); /* NOP */
1348 mtsdram(SDRAM_INITPLR1, 0x82000400 | CMD_PRECHARGE); /* precharge 8 DDR clock cycle */
1349 mtsdram(SDRAM_INITPLR2, 0x80800000 | emr2); /* EMR2 */
1350 mtsdram(SDRAM_INITPLR3, 0x80800000 | emr3); /* EMR3 */
1351 mtsdram(SDRAM_INITPLR4, 0x80800000 | emr); /* EMR DLL ENABLE */
1352 mtsdram(SDRAM_INITPLR5, 0x80800000 | mr | DLL_RESET); /* MR w/ DLL reset */
1354 mtsdram(SDRAM_INITPLR6, 0x82000400 | CMD_PRECHARGE); /* precharge 8 DDR clock cycle */
1355 mtsdram(SDRAM_INITPLR7, 0x8a000000 | CMD_REFRESH); /* Refresh 50 DDR clock cycle */
1356 mtsdram(SDRAM_INITPLR8, 0x8a000000 | CMD_REFRESH); /* Refresh 50 DDR clock cycle */
1357 mtsdram(SDRAM_INITPLR9, 0x8a000000 | CMD_REFRESH); /* Refresh 50 DDR clock cycle */
1358 mtsdram(SDRAM_INITPLR10, 0x8a000000 | CMD_REFRESH); /* Refresh 50 DDR clock cycle */
1359 mtsdram(SDRAM_INITPLR11, 0x80000000 | mr); /* MR w/o DLL reset */
1360 mtsdram(SDRAM_INITPLR12, 0x80800380 | emr); /* EMR OCD Default */
1361 mtsdram(SDRAM_INITPLR13, 0x80800000 | emr); /* EMR OCD Exit */
1363 printf("ERROR: ucode error as unknown DDR type in program_initplr");
1364 spd_ddr_init_hang ();
1368 /*------------------------------------------------------------------
1369 * This routine programs the SDRAM_MMODE register.
1370 * the selected_cas is an output parameter, that will be passed
1371 * by caller to call the above program_initplr( )
1372 *-----------------------------------------------------------------*/
1373 static void program_mode(unsigned long *dimm_populated,
1374 unsigned char *iic0_dimm_addr,
1375 unsigned long num_dimm_banks,
1376 ddr_cas_id_t *selected_cas,
1377 int *write_recovery)
1379 unsigned long dimm_num;
1380 unsigned long sdram_ddr1;
1381 unsigned long t_wr_ns;
1382 unsigned long t_wr_clk;
1383 unsigned long cas_bit;
1384 unsigned long cas_index;
1385 unsigned long sdram_freq;
1386 unsigned long ddr_check;
1387 unsigned long mmode;
1388 unsigned long tcyc_reg;
1389 unsigned long cycle_2_0_clk;
1390 unsigned long cycle_2_5_clk;
1391 unsigned long cycle_3_0_clk;
1392 unsigned long cycle_4_0_clk;
1393 unsigned long cycle_5_0_clk;
1394 unsigned long max_2_0_tcyc_ns_x_100;
1395 unsigned long max_2_5_tcyc_ns_x_100;
1396 unsigned long max_3_0_tcyc_ns_x_100;
1397 unsigned long max_4_0_tcyc_ns_x_100;
1398 unsigned long max_5_0_tcyc_ns_x_100;
1399 unsigned long cycle_time_ns_x_100[3];
1400 PPC4xx_SYS_INFO board_cfg;
1401 unsigned char cas_2_0_available;
1402 unsigned char cas_2_5_available;
1403 unsigned char cas_3_0_available;
1404 unsigned char cas_4_0_available;
1405 unsigned char cas_5_0_available;
1406 unsigned long sdr_ddrpll;
1408 /*------------------------------------------------------------------
1409 * Get the board configuration info.
1410 *-----------------------------------------------------------------*/
1411 get_sys_info(&board_cfg);
1413 mfsdr(SDR0_DDR0, sdr_ddrpll);
1414 sdram_freq = MULDIV64((board_cfg.freqPLB), SDR0_DDR0_DDRM_DECODE(sdr_ddrpll), 1);
1415 debug("sdram_freq=%d\n", sdram_freq);
1417 /*------------------------------------------------------------------
1418 * Handle the timing. We need to find the worst case timing of all
1419 * the dimm modules installed.
1420 *-----------------------------------------------------------------*/
1422 cas_2_0_available = TRUE;
1423 cas_2_5_available = TRUE;
1424 cas_3_0_available = TRUE;
1425 cas_4_0_available = TRUE;
1426 cas_5_0_available = TRUE;
1427 max_2_0_tcyc_ns_x_100 = 10;
1428 max_2_5_tcyc_ns_x_100 = 10;
1429 max_3_0_tcyc_ns_x_100 = 10;
1430 max_4_0_tcyc_ns_x_100 = 10;
1431 max_5_0_tcyc_ns_x_100 = 10;
1434 /* loop through all the DIMM slots on the board */
1435 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1436 /* If a dimm is installed in a particular slot ... */
1437 if (dimm_populated[dimm_num] != SDRAM_NONE) {
1438 if (dimm_populated[dimm_num] == SDRAM_DDR1)
1443 /* t_wr_ns = max(t_wr_ns, (unsigned long)dimm_spd[dimm_num][36] >> 2); */ /* not used in this loop. */
1444 cas_bit = spd_read(iic0_dimm_addr[dimm_num], 18);
1445 debug("cas_bit[SPD byte 18]=%02x\n", cas_bit);
1447 /* For a particular DIMM, grab the three CAS values it supports */
1448 for (cas_index = 0; cas_index < 3; cas_index++) {
1449 switch (cas_index) {
1451 tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 9);
1454 tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 23);
1457 tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 25);
1461 if ((tcyc_reg & 0x0F) >= 10) {
1462 if ((tcyc_reg & 0x0F) == 0x0D) {
1463 /* Convert from hex to decimal */
1464 cycle_time_ns_x_100[cas_index] =
1465 (((tcyc_reg & 0xF0) >> 4) * 100) + 75;
1467 printf("ERROR: SPD reported Tcyc is incorrect for DIMM "
1468 "in slot %d\n", (unsigned int)dimm_num);
1469 spd_ddr_init_hang ();
1472 /* Convert from hex to decimal */
1473 cycle_time_ns_x_100[cas_index] =
1474 (((tcyc_reg & 0xF0) >> 4) * 100) +
1475 ((tcyc_reg & 0x0F)*10);
1477 debug("cas_index=%d: cycle_time_ns_x_100=%d\n", cas_index,
1478 cycle_time_ns_x_100[cas_index]);
1481 /* The rest of this routine determines if CAS 2.0, 2.5, 3.0, 4.0 and 5.0 are */
1482 /* supported for a particular DIMM. */
1487 * DDR devices use the following bitmask for CAS latency:
1488 * Bit 7 6 5 4 3 2 1 0
1489 * TBD 4.0 3.5 3.0 2.5 2.0 1.5 1.0
1491 if (((cas_bit & 0x40) == 0x40) && (cas_index < 3) &&
1492 (cycle_time_ns_x_100[cas_index] != 0)) {
1493 max_4_0_tcyc_ns_x_100 = max(max_4_0_tcyc_ns_x_100,
1494 cycle_time_ns_x_100[cas_index]);
1499 cas_4_0_available = FALSE;
1502 if (((cas_bit & 0x10) == 0x10) && (cas_index < 3) &&
1503 (cycle_time_ns_x_100[cas_index] != 0)) {
1504 max_3_0_tcyc_ns_x_100 = max(max_3_0_tcyc_ns_x_100,
1505 cycle_time_ns_x_100[cas_index]);
1510 cas_3_0_available = FALSE;
1513 if (((cas_bit & 0x08) == 0x08) && (cas_index < 3) &&
1514 (cycle_time_ns_x_100[cas_index] != 0)) {
1515 max_2_5_tcyc_ns_x_100 = max(max_2_5_tcyc_ns_x_100,
1516 cycle_time_ns_x_100[cas_index]);
1521 cas_2_5_available = FALSE;
1524 if (((cas_bit & 0x04) == 0x04) && (cas_index < 3) &&
1525 (cycle_time_ns_x_100[cas_index] != 0)) {
1526 max_2_0_tcyc_ns_x_100 = max(max_2_0_tcyc_ns_x_100,
1527 cycle_time_ns_x_100[cas_index]);
1532 cas_2_0_available = FALSE;
1536 * DDR2 devices use the following bitmask for CAS latency:
1537 * Bit 7 6 5 4 3 2 1 0
1538 * TBD 6.0 5.0 4.0 3.0 2.0 TBD TBD
1540 if (((cas_bit & 0x20) == 0x20) && (cas_index < 3) &&
1541 (cycle_time_ns_x_100[cas_index] != 0)) {
1542 max_5_0_tcyc_ns_x_100 = max(max_5_0_tcyc_ns_x_100,
1543 cycle_time_ns_x_100[cas_index]);
1548 cas_5_0_available = FALSE;
1551 if (((cas_bit & 0x10) == 0x10) && (cas_index < 3) &&
1552 (cycle_time_ns_x_100[cas_index] != 0)) {
1553 max_4_0_tcyc_ns_x_100 = max(max_4_0_tcyc_ns_x_100,
1554 cycle_time_ns_x_100[cas_index]);
1559 cas_4_0_available = FALSE;
1562 if (((cas_bit & 0x08) == 0x08) && (cas_index < 3) &&
1563 (cycle_time_ns_x_100[cas_index] != 0)) {
1564 max_3_0_tcyc_ns_x_100 = max(max_3_0_tcyc_ns_x_100,
1565 cycle_time_ns_x_100[cas_index]);
1570 cas_3_0_available = FALSE;
1576 /*------------------------------------------------------------------
1577 * Set the SDRAM mode, SDRAM_MMODE
1578 *-----------------------------------------------------------------*/
1579 mfsdram(SDRAM_MMODE, mmode);
1580 mmode = mmode & ~(SDRAM_MMODE_WR_MASK | SDRAM_MMODE_DCL_MASK);
1582 /* add 10 here because of rounding problems */
1583 cycle_2_0_clk = MULDIV64(ONE_BILLION, 100, max_2_0_tcyc_ns_x_100) + 10;
1584 cycle_2_5_clk = MULDIV64(ONE_BILLION, 100, max_2_5_tcyc_ns_x_100) + 10;
1585 cycle_3_0_clk = MULDIV64(ONE_BILLION, 100, max_3_0_tcyc_ns_x_100) + 10;
1586 cycle_4_0_clk = MULDIV64(ONE_BILLION, 100, max_4_0_tcyc_ns_x_100) + 10;
1587 cycle_5_0_clk = MULDIV64(ONE_BILLION, 100, max_5_0_tcyc_ns_x_100) + 10;
1588 debug("cycle_3_0_clk=%d\n", cycle_3_0_clk);
1589 debug("cycle_4_0_clk=%d\n", cycle_4_0_clk);
1590 debug("cycle_5_0_clk=%d\n", cycle_5_0_clk);
1592 if (sdram_ddr1 == TRUE) { /* DDR1 */
1593 if ((cas_2_0_available == TRUE) && (sdram_freq <= cycle_2_0_clk)) {
1594 mmode |= SDRAM_MMODE_DCL_DDR1_2_0_CLK;
1595 *selected_cas = DDR_CAS_2;
1596 } else if ((cas_2_5_available == TRUE) && (sdram_freq <= cycle_2_5_clk)) {
1597 mmode |= SDRAM_MMODE_DCL_DDR1_2_5_CLK;
1598 *selected_cas = DDR_CAS_2_5;
1599 } else if ((cas_3_0_available == TRUE) && (sdram_freq <= cycle_3_0_clk)) {
1600 mmode |= SDRAM_MMODE_DCL_DDR1_3_0_CLK;
1601 *selected_cas = DDR_CAS_3;
1603 printf("ERROR: Cannot find a supported CAS latency with the installed DIMMs.\n");
1604 printf("Only DIMMs DDR1 with CAS latencies of 2.0, 2.5, and 3.0 are supported.\n");
1605 printf("Make sure the PLB speed is within the supported range of the DIMMs.\n\n");
1606 spd_ddr_init_hang ();
1609 debug("cas_3_0_available=%d\n", cas_3_0_available);
1610 debug("cas_4_0_available=%d\n", cas_4_0_available);
1611 debug("cas_5_0_available=%d\n", cas_5_0_available);
1612 if ((cas_3_0_available == TRUE) && (sdram_freq <= cycle_3_0_clk)) {
1613 mmode |= SDRAM_MMODE_DCL_DDR2_3_0_CLK;
1614 *selected_cas = DDR_CAS_3;
1615 } else if ((cas_4_0_available == TRUE) && (sdram_freq <= cycle_4_0_clk)) {
1616 mmode |= SDRAM_MMODE_DCL_DDR2_4_0_CLK;
1617 *selected_cas = DDR_CAS_4;
1618 } else if ((cas_5_0_available == TRUE) && (sdram_freq <= cycle_5_0_clk)) {
1619 mmode |= SDRAM_MMODE_DCL_DDR2_5_0_CLK;
1620 *selected_cas = DDR_CAS_5;
1622 printf("ERROR: Cannot find a supported CAS latency with the installed DIMMs.\n");
1623 printf("Only DIMMs DDR2 with CAS latencies of 3.0, 4.0, and 5.0 are supported.\n");
1624 printf("Make sure the PLB speed is within the supported range of the DIMMs.\n");
1625 printf("cas3=%d cas4=%d cas5=%d\n",
1626 cas_3_0_available, cas_4_0_available, cas_5_0_available);
1627 printf("sdram_freq=%lu cycle3=%lu cycle4=%lu cycle5=%lu\n\n",
1628 sdram_freq, cycle_3_0_clk, cycle_4_0_clk, cycle_5_0_clk);
1629 spd_ddr_init_hang ();
1633 if (sdram_ddr1 == TRUE)
1634 mmode |= SDRAM_MMODE_WR_DDR1;
1637 /* loop through all the DIMM slots on the board */
1638 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1639 /* If a dimm is installed in a particular slot ... */
1640 if (dimm_populated[dimm_num] != SDRAM_NONE)
1641 t_wr_ns = max(t_wr_ns,
1642 spd_read(iic0_dimm_addr[dimm_num], 36) >> 2);
1646 * convert from nanoseconds to ddr clocks
1647 * round up if necessary
1649 t_wr_clk = MULDIV64(sdram_freq, t_wr_ns, ONE_BILLION);
1650 ddr_check = MULDIV64(ONE_BILLION, t_wr_clk, t_wr_ns);
1651 if (sdram_freq != ddr_check)
1659 mmode |= SDRAM_MMODE_WR_DDR2_3_CYC;
1662 mmode |= SDRAM_MMODE_WR_DDR2_4_CYC;
1665 mmode |= SDRAM_MMODE_WR_DDR2_5_CYC;
1668 mmode |= SDRAM_MMODE_WR_DDR2_6_CYC;
1671 *write_recovery = t_wr_clk;
1674 debug("CAS latency = %d\n", *selected_cas);
1675 debug("Write recovery = %d\n", *write_recovery);
1677 mtsdram(SDRAM_MMODE, mmode);
1680 /*-----------------------------------------------------------------------------+
1682 *-----------------------------------------------------------------------------*/
1683 static void program_rtr(unsigned long *dimm_populated,
1684 unsigned char *iic0_dimm_addr,
1685 unsigned long num_dimm_banks)
1687 PPC4xx_SYS_INFO board_cfg;
1688 unsigned long max_refresh_rate;
1689 unsigned long dimm_num;
1690 unsigned long refresh_rate_type;
1691 unsigned long refresh_rate;
1693 unsigned long sdram_freq;
1694 unsigned long sdr_ddrpll;
1697 /*------------------------------------------------------------------
1698 * Get the board configuration info.
1699 *-----------------------------------------------------------------*/
1700 get_sys_info(&board_cfg);
1702 /*------------------------------------------------------------------
1703 * Set the SDRAM Refresh Timing Register, SDRAM_RTR
1704 *-----------------------------------------------------------------*/
1705 mfsdr(SDR0_DDR0, sdr_ddrpll);
1706 sdram_freq = ((board_cfg.freqPLB) * SDR0_DDR0_DDRM_DECODE(sdr_ddrpll));
1708 max_refresh_rate = 0;
1709 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1710 if (dimm_populated[dimm_num] != SDRAM_NONE) {
1712 refresh_rate_type = spd_read(iic0_dimm_addr[dimm_num], 12);
1713 refresh_rate_type &= 0x7F;
1714 switch (refresh_rate_type) {
1716 refresh_rate = 15625;
1719 refresh_rate = 3906;
1722 refresh_rate = 7812;
1725 refresh_rate = 31250;
1728 refresh_rate = 62500;
1731 refresh_rate = 125000;
1735 printf("ERROR: DIMM %d unsupported refresh rate/type.\n",
1736 (unsigned int)dimm_num);
1737 printf("Replace the DIMM module with a supported DIMM.\n\n");
1738 spd_ddr_init_hang ();
1742 max_refresh_rate = max(max_refresh_rate, refresh_rate);
1746 rint = MULDIV64(sdram_freq, max_refresh_rate, ONE_BILLION);
1747 mfsdram(SDRAM_RTR, val);
1748 mtsdram(SDRAM_RTR, (val & ~SDRAM_RTR_RINT_MASK) |
1749 (SDRAM_RTR_RINT_ENCODE(rint)));
1752 /*------------------------------------------------------------------
1753 * This routine programs the SDRAM_TRx registers.
1754 *-----------------------------------------------------------------*/
1755 static void program_tr(unsigned long *dimm_populated,
1756 unsigned char *iic0_dimm_addr,
1757 unsigned long num_dimm_banks)
1759 unsigned long dimm_num;
1760 unsigned long sdram_ddr1;
1761 unsigned long t_rp_ns;
1762 unsigned long t_rcd_ns;
1763 unsigned long t_rrd_ns;
1764 unsigned long t_ras_ns;
1765 unsigned long t_rc_ns;
1766 unsigned long t_rfc_ns;
1767 unsigned long t_wpc_ns;
1768 unsigned long t_wtr_ns;
1769 unsigned long t_rpc_ns;
1770 unsigned long t_rp_clk;
1771 unsigned long t_rcd_clk;
1772 unsigned long t_rrd_clk;
1773 unsigned long t_ras_clk;
1774 unsigned long t_rc_clk;
1775 unsigned long t_rfc_clk;
1776 unsigned long t_wpc_clk;
1777 unsigned long t_wtr_clk;
1778 unsigned long t_rpc_clk;
1779 unsigned long sdtr1, sdtr2, sdtr3;
1780 unsigned long ddr_check;
1781 unsigned long sdram_freq;
1782 unsigned long sdr_ddrpll;
1784 PPC4xx_SYS_INFO board_cfg;
1786 /*------------------------------------------------------------------
1787 * Get the board configuration info.
1788 *-----------------------------------------------------------------*/
1789 get_sys_info(&board_cfg);
1791 mfsdr(SDR0_DDR0, sdr_ddrpll);
1792 sdram_freq = ((board_cfg.freqPLB) * SDR0_DDR0_DDRM_DECODE(sdr_ddrpll));
1794 /*------------------------------------------------------------------
1795 * Handle the timing. We need to find the worst case timing of all
1796 * the dimm modules installed.
1797 *-----------------------------------------------------------------*/
1809 /* loop through all the DIMM slots on the board */
1810 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1811 /* If a dimm is installed in a particular slot ... */
1812 if (dimm_populated[dimm_num] != SDRAM_NONE) {
1813 if (dimm_populated[dimm_num] == SDRAM_DDR2)
1818 t_rcd_ns = max(t_rcd_ns, spd_read(iic0_dimm_addr[dimm_num], 29) >> 2);
1819 t_rrd_ns = max(t_rrd_ns, spd_read(iic0_dimm_addr[dimm_num], 28) >> 2);
1820 t_rp_ns = max(t_rp_ns, spd_read(iic0_dimm_addr[dimm_num], 27) >> 2);
1821 t_ras_ns = max(t_ras_ns, spd_read(iic0_dimm_addr[dimm_num], 30));
1822 t_rc_ns = max(t_rc_ns, spd_read(iic0_dimm_addr[dimm_num], 41));
1823 t_rfc_ns = max(t_rfc_ns, spd_read(iic0_dimm_addr[dimm_num], 42));
1827 /*------------------------------------------------------------------
1828 * Set the SDRAM Timing Reg 1, SDRAM_TR1
1829 *-----------------------------------------------------------------*/
1830 mfsdram(SDRAM_SDTR1, sdtr1);
1831 sdtr1 &= ~(SDRAM_SDTR1_LDOF_MASK | SDRAM_SDTR1_RTW_MASK |
1832 SDRAM_SDTR1_WTWO_MASK | SDRAM_SDTR1_RTRO_MASK);
1834 /* default values */
1835 sdtr1 |= SDRAM_SDTR1_LDOF_2_CLK;
1836 sdtr1 |= SDRAM_SDTR1_RTW_2_CLK;
1838 /* normal operations */
1839 sdtr1 |= SDRAM_SDTR1_WTWO_0_CLK;
1840 sdtr1 |= SDRAM_SDTR1_RTRO_1_CLK;
1842 mtsdram(SDRAM_SDTR1, sdtr1);
1844 /*------------------------------------------------------------------
1845 * Set the SDRAM Timing Reg 2, SDRAM_TR2
1846 *-----------------------------------------------------------------*/
1847 mfsdram(SDRAM_SDTR2, sdtr2);
1848 sdtr2 &= ~(SDRAM_SDTR2_RCD_MASK | SDRAM_SDTR2_WTR_MASK |
1849 SDRAM_SDTR2_XSNR_MASK | SDRAM_SDTR2_WPC_MASK |
1850 SDRAM_SDTR2_RPC_MASK | SDRAM_SDTR2_RP_MASK |
1851 SDRAM_SDTR2_RRD_MASK);
1854 * convert t_rcd from nanoseconds to ddr clocks
1855 * round up if necessary
1857 t_rcd_clk = MULDIV64(sdram_freq, t_rcd_ns, ONE_BILLION);
1858 ddr_check = MULDIV64(ONE_BILLION, t_rcd_clk, t_rcd_ns);
1859 if (sdram_freq != ddr_check)
1862 switch (t_rcd_clk) {
1865 sdtr2 |= SDRAM_SDTR2_RCD_1_CLK;
1868 sdtr2 |= SDRAM_SDTR2_RCD_2_CLK;
1871 sdtr2 |= SDRAM_SDTR2_RCD_3_CLK;
1874 sdtr2 |= SDRAM_SDTR2_RCD_4_CLK;
1877 sdtr2 |= SDRAM_SDTR2_RCD_5_CLK;
1881 if (sdram_ddr1 == TRUE) { /* DDR1 */
1882 if (sdram_freq < 200000000) {
1883 sdtr2 |= SDRAM_SDTR2_WTR_1_CLK;
1884 sdtr2 |= SDRAM_SDTR2_WPC_2_CLK;
1885 sdtr2 |= SDRAM_SDTR2_RPC_2_CLK;
1887 sdtr2 |= SDRAM_SDTR2_WTR_2_CLK;
1888 sdtr2 |= SDRAM_SDTR2_WPC_3_CLK;
1889 sdtr2 |= SDRAM_SDTR2_RPC_2_CLK;
1892 /* loop through all the DIMM slots on the board */
1893 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1894 /* If a dimm is installed in a particular slot ... */
1895 if (dimm_populated[dimm_num] != SDRAM_NONE) {
1896 t_wpc_ns = max(t_wtr_ns, spd_read(iic0_dimm_addr[dimm_num], 36) >> 2);
1897 t_wtr_ns = max(t_wtr_ns, spd_read(iic0_dimm_addr[dimm_num], 37) >> 2);
1898 t_rpc_ns = max(t_rpc_ns, spd_read(iic0_dimm_addr[dimm_num], 38) >> 2);
1903 * convert from nanoseconds to ddr clocks
1904 * round up if necessary
1906 t_wpc_clk = MULDIV64(sdram_freq, t_wpc_ns, ONE_BILLION);
1907 ddr_check = MULDIV64(ONE_BILLION, t_wpc_clk, t_wpc_ns);
1908 if (sdram_freq != ddr_check)
1911 switch (t_wpc_clk) {
1915 sdtr2 |= SDRAM_SDTR2_WPC_2_CLK;
1918 sdtr2 |= SDRAM_SDTR2_WPC_3_CLK;
1921 sdtr2 |= SDRAM_SDTR2_WPC_4_CLK;
1924 sdtr2 |= SDRAM_SDTR2_WPC_5_CLK;
1927 sdtr2 |= SDRAM_SDTR2_WPC_6_CLK;
1932 * convert from nanoseconds to ddr clocks
1933 * round up if necessary
1935 t_wtr_clk = MULDIV64(sdram_freq, t_wtr_ns, ONE_BILLION);
1936 ddr_check = MULDIV64(ONE_BILLION, t_wtr_clk, t_wtr_ns);
1937 if (sdram_freq != ddr_check)
1940 switch (t_wtr_clk) {
1943 sdtr2 |= SDRAM_SDTR2_WTR_1_CLK;
1946 sdtr2 |= SDRAM_SDTR2_WTR_2_CLK;
1949 sdtr2 |= SDRAM_SDTR2_WTR_3_CLK;
1952 sdtr2 |= SDRAM_SDTR2_WTR_4_CLK;
1957 * convert from nanoseconds to ddr clocks
1958 * round up if necessary
1960 t_rpc_clk = MULDIV64(sdram_freq, t_rpc_ns, ONE_BILLION);
1961 ddr_check = MULDIV64(ONE_BILLION, t_rpc_clk, t_rpc_ns);
1962 if (sdram_freq != ddr_check)
1965 switch (t_rpc_clk) {
1969 sdtr2 |= SDRAM_SDTR2_RPC_2_CLK;
1972 sdtr2 |= SDRAM_SDTR2_RPC_3_CLK;
1975 sdtr2 |= SDRAM_SDTR2_RPC_4_CLK;
1981 sdtr2 |= SDRAM_SDTR2_XSNR_16_CLK;
1984 * convert t_rrd from nanoseconds to ddr clocks
1985 * round up if necessary
1987 t_rrd_clk = MULDIV64(sdram_freq, t_rrd_ns, ONE_BILLION);
1988 ddr_check = MULDIV64(ONE_BILLION, t_rrd_clk, t_rrd_ns);
1989 if (sdram_freq != ddr_check)
1993 sdtr2 |= SDRAM_SDTR2_RRD_3_CLK;
1995 sdtr2 |= SDRAM_SDTR2_RRD_2_CLK;
1998 * convert t_rp from nanoseconds to ddr clocks
1999 * round up if necessary
2001 t_rp_clk = MULDIV64(sdram_freq, t_rp_ns, ONE_BILLION);
2002 ddr_check = MULDIV64(ONE_BILLION, t_rp_clk, t_rp_ns);
2003 if (sdram_freq != ddr_check)
2011 sdtr2 |= SDRAM_SDTR2_RP_3_CLK;
2014 sdtr2 |= SDRAM_SDTR2_RP_4_CLK;
2017 sdtr2 |= SDRAM_SDTR2_RP_5_CLK;
2020 sdtr2 |= SDRAM_SDTR2_RP_6_CLK;
2023 sdtr2 |= SDRAM_SDTR2_RP_7_CLK;
2027 mtsdram(SDRAM_SDTR2, sdtr2);
2029 /*------------------------------------------------------------------
2030 * Set the SDRAM Timing Reg 3, SDRAM_TR3
2031 *-----------------------------------------------------------------*/
2032 mfsdram(SDRAM_SDTR3, sdtr3);
2033 sdtr3 &= ~(SDRAM_SDTR3_RAS_MASK | SDRAM_SDTR3_RC_MASK |
2034 SDRAM_SDTR3_XCS_MASK | SDRAM_SDTR3_RFC_MASK);
2037 * convert t_ras from nanoseconds to ddr clocks
2038 * round up if necessary
2040 t_ras_clk = MULDIV64(sdram_freq, t_ras_ns, ONE_BILLION);
2041 ddr_check = MULDIV64(ONE_BILLION, t_ras_clk, t_ras_ns);
2042 if (sdram_freq != ddr_check)
2045 sdtr3 |= SDRAM_SDTR3_RAS_ENCODE(t_ras_clk);
2048 * convert t_rc from nanoseconds to ddr clocks
2049 * round up if necessary
2051 t_rc_clk = MULDIV64(sdram_freq, t_rc_ns, ONE_BILLION);
2052 ddr_check = MULDIV64(ONE_BILLION, t_rc_clk, t_rc_ns);
2053 if (sdram_freq != ddr_check)
2056 sdtr3 |= SDRAM_SDTR3_RC_ENCODE(t_rc_clk);
2058 /* default xcs value */
2059 sdtr3 |= SDRAM_SDTR3_XCS;
2062 * convert t_rfc from nanoseconds to ddr clocks
2063 * round up if necessary
2065 t_rfc_clk = MULDIV64(sdram_freq, t_rfc_ns, ONE_BILLION);
2066 ddr_check = MULDIV64(ONE_BILLION, t_rfc_clk, t_rfc_ns);
2067 if (sdram_freq != ddr_check)
2070 sdtr3 |= SDRAM_SDTR3_RFC_ENCODE(t_rfc_clk);
2072 mtsdram(SDRAM_SDTR3, sdtr3);
2075 /*-----------------------------------------------------------------------------+
2077 *-----------------------------------------------------------------------------*/
2078 static void program_bxcf(unsigned long *dimm_populated,
2079 unsigned char *iic0_dimm_addr,
2080 unsigned long num_dimm_banks)
2082 unsigned long dimm_num;
2083 unsigned long num_col_addr;
2084 unsigned long num_ranks;
2085 unsigned long num_banks;
2087 unsigned long ind_rank;
2089 unsigned long ind_bank;
2090 unsigned long bank_0_populated;
2092 /*------------------------------------------------------------------
2093 * Set the BxCF regs. First, wipe out the bank config registers.
2094 *-----------------------------------------------------------------*/
2095 mtsdram(SDRAM_MB0CF, 0x00000000);
2096 mtsdram(SDRAM_MB1CF, 0x00000000);
2097 mtsdram(SDRAM_MB2CF, 0x00000000);
2098 mtsdram(SDRAM_MB3CF, 0x00000000);
2100 mode = SDRAM_BXCF_M_BE_ENABLE;
2102 bank_0_populated = 0;
2104 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
2105 if (dimm_populated[dimm_num] != SDRAM_NONE) {
2106 num_col_addr = spd_read(iic0_dimm_addr[dimm_num], 4);
2107 num_ranks = spd_read(iic0_dimm_addr[dimm_num], 5);
2108 if ((spd_read(iic0_dimm_addr[dimm_num], 2)) == 0x08)
2109 num_ranks = (num_ranks & 0x0F) +1;
2111 num_ranks = num_ranks & 0x0F;
2113 num_banks = spd_read(iic0_dimm_addr[dimm_num], 17);
2115 for (ind_bank = 0; ind_bank < 2; ind_bank++) {
2120 switch (num_col_addr) {
2122 mode |= (SDRAM_BXCF_M_AM_0 + ind);
2125 mode |= (SDRAM_BXCF_M_AM_1 + ind);
2128 mode |= (SDRAM_BXCF_M_AM_2 + ind);
2131 mode |= (SDRAM_BXCF_M_AM_3 + ind);
2134 mode |= (SDRAM_BXCF_M_AM_4 + ind);
2137 printf("DDR-SDRAM: DIMM %d BxCF configuration.\n",
2138 (unsigned int)dimm_num);
2139 printf("ERROR: Unsupported value for number of "
2140 "column addresses: %d.\n", (unsigned int)num_col_addr);
2141 printf("Replace the DIMM module with a supported DIMM.\n\n");
2142 spd_ddr_init_hang ();
2146 if ((dimm_populated[dimm_num] != SDRAM_NONE)&& (dimm_num ==1))
2147 bank_0_populated = 1;
2149 for (ind_rank = 0; ind_rank < num_ranks; ind_rank++) {
2150 mtsdram(SDRAM_MB0CF +
2151 ((dimm_num + bank_0_populated + ind_rank) << 2),
2158 /*------------------------------------------------------------------
2159 * program memory queue.
2160 *-----------------------------------------------------------------*/
2161 static void program_memory_queue(unsigned long *dimm_populated,
2162 unsigned char *iic0_dimm_addr,
2163 unsigned long num_dimm_banks)
2165 unsigned long dimm_num;
2166 phys_size_t rank_base_addr;
2167 unsigned long rank_reg;
2168 phys_size_t rank_size_bytes;
2169 unsigned long rank_size_id;
2170 unsigned long num_ranks;
2171 unsigned long baseadd_size;
2173 unsigned long bank_0_populated = 0;
2174 phys_size_t total_size = 0;
2176 /*------------------------------------------------------------------
2177 * Reset the rank_base_address.
2178 *-----------------------------------------------------------------*/
2179 rank_reg = SDRAM_R0BAS;
2181 rank_base_addr = 0x00000000;
2183 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
2184 if (dimm_populated[dimm_num] != SDRAM_NONE) {
2185 num_ranks = spd_read(iic0_dimm_addr[dimm_num], 5);
2186 if ((spd_read(iic0_dimm_addr[dimm_num], 2)) == 0x08)
2187 num_ranks = (num_ranks & 0x0F) + 1;
2189 num_ranks = num_ranks & 0x0F;
2191 rank_size_id = spd_read(iic0_dimm_addr[dimm_num], 31);
2193 /*------------------------------------------------------------------
2195 *-----------------------------------------------------------------*/
2197 switch (rank_size_id) {
2199 baseadd_size |= SDRAM_RXBAS_SDSZ_1024;
2203 baseadd_size |= SDRAM_RXBAS_SDSZ_2048;
2207 baseadd_size |= SDRAM_RXBAS_SDSZ_4096;
2211 baseadd_size |= SDRAM_RXBAS_SDSZ_32;
2215 baseadd_size |= SDRAM_RXBAS_SDSZ_64;
2219 baseadd_size |= SDRAM_RXBAS_SDSZ_128;
2223 baseadd_size |= SDRAM_RXBAS_SDSZ_256;
2227 baseadd_size |= SDRAM_RXBAS_SDSZ_512;
2231 printf("DDR-SDRAM: DIMM %d memory queue configuration.\n",
2232 (unsigned int)dimm_num);
2233 printf("ERROR: Unsupported value for the banksize: %d.\n",
2234 (unsigned int)rank_size_id);
2235 printf("Replace the DIMM module with a supported DIMM.\n\n");
2236 spd_ddr_init_hang ();
2238 rank_size_bytes = total_size << 20;
2240 if ((dimm_populated[dimm_num] != SDRAM_NONE) && (dimm_num == 1))
2241 bank_0_populated = 1;
2243 for (i = 0; i < num_ranks; i++) {
2244 mtdcr_any(rank_reg+i+dimm_num+bank_0_populated,
2245 (SDRAM_RXBAS_SDBA_ENCODE(rank_base_addr) |
2247 rank_base_addr += rank_size_bytes;
2252 #if defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
2253 defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
2254 defined(CONFIG_460SX)
2256 * Enable high bandwidth access
2257 * This is currently not used, but with this setup
2258 * it is possible to use it later on in e.g. the Linux
2259 * EMAC driver for performance gain.
2261 mtdcr(SDRAM_PLBADDULL, 0x00000000); /* MQ0_BAUL */
2262 mtdcr(SDRAM_PLBADDUHB, 0x00000008); /* MQ0_BAUH */
2265 * Set optimal value for Memory Queue HB/LL Configuration registers
2267 mtdcr(SDRAM_CONF1HB, mfdcr(SDRAM_CONF1HB) | SDRAM_CONF1HB_AAFR |
2268 SDRAM_CONF1HB_RPEN | SDRAM_CONF1HB_RFTE);
2269 mtdcr(SDRAM_CONF1LL, mfdcr(SDRAM_CONF1LL) | SDRAM_CONF1LL_AAFR |
2270 SDRAM_CONF1LL_RPEN | SDRAM_CONF1LL_RFTE);
2271 mtdcr(SDRAM_CONFPATHB, mfdcr(SDRAM_CONFPATHB) | SDRAM_CONFPATHB_TPEN);
2275 /*-----------------------------------------------------------------------------+
2277 *-----------------------------------------------------------------------------*/
2278 static unsigned long is_ecc_enabled(void)
2280 unsigned long dimm_num;
2285 /* loop through all the DIMM slots on the board */
2286 for (dimm_num = 0; dimm_num < MAXDIMMS; dimm_num++) {
2287 mfsdram(SDRAM_MCOPT1, val);
2288 ecc = max(ecc, SDRAM_MCOPT1_MCHK_CHK_DECODE(val));
2294 static void blank_string(int size)
2298 for (i=0; i<size; i++)
2300 for (i=0; i<size; i++)
2302 for (i=0; i<size; i++)
2306 #ifdef CONFIG_DDR_ECC
2307 /*-----------------------------------------------------------------------------+
2309 *-----------------------------------------------------------------------------*/
2310 static void program_ecc(unsigned long *dimm_populated,
2311 unsigned char *iic0_dimm_addr,
2312 unsigned long num_dimm_banks,
2313 unsigned long tlb_word2_i_value)
2315 unsigned long mcopt1;
2316 unsigned long mcopt2;
2317 unsigned long mcstat;
2318 unsigned long dimm_num;
2322 /* loop through all the DIMM slots on the board */
2323 for (dimm_num = 0; dimm_num < MAXDIMMS; dimm_num++) {
2324 /* If a dimm is installed in a particular slot ... */
2325 if (dimm_populated[dimm_num] != SDRAM_NONE)
2326 ecc = max(ecc, spd_read(iic0_dimm_addr[dimm_num], 11));
2331 if (sdram_memsize() > CONFIG_MAX_MEM_MAPPED) {
2332 printf("\nWarning: Can't enable ECC on systems with more than 2GB of SDRAM!\n");
2336 mfsdram(SDRAM_MCOPT1, mcopt1);
2337 mfsdram(SDRAM_MCOPT2, mcopt2);
2339 if ((mcopt1 & SDRAM_MCOPT1_MCHK_MASK) != SDRAM_MCOPT1_MCHK_NON) {
2340 /* DDR controller must be enabled and not in self-refresh. */
2341 mfsdram(SDRAM_MCSTAT, mcstat);
2342 if (((mcopt2 & SDRAM_MCOPT2_DCEN_MASK) == SDRAM_MCOPT2_DCEN_ENABLE)
2343 && ((mcopt2 & SDRAM_MCOPT2_SREN_MASK) == SDRAM_MCOPT2_SREN_EXIT)
2344 && ((mcstat & (SDRAM_MCSTAT_MIC_MASK | SDRAM_MCSTAT_SRMS_MASK))
2345 == (SDRAM_MCSTAT_MIC_COMP | SDRAM_MCSTAT_SRMS_NOT_SF))) {
2347 program_ecc_addr(0, sdram_memsize(), tlb_word2_i_value);
2354 static void wait_ddr_idle(void)
2359 mfsdram(SDRAM_MCSTAT, val);
2360 } while ((val & SDRAM_MCSTAT_IDLE_MASK) == SDRAM_MCSTAT_IDLE_NOT);
2363 /*-----------------------------------------------------------------------------+
2365 *-----------------------------------------------------------------------------*/
2366 static void program_ecc_addr(unsigned long start_address,
2367 unsigned long num_bytes,
2368 unsigned long tlb_word2_i_value)
2370 unsigned long current_address;
2371 unsigned long end_address;
2372 unsigned long address_increment;
2373 unsigned long mcopt1;
2374 char str[] = "ECC generation -";
2375 char slash[] = "\\|/-\\|/-";
2379 current_address = start_address;
2380 mfsdram(SDRAM_MCOPT1, mcopt1);
2381 if ((mcopt1 & SDRAM_MCOPT1_MCHK_MASK) != SDRAM_MCOPT1_MCHK_NON) {
2382 mtsdram(SDRAM_MCOPT1,
2383 (mcopt1 & ~SDRAM_MCOPT1_MCHK_MASK) | SDRAM_MCOPT1_MCHK_GEN);
2389 if (tlb_word2_i_value == TLB_WORD2_I_ENABLE) {
2390 /* ECC bit set method for non-cached memory */
2391 if ((mcopt1 & SDRAM_MCOPT1_DMWD_MASK) == SDRAM_MCOPT1_DMWD_32)
2392 address_increment = 4;
2394 address_increment = 8;
2395 end_address = current_address + num_bytes;
2397 while (current_address < end_address) {
2398 *((unsigned long *)current_address) = 0x00000000;
2399 current_address += address_increment;
2401 if ((loop++ % (2 << 20)) == 0) {
2403 putc(slash[loopi++ % 8]);
2408 /* ECC bit set method for cached memory */
2409 dcbz_area(start_address, num_bytes);
2410 /* Write modified dcache lines back to memory */
2411 clean_dcache_range(start_address, start_address + num_bytes);
2414 blank_string(strlen(str));
2420 /* clear ECC error repoting registers */
2421 mtsdram(SDRAM_ECCCR, 0xffffffff);
2422 mtdcr(0x4c, 0xffffffff);
2424 mtsdram(SDRAM_MCOPT1,
2425 (mcopt1 & ~SDRAM_MCOPT1_MCHK_MASK) | SDRAM_MCOPT1_MCHK_CHK_REP);
2433 /*-----------------------------------------------------------------------------+
2434 * program_DQS_calibration.
2435 *-----------------------------------------------------------------------------*/
2436 static void program_DQS_calibration(unsigned long *dimm_populated,
2437 unsigned char *iic0_dimm_addr,
2438 unsigned long num_dimm_banks)
2442 #ifdef HARD_CODED_DQS /* calibration test with hardvalues */
2443 mtsdram(SDRAM_RQDC, 0x80000037);
2444 mtsdram(SDRAM_RDCC, 0x40000000);
2445 mtsdram(SDRAM_RFDC, 0x000001DF);
2449 /*------------------------------------------------------------------
2450 * Program RDCC register
2451 * Read sample cycle auto-update enable
2452 *-----------------------------------------------------------------*/
2454 mfsdram(SDRAM_RDCC, val);
2456 (val & ~(SDRAM_RDCC_RDSS_MASK | SDRAM_RDCC_RSAE_MASK))
2457 | SDRAM_RDCC_RSAE_ENABLE);
2459 /*------------------------------------------------------------------
2460 * Program RQDC register
2461 * Internal DQS delay mechanism enable
2462 *-----------------------------------------------------------------*/
2463 mtsdram(SDRAM_RQDC, (SDRAM_RQDC_RQDE_ENABLE|SDRAM_RQDC_RQFD_ENCODE(0x38)));
2465 /*------------------------------------------------------------------
2466 * Program RFDC register
2467 * Set Feedback Fractional Oversample
2468 * Auto-detect read sample cycle enable
2469 *-----------------------------------------------------------------*/
2470 mfsdram(SDRAM_RFDC, val);
2472 (val & ~(SDRAM_RFDC_ARSE_MASK | SDRAM_RFDC_RFOS_MASK |
2473 SDRAM_RFDC_RFFD_MASK))
2474 | (SDRAM_RFDC_ARSE_ENABLE | SDRAM_RFDC_RFOS_ENCODE(0) |
2475 SDRAM_RFDC_RFFD_ENCODE(0)));
2477 DQS_calibration_process();
2481 static int short_mem_test(void)
2488 phys_size_t base_addr;
2489 u32 test[NUMMEMTESTS][NUMMEMWORDS] = {
2490 {0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
2491 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF},
2492 {0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
2493 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000},
2494 {0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
2495 0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555},
2496 {0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
2497 0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA},
2498 {0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
2499 0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A},
2500 {0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
2501 0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5},
2502 {0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
2503 0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA},
2504 {0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
2505 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55} };
2508 for (bxcr_num = 0; bxcr_num < MAXBXCF; bxcr_num++) {
2509 mfsdram(SDRAM_MB0CF + (bxcr_num << 2), bxcf);
2512 if ((bxcf & SDRAM_BXCF_M_BE_MASK) == SDRAM_BXCF_M_BE_ENABLE) {
2513 /* Bank is enabled */
2516 * Only run test on accessable memory (below 2GB)
2518 base_addr = SDRAM_RXBAS_SDBA_DECODE(mfdcr_any(SDRAM_R0BAS+bxcr_num));
2519 if (base_addr >= CONFIG_MAX_MEM_MAPPED)
2522 /*------------------------------------------------------------------
2523 * Run the short memory test.
2524 *-----------------------------------------------------------------*/
2525 membase = (u32 *)(u32)base_addr;
2527 for (i = 0; i < NUMMEMTESTS; i++) {
2528 for (j = 0; j < NUMMEMWORDS; j++) {
2529 membase[j] = test[i][j];
2530 ppcDcbf((u32)&(membase[j]));
2533 for (l=0; l<NUMLOOPS; l++) {
2534 for (j = 0; j < NUMMEMWORDS; j++) {
2535 if (membase[j] != test[i][j]) {
2536 ppcDcbf((u32)&(membase[j]));
2539 ppcDcbf((u32)&(membase[j]));
2544 } /* if bank enabled */
2545 } /* for bxcf_num */
2550 #ifndef HARD_CODED_DQS
2551 /*-----------------------------------------------------------------------------+
2552 * DQS_calibration_process.
2553 *-----------------------------------------------------------------------------*/
2554 static void DQS_calibration_process(void)
2556 unsigned long rfdc_reg;
2562 unsigned long begin_rqfd[MAXRANKS];
2563 unsigned long begin_rffd[MAXRANKS];
2564 unsigned long end_rqfd[MAXRANKS];
2565 unsigned long end_rffd[MAXRANKS];
2567 unsigned long dlycal;
2568 unsigned long dly_val;
2569 unsigned long max_pass_length;
2570 unsigned long current_pass_length;
2571 unsigned long current_fail_length;
2572 unsigned long current_start;
2574 unsigned char fail_found;
2575 unsigned char pass_found;
2576 #if !defined(CONFIG_DDR_RQDC_FIXED)
2582 char str[] = "Auto calibration -";
2583 char slash[] = "\\|/-\\|/-";
2585 /*------------------------------------------------------------------
2586 * Test to determine the best read clock delay tuning bits.
2588 * Before the DDR controller can be used, the read clock delay needs to be
2589 * set. This is SDRAM_RQDC[RQFD] and SDRAM_RFDC[RFFD].
2590 * This value cannot be hardcoded into the program because it changes
2591 * depending on the board's setup and environment.
2592 * To do this, all delay values are tested to see if they
2593 * work or not. By doing this, you get groups of fails with groups of
2594 * passing values. The idea is to find the start and end of a passing
2595 * window and take the center of it to use as the read clock delay.
2597 * A failure has to be seen first so that when we hit a pass, we know
2598 * that it is truely the start of the window. If we get passing values
2599 * to start off with, we don't know if we are at the start of the window.
2601 * The code assumes that a failure will always be found.
2602 * If a failure is not found, there is no easy way to get the middle
2603 * of the passing window. I guess we can pretty much pick any value
2604 * but some values will be better than others. Since the lowest speed
2605 * we can clock the DDR interface at is 200 MHz (2x 100 MHz PLB speed),
2606 * from experimentation it is safe to say you will always have a failure.
2607 *-----------------------------------------------------------------*/
2609 /* first fix RQDC[RQFD] to an average of 80 degre phase shift to find RFDC[RFFD] */
2610 rqfd_start = 64; /* test-only: don't know if this is the _best_ start value */
2615 mfsdram(SDRAM_RQDC, rqdc_reg);
2616 mtsdram(SDRAM_RQDC, (rqdc_reg & ~SDRAM_RQDC_RQFD_MASK) |
2617 SDRAM_RQDC_RQFD_ENCODE(rqfd_start));
2618 #else /* CONFIG_DDR_RQDC_FIXED */
2620 * On Katmai the complete auto-calibration somehow doesn't seem to
2621 * produce the best results, meaning optimal values for RQFD/RFFD.
2622 * This was discovered by GDA using a high bandwidth scope,
2623 * analyzing the DDR2 signals. GDA provided a fixed value for RQFD,
2624 * so now on Katmai "only" RFFD is auto-calibrated.
2626 mtsdram(SDRAM_RQDC, CONFIG_DDR_RQDC_FIXED);
2627 #endif /* CONFIG_DDR_RQDC_FIXED */
2639 window_found = FALSE;
2641 max_pass_length = 0;
2644 current_pass_length = 0;
2645 current_fail_length = 0;
2647 window_found = FALSE;
2652 * get the delay line calibration register value
2654 mfsdram(SDRAM_DLCR, dlycal);
2655 dly_val = SDRAM_DLYCAL_DLCV_DECODE(dlycal) << 2;
2657 for (rffd = 0; rffd <= SDRAM_RFDC_RFFD_MAX; rffd++) {
2658 mfsdram(SDRAM_RFDC, rfdc_reg);
2659 rfdc_reg &= ~(SDRAM_RFDC_RFFD_MASK);
2661 /*------------------------------------------------------------------
2662 * Set the timing reg for the test.
2663 *-----------------------------------------------------------------*/
2664 mtsdram(SDRAM_RFDC, rfdc_reg | SDRAM_RFDC_RFFD_ENCODE(rffd));
2666 /*------------------------------------------------------------------
2667 * See if the rffd value passed.
2668 *-----------------------------------------------------------------*/
2669 if (short_mem_test()) {
2670 if (fail_found == TRUE) {
2672 if (current_pass_length == 0)
2673 current_start = rffd;
2675 current_fail_length = 0;
2676 current_pass_length++;
2678 if (current_pass_length > max_pass_length) {
2679 max_pass_length = current_pass_length;
2680 max_start = current_start;
2685 current_pass_length = 0;
2686 current_fail_length++;
2688 if (current_fail_length >= (dly_val >> 2)) {
2689 if (fail_found == FALSE) {
2691 } else if (pass_found == TRUE) {
2692 window_found = TRUE;
2699 /*------------------------------------------------------------------
2700 * Set the average RFFD value
2701 *-----------------------------------------------------------------*/
2702 rffd_average = ((max_start + max_end) >> 1);
2704 if (rffd_average < 0)
2707 if (rffd_average > SDRAM_RFDC_RFFD_MAX)
2708 rffd_average = SDRAM_RFDC_RFFD_MAX;
2709 /* now fix RFDC[RFFD] found and find RQDC[RQFD] */
2710 mtsdram(SDRAM_RFDC, rfdc_reg | SDRAM_RFDC_RFFD_ENCODE(rffd_average));
2712 #if !defined(CONFIG_DDR_RQDC_FIXED)
2713 max_pass_length = 0;
2716 current_pass_length = 0;
2717 current_fail_length = 0;
2719 window_found = FALSE;
2723 for (rqfd = 0; rqfd <= SDRAM_RQDC_RQFD_MAX; rqfd++) {
2724 mfsdram(SDRAM_RQDC, rqdc_reg);
2725 rqdc_reg &= ~(SDRAM_RQDC_RQFD_MASK);
2727 /*------------------------------------------------------------------
2728 * Set the timing reg for the test.
2729 *-----------------------------------------------------------------*/
2730 mtsdram(SDRAM_RQDC, rqdc_reg | SDRAM_RQDC_RQFD_ENCODE(rqfd));
2732 /*------------------------------------------------------------------
2733 * See if the rffd value passed.
2734 *-----------------------------------------------------------------*/
2735 if (short_mem_test()) {
2736 if (fail_found == TRUE) {
2738 if (current_pass_length == 0)
2739 current_start = rqfd;
2741 current_fail_length = 0;
2742 current_pass_length++;
2744 if (current_pass_length > max_pass_length) {
2745 max_pass_length = current_pass_length;
2746 max_start = current_start;
2751 current_pass_length = 0;
2752 current_fail_length++;
2754 if (fail_found == FALSE) {
2756 } else if (pass_found == TRUE) {
2757 window_found = TRUE;
2763 rqfd_average = ((max_start + max_end) >> 1);
2765 /*------------------------------------------------------------------
2766 * Make sure we found the valid read passing window. Halt if not
2767 *-----------------------------------------------------------------*/
2768 if (window_found == FALSE) {
2769 if (rqfd_start < SDRAM_RQDC_RQFD_MAX) {
2771 putc(slash[loopi++ % 8]);
2773 /* try again from with a different RQFD start value */
2775 goto calibration_loop;
2778 printf("\nERROR: Cannot determine a common read delay for the "
2779 "DIMM(s) installed.\n");
2780 debug("%s[%d] ERROR : \n", __FUNCTION__,__LINE__);
2781 ppc4xx_ibm_ddr2_register_dump();
2782 spd_ddr_init_hang ();
2785 if (rqfd_average < 0)
2788 if (rqfd_average > SDRAM_RQDC_RQFD_MAX)
2789 rqfd_average = SDRAM_RQDC_RQFD_MAX;
2792 (rqdc_reg & ~SDRAM_RQDC_RQFD_MASK) |
2793 SDRAM_RQDC_RQFD_ENCODE(rqfd_average));
2795 blank_string(strlen(str));
2796 #endif /* CONFIG_DDR_RQDC_FIXED */
2799 * Now complete RDSS configuration as mentioned on page 7 of the AMCC
2800 * PowerPC440SP/SPe DDR2 application note:
2801 * "DDR1/DDR2 Initialization Sequence and Dynamic Tuning"
2803 mfsdram(SDRAM_RTSR, val);
2804 if ((val & SDRAM_RTSR_TRK1SM_MASK) == SDRAM_RTSR_TRK1SM_ATPLS1) {
2805 mfsdram(SDRAM_RDCC, val);
2806 if ((val & SDRAM_RDCC_RDSS_MASK) != SDRAM_RDCC_RDSS_T4) {
2808 mtsdram(SDRAM_RDCC, val);
2812 mfsdram(SDRAM_DLCR, val);
2813 debug("%s[%d] DLCR: 0x%08X\n", __FUNCTION__, __LINE__, val);
2814 mfsdram(SDRAM_RQDC, val);
2815 debug("%s[%d] RQDC: 0x%08X\n", __FUNCTION__, __LINE__, val);
2816 mfsdram(SDRAM_RFDC, val);
2817 debug("%s[%d] RFDC: 0x%08X\n", __FUNCTION__, __LINE__, val);
2818 mfsdram(SDRAM_RDCC, val);
2819 debug("%s[%d] RDCC: 0x%08X\n", __FUNCTION__, __LINE__, val);
2821 #else /* calibration test with hardvalues */
2822 /*-----------------------------------------------------------------------------+
2823 * DQS_calibration_process.
2824 *-----------------------------------------------------------------------------*/
2825 static void test(void)
2827 unsigned long dimm_num;
2828 unsigned long ecc_temp;
2830 unsigned long *membase;
2831 unsigned long bxcf[MAXRANKS];
2834 char begin_found[MAXDIMMS];
2835 char end_found[MAXDIMMS];
2836 char search_end[MAXDIMMS];
2837 unsigned long test[NUMMEMTESTS][NUMMEMWORDS] = {
2838 {0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
2839 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF},
2840 {0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
2841 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000},
2842 {0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
2843 0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555},
2844 {0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
2845 0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA},
2846 {0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
2847 0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A},
2848 {0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
2849 0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5},
2850 {0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
2851 0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA},
2852 {0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
2853 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55} };
2855 /*------------------------------------------------------------------
2856 * Test to determine the best read clock delay tuning bits.
2858 * Before the DDR controller can be used, the read clock delay needs to be
2859 * set. This is SDRAM_RQDC[RQFD] and SDRAM_RFDC[RFFD].
2860 * This value cannot be hardcoded into the program because it changes
2861 * depending on the board's setup and environment.
2862 * To do this, all delay values are tested to see if they
2863 * work or not. By doing this, you get groups of fails with groups of
2864 * passing values. The idea is to find the start and end of a passing
2865 * window and take the center of it to use as the read clock delay.
2867 * A failure has to be seen first so that when we hit a pass, we know
2868 * that it is truely the start of the window. If we get passing values
2869 * to start off with, we don't know if we are at the start of the window.
2871 * The code assumes that a failure will always be found.
2872 * If a failure is not found, there is no easy way to get the middle
2873 * of the passing window. I guess we can pretty much pick any value
2874 * but some values will be better than others. Since the lowest speed
2875 * we can clock the DDR interface at is 200 MHz (2x 100 MHz PLB speed),
2876 * from experimentation it is safe to say you will always have a failure.
2877 *-----------------------------------------------------------------*/
2878 mfsdram(SDRAM_MCOPT1, ecc_temp);
2879 ecc_temp &= SDRAM_MCOPT1_MCHK_MASK;
2880 mfsdram(SDRAM_MCOPT1, val);
2881 mtsdram(SDRAM_MCOPT1, (val & ~SDRAM_MCOPT1_MCHK_MASK) |
2882 SDRAM_MCOPT1_MCHK_NON);
2884 window_found = FALSE;
2885 begin_found[0] = FALSE;
2886 end_found[0] = FALSE;
2887 search_end[0] = FALSE;
2888 begin_found[1] = FALSE;
2889 end_found[1] = FALSE;
2890 search_end[1] = FALSE;
2892 for (dimm_num = 0; dimm_num < MAXDIMMS; dimm_num++) {
2893 mfsdram(SDRAM_MB0CF + (bxcr_num << 2), bxcf[bxcr_num]);
2896 if ((bxcf[dimm_num] & SDRAM_BXCF_M_BE_MASK) == SDRAM_BXCF_M_BE_ENABLE) {
2898 /* Bank is enabled */
2900 (unsigned long*)(SDRAM_RXBAS_SDBA_DECODE(mfdcr_any(SDRAM_R0BAS+dimm_num)));
2902 /*------------------------------------------------------------------
2903 * Run the short memory test.
2904 *-----------------------------------------------------------------*/
2905 for (i = 0; i < NUMMEMTESTS; i++) {
2906 for (j = 0; j < NUMMEMWORDS; j++) {
2907 membase[j] = test[i][j];
2908 ppcDcbf((u32)&(membase[j]));
2911 for (j = 0; j < NUMMEMWORDS; j++) {
2912 if (membase[j] != test[i][j]) {
2913 ppcDcbf((u32)&(membase[j]));
2916 ppcDcbf((u32)&(membase[j]));
2919 if (j < NUMMEMWORDS)
2923 /*------------------------------------------------------------------
2924 * See if the rffd value passed.
2925 *-----------------------------------------------------------------*/
2926 if (i < NUMMEMTESTS) {
2927 if ((end_found[dimm_num] == FALSE) &&
2928 (search_end[dimm_num] == TRUE)) {
2929 end_found[dimm_num] = TRUE;
2931 if ((end_found[0] == TRUE) &&
2932 (end_found[1] == TRUE))
2935 if (begin_found[dimm_num] == FALSE) {
2936 begin_found[dimm_num] = TRUE;
2937 search_end[dimm_num] = TRUE;
2941 begin_found[dimm_num] = TRUE;
2942 end_found[dimm_num] = TRUE;
2946 if ((begin_found[0] == TRUE) && (begin_found[1] == TRUE))
2947 window_found = TRUE;
2949 /*------------------------------------------------------------------
2950 * Make sure we found the valid read passing window. Halt if not
2951 *-----------------------------------------------------------------*/
2952 if (window_found == FALSE) {
2953 printf("ERROR: Cannot determine a common read delay for the "
2954 "DIMM(s) installed.\n");
2955 spd_ddr_init_hang ();
2958 /*------------------------------------------------------------------
2959 * Restore the ECC variable to what it originally was
2960 *-----------------------------------------------------------------*/
2961 mtsdram(SDRAM_MCOPT1,
2962 (ppcMfdcr_sdram(SDRAM_MCOPT1) & ~SDRAM_MCOPT1_MCHK_MASK)
2967 #else /* CONFIG_SPD_EEPROM */
2969 /*-----------------------------------------------------------------------------
2970 * Function: initdram
2971 * Description: Configures the PPC405EX(r) DDR1/DDR2 SDRAM memory
2972 * banks. The configuration is performed using static, compile-
2974 *---------------------------------------------------------------------------*/
2975 phys_size_t initdram(int board_type)
2978 * Only run this SDRAM init code once. For NAND booting
2979 * targets like Kilauea, we call initdram() early from the
2980 * 4k NAND booting image (CONFIG_NAND_SPL) from nand_boot().
2981 * Later on the NAND U-Boot image runs (CONFIG_NAND_U_BOOT)
2982 * which calls initdram() again. This time the controller
2983 * mustn't be reconfigured again since we're already running
2986 #if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
2989 /* Set Memory Bank Configuration Registers */
2991 mtsdram(SDRAM_MB0CF, CFG_SDRAM0_MB0CF);
2992 mtsdram(SDRAM_MB1CF, CFG_SDRAM0_MB1CF);
2993 mtsdram(SDRAM_MB2CF, CFG_SDRAM0_MB2CF);
2994 mtsdram(SDRAM_MB3CF, CFG_SDRAM0_MB3CF);
2996 /* Set Memory Clock Timing Register */
2998 mtsdram(SDRAM_CLKTR, CFG_SDRAM0_CLKTR);
3000 /* Set Refresh Time Register */
3002 mtsdram(SDRAM_RTR, CFG_SDRAM0_RTR);
3004 /* Set SDRAM Timing Registers */
3006 mtsdram(SDRAM_SDTR1, CFG_SDRAM0_SDTR1);
3007 mtsdram(SDRAM_SDTR2, CFG_SDRAM0_SDTR2);
3008 mtsdram(SDRAM_SDTR3, CFG_SDRAM0_SDTR3);
3010 /* Set Mode and Extended Mode Registers */
3012 mtsdram(SDRAM_MMODE, CFG_SDRAM0_MMODE);
3013 mtsdram(SDRAM_MEMODE, CFG_SDRAM0_MEMODE);
3015 /* Set Memory Controller Options 1 Register */
3017 mtsdram(SDRAM_MCOPT1, CFG_SDRAM0_MCOPT1);
3019 /* Set Manual Initialization Control Registers */
3021 mtsdram(SDRAM_INITPLR0, CFG_SDRAM0_INITPLR0);
3022 mtsdram(SDRAM_INITPLR1, CFG_SDRAM0_INITPLR1);
3023 mtsdram(SDRAM_INITPLR2, CFG_SDRAM0_INITPLR2);
3024 mtsdram(SDRAM_INITPLR3, CFG_SDRAM0_INITPLR3);
3025 mtsdram(SDRAM_INITPLR4, CFG_SDRAM0_INITPLR4);
3026 mtsdram(SDRAM_INITPLR5, CFG_SDRAM0_INITPLR5);
3027 mtsdram(SDRAM_INITPLR6, CFG_SDRAM0_INITPLR6);
3028 mtsdram(SDRAM_INITPLR7, CFG_SDRAM0_INITPLR7);
3029 mtsdram(SDRAM_INITPLR8, CFG_SDRAM0_INITPLR8);
3030 mtsdram(SDRAM_INITPLR9, CFG_SDRAM0_INITPLR9);
3031 mtsdram(SDRAM_INITPLR10, CFG_SDRAM0_INITPLR10);
3032 mtsdram(SDRAM_INITPLR11, CFG_SDRAM0_INITPLR11);
3033 mtsdram(SDRAM_INITPLR12, CFG_SDRAM0_INITPLR12);
3034 mtsdram(SDRAM_INITPLR13, CFG_SDRAM0_INITPLR13);
3035 mtsdram(SDRAM_INITPLR14, CFG_SDRAM0_INITPLR14);
3036 mtsdram(SDRAM_INITPLR15, CFG_SDRAM0_INITPLR15);
3038 /* Set On-Die Termination Registers */
3040 mtsdram(SDRAM_CODT, CFG_SDRAM0_CODT);
3041 mtsdram(SDRAM_MODT0, CFG_SDRAM0_MODT0);
3042 mtsdram(SDRAM_MODT1, CFG_SDRAM0_MODT1);
3044 /* Set Write Timing Register */
3046 mtsdram(SDRAM_WRDTR, CFG_SDRAM0_WRDTR);
3049 * Start Initialization by SDRAM0_MCOPT2[SREN] = 0 and
3050 * SDRAM0_MCOPT2[IPTR] = 1
3053 mtsdram(SDRAM_MCOPT2, (SDRAM_MCOPT2_SREN_EXIT |
3054 SDRAM_MCOPT2_IPTR_EXECUTE));
3057 * Poll SDRAM0_MCSTAT[MIC] for assertion to indicate the
3058 * completion of initialization.
3062 mfsdram(SDRAM_MCSTAT, val);
3063 } while ((val & SDRAM_MCSTAT_MIC_MASK) != SDRAM_MCSTAT_MIC_COMP);
3065 /* Set Delay Control Registers */
3067 mtsdram(SDRAM_DLCR, CFG_SDRAM0_DLCR);
3068 mtsdram(SDRAM_RDCC, CFG_SDRAM0_RDCC);
3069 mtsdram(SDRAM_RQDC, CFG_SDRAM0_RQDC);
3070 mtsdram(SDRAM_RFDC, CFG_SDRAM0_RFDC);
3073 * Enable Controller by SDRAM0_MCOPT2[DCEN] = 1:
3076 mfsdram(SDRAM_MCOPT2, val);
3077 mtsdram(SDRAM_MCOPT2, val | SDRAM_MCOPT2_DCEN_ENABLE);
3079 #if defined(CONFIG_DDR_ECC)
3080 ecc_init(CFG_SDRAM_BASE, CFG_MBYTES_SDRAM << 20);
3081 #endif /* defined(CONFIG_DDR_ECC) */
3083 ppc4xx_ibm_ddr2_register_dump();
3084 #endif /* !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) */
3086 return (CFG_MBYTES_SDRAM << 20);
3088 #endif /* CONFIG_SPD_EEPROM */
3090 static inline void ppc4xx_ibm_ddr2_register_dump(void)
3093 printf("\nPPC4xx IBM DDR2 Register Dump:\n");
3095 #if (defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
3096 defined(CONFIG_460EX) || defined(CONFIG_460GT))
3097 PPC4xx_IBM_DDR2_DUMP_REGISTER(R0BAS);
3098 PPC4xx_IBM_DDR2_DUMP_REGISTER(R1BAS);
3099 PPC4xx_IBM_DDR2_DUMP_REGISTER(R2BAS);
3100 PPC4xx_IBM_DDR2_DUMP_REGISTER(R3BAS);
3101 #endif /* (defined(CONFIG_440SP) || ... */
3102 #if defined(CONFIG_405EX)
3103 PPC4xx_IBM_DDR2_DUMP_REGISTER(BESR);
3104 PPC4xx_IBM_DDR2_DUMP_REGISTER(BEARL);
3105 PPC4xx_IBM_DDR2_DUMP_REGISTER(BEARH);
3106 PPC4xx_IBM_DDR2_DUMP_REGISTER(WMIRQ);
3107 PPC4xx_IBM_DDR2_DUMP_REGISTER(PLBOPT);
3108 PPC4xx_IBM_DDR2_DUMP_REGISTER(PUABA);
3109 #endif /* defined(CONFIG_405EX) */
3110 PPC4xx_IBM_DDR2_DUMP_REGISTER(MB0CF);
3111 PPC4xx_IBM_DDR2_DUMP_REGISTER(MB1CF);
3112 PPC4xx_IBM_DDR2_DUMP_REGISTER(MB2CF);
3113 PPC4xx_IBM_DDR2_DUMP_REGISTER(MB3CF);
3114 PPC4xx_IBM_DDR2_DUMP_REGISTER(MCSTAT);
3115 PPC4xx_IBM_DDR2_DUMP_REGISTER(MCOPT1);
3116 PPC4xx_IBM_DDR2_DUMP_REGISTER(MCOPT2);
3117 PPC4xx_IBM_DDR2_DUMP_REGISTER(MODT0);
3118 PPC4xx_IBM_DDR2_DUMP_REGISTER(MODT1);
3119 PPC4xx_IBM_DDR2_DUMP_REGISTER(MODT2);
3120 PPC4xx_IBM_DDR2_DUMP_REGISTER(MODT3);
3121 PPC4xx_IBM_DDR2_DUMP_REGISTER(CODT);
3122 #if (defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
3123 defined(CONFIG_460EX) || defined(CONFIG_460GT))
3124 PPC4xx_IBM_DDR2_DUMP_REGISTER(VVPR);
3125 PPC4xx_IBM_DDR2_DUMP_REGISTER(OPARS);
3127 * OPART is only used as a trigger register.
3129 * No data is contained in this register, and reading or writing
3130 * to is can cause bad things to happen (hangs). Just skip it and
3133 printf("%20s = N/A\n", "SDRAM_OPART");
3134 #endif /* defined(CONFIG_440SP) || ... */
3135 PPC4xx_IBM_DDR2_DUMP_REGISTER(RTR);
3136 PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR0);
3137 PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR1);
3138 PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR2);
3139 PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR3);
3140 PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR4);
3141 PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR5);
3142 PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR6);
3143 PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR7);
3144 PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR8);
3145 PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR9);
3146 PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR10);
3147 PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR11);
3148 PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR12);
3149 PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR13);
3150 PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR14);
3151 PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR15);
3152 PPC4xx_IBM_DDR2_DUMP_REGISTER(RQDC);
3153 PPC4xx_IBM_DDR2_DUMP_REGISTER(RFDC);
3154 PPC4xx_IBM_DDR2_DUMP_REGISTER(RDCC);
3155 PPC4xx_IBM_DDR2_DUMP_REGISTER(DLCR);
3156 PPC4xx_IBM_DDR2_DUMP_REGISTER(CLKTR);
3157 PPC4xx_IBM_DDR2_DUMP_REGISTER(WRDTR);
3158 PPC4xx_IBM_DDR2_DUMP_REGISTER(SDTR1);
3159 PPC4xx_IBM_DDR2_DUMP_REGISTER(SDTR2);
3160 PPC4xx_IBM_DDR2_DUMP_REGISTER(SDTR3);
3161 PPC4xx_IBM_DDR2_DUMP_REGISTER(MMODE);
3162 PPC4xx_IBM_DDR2_DUMP_REGISTER(MEMODE);
3163 PPC4xx_IBM_DDR2_DUMP_REGISTER(ECCCR);
3164 #if (defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
3165 defined(CONFIG_460EX) || defined(CONFIG_460GT))
3166 PPC4xx_IBM_DDR2_DUMP_REGISTER(CID);
3167 #endif /* defined(CONFIG_440SP) || ... */
3168 PPC4xx_IBM_DDR2_DUMP_REGISTER(RID);
3169 PPC4xx_IBM_DDR2_DUMP_REGISTER(FCSR);
3170 PPC4xx_IBM_DDR2_DUMP_REGISTER(RTSR);
3171 #endif /* defined(DEBUG) */
3174 #endif /* CONFIG_SDRAM_PPC4xx_IBM_DDR2 */