2 * cpu/ppc4xx/44x_spd_ddr2.c
3 * This SPD SDRAM detection code supports AMCC PPC44x cpu's with a
4 * DDR2 controller (non Denali Core). Those currently are:
7 * 440/460: 440SP/440SPe/460EX/460GT
9 * Copyright (c) 2008 Nuovation System Designs, LLC
10 * Grant Erickson <gerickson@nuovations.com>
12 * (C) Copyright 2007-2008
13 * Stefan Roese, DENX Software Engineering, sr@denx.de.
15 * COPYRIGHT AMCC CORPORATION 2004
17 * See file CREDITS for list of people who contributed to this
20 * This program is free software; you can redistribute it and/or
21 * modify it under the terms of the GNU General Public License as
22 * published by the Free Software Foundation; either version 2 of
23 * the License, or (at your option) any later version.
25 * This program is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU General Public License for more details.
30 * You should have received a copy of the GNU General Public License
31 * along with this program; if not, write to the Free Software
32 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
37 /* define DEBUG for debugging output (obviously ;-)) */
47 #include <asm/processor.h>
49 #include <asm/cache.h>
53 #if defined(CONFIG_SDRAM_PPC4xx_IBM_DDR2)
55 #define PPC4xx_IBM_DDR2_DUMP_REGISTER(mnemonic) \
58 mfsdram(SDRAM_##mnemonic, data); \
59 printf("%20s[%02x] = 0x%08X\n", \
60 "SDRAM_" #mnemonic, SDRAM_##mnemonic, data); \
63 #if defined(CONFIG_440)
65 * This DDR2 setup code can dynamically setup the TLB entries for the DDR2
66 * memory region. Right now the cache should still be disabled in U-Boot
67 * because of the EMAC driver, that need its buffer descriptor to be located
68 * in non cached memory.
70 * If at some time this restriction doesn't apply anymore, just define
71 * CONFIG_4xx_DCACHE in the board config file and this code should setup
72 * everything correctly.
74 #ifdef CONFIG_4xx_DCACHE
75 /* enable caching on SDRAM */
76 #define MY_TLB_WORD2_I_ENABLE 0
78 /* disable caching on SDRAM */
79 #define MY_TLB_WORD2_I_ENABLE TLB_WORD2_I_ENABLE
80 #endif /* CONFIG_4xx_DCACHE */
81 #endif /* CONFIG_440 */
83 #if defined(CONFIG_SPD_EEPROM)
85 /*-----------------------------------------------------------------------------+
87 *-----------------------------------------------------------------------------*/
102 #define MAX_SPD_BYTES 256 /* Max number of bytes on the DIMM's SPD EEPROM */
104 #define ONE_BILLION 1000000000
106 #define MULDIV64(m1, m2, d) (u32)(((u64)(m1) * (u64)(m2)) / (u64)(d))
108 #define CMD_NOP (7 << 19)
109 #define CMD_PRECHARGE (2 << 19)
110 #define CMD_REFRESH (1 << 19)
111 #define CMD_EMR (0 << 19)
112 #define CMD_READ (5 << 19)
113 #define CMD_WRITE (4 << 19)
115 #define SELECT_MR (0 << 16)
116 #define SELECT_EMR (1 << 16)
117 #define SELECT_EMR2 (2 << 16)
118 #define SELECT_EMR3 (3 << 16)
121 #define DLL_RESET 0x00000100
123 #define WRITE_RECOV_2 (1 << 9)
124 #define WRITE_RECOV_3 (2 << 9)
125 #define WRITE_RECOV_4 (3 << 9)
126 #define WRITE_RECOV_5 (4 << 9)
127 #define WRITE_RECOV_6 (5 << 9)
129 #define BURST_LEN_4 0x00000002
132 #define ODT_0_OHM 0x00000000
133 #define ODT_50_OHM 0x00000044
134 #define ODT_75_OHM 0x00000004
135 #define ODT_150_OHM 0x00000040
137 #define ODS_FULL 0x00000000
138 #define ODS_REDUCED 0x00000002
139 #define OCD_CALIB_DEF 0x00000380
141 /* defines for ODT (On Die Termination) of the 440SP(e) DDR2 controller */
142 #define ODT_EB0R (0x80000000 >> 8)
143 #define ODT_EB0W (0x80000000 >> 7)
144 #define CALC_ODT_R(n) (ODT_EB0R << (n << 1))
145 #define CALC_ODT_W(n) (ODT_EB0W << (n << 1))
146 #define CALC_ODT_RW(n) (CALC_ODT_R(n) | CALC_ODT_W(n))
148 /* Defines for the Read Cycle Delay test */
149 #define NUMMEMTESTS 8
150 #define NUMMEMWORDS 8
151 #define NUMLOOPS 64 /* memory test loops */
154 * Newer PPC's like 440SPe, 460EX/GT can be equipped with more than 2GB of SDRAM.
155 * To support such configurations, we "only" map the first 2GB via the TLB's. We
156 * need some free virtual address space for the remaining peripherals like, SoC
157 * devices, FLASH etc.
159 * Note that ECC is currently not supported on configurations with more than 2GB
160 * SDRAM. This is because we only map the first 2GB on such systems, and therefore
161 * the ECC parity byte of the remaining area can't be written.
165 * Board-specific Platform code can reimplement spd_ddr_init_hang () if needed
167 void __spd_ddr_init_hang (void)
171 void spd_ddr_init_hang (void) __attribute__((weak, alias("__spd_ddr_init_hang")));
174 * To provide an interface for board specific config values in this common
175 * DDR setup code, we implement he "weak" default functions here. They return
176 * the default value back to the caller.
178 * Please see include/configs/yucca.h for an example fora board specific
181 u32 __ddr_wrdtr(u32 default_val)
185 u32 ddr_wrdtr(u32) __attribute__((weak, alias("__ddr_wrdtr")));
187 u32 __ddr_clktr(u32 default_val)
191 u32 ddr_clktr(u32) __attribute__((weak, alias("__ddr_clktr")));
194 /* Private Structure Definitions */
196 /* enum only to ease code for cas latency setting */
197 typedef enum ddr_cas_id {
205 /*-----------------------------------------------------------------------------+
207 *-----------------------------------------------------------------------------*/
208 static phys_size_t sdram_memsize(void);
209 static void get_spd_info(unsigned long *dimm_populated,
210 unsigned char *iic0_dimm_addr,
211 unsigned long num_dimm_banks);
212 static void check_mem_type(unsigned long *dimm_populated,
213 unsigned char *iic0_dimm_addr,
214 unsigned long num_dimm_banks);
215 static void check_frequency(unsigned long *dimm_populated,
216 unsigned char *iic0_dimm_addr,
217 unsigned long num_dimm_banks);
218 static void check_rank_number(unsigned long *dimm_populated,
219 unsigned char *iic0_dimm_addr,
220 unsigned long num_dimm_banks);
221 static void check_voltage_type(unsigned long *dimm_populated,
222 unsigned char *iic0_dimm_addr,
223 unsigned long num_dimm_banks);
224 static void program_memory_queue(unsigned long *dimm_populated,
225 unsigned char *iic0_dimm_addr,
226 unsigned long num_dimm_banks);
227 static void program_codt(unsigned long *dimm_populated,
228 unsigned char *iic0_dimm_addr,
229 unsigned long num_dimm_banks);
230 static void program_mode(unsigned long *dimm_populated,
231 unsigned char *iic0_dimm_addr,
232 unsigned long num_dimm_banks,
233 ddr_cas_id_t *selected_cas,
234 int *write_recovery);
235 static void program_tr(unsigned long *dimm_populated,
236 unsigned char *iic0_dimm_addr,
237 unsigned long num_dimm_banks);
238 static void program_rtr(unsigned long *dimm_populated,
239 unsigned char *iic0_dimm_addr,
240 unsigned long num_dimm_banks);
241 static void program_bxcf(unsigned long *dimm_populated,
242 unsigned char *iic0_dimm_addr,
243 unsigned long num_dimm_banks);
244 static void program_copt1(unsigned long *dimm_populated,
245 unsigned char *iic0_dimm_addr,
246 unsigned long num_dimm_banks);
247 static void program_initplr(unsigned long *dimm_populated,
248 unsigned char *iic0_dimm_addr,
249 unsigned long num_dimm_banks,
250 ddr_cas_id_t selected_cas,
252 static unsigned long is_ecc_enabled(void);
253 #ifdef CONFIG_DDR_ECC
254 static void program_ecc(unsigned long *dimm_populated,
255 unsigned char *iic0_dimm_addr,
256 unsigned long num_dimm_banks,
257 unsigned long tlb_word2_i_value);
258 static void program_ecc_addr(unsigned long start_address,
259 unsigned long num_bytes,
260 unsigned long tlb_word2_i_value);
262 #if !defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION)
263 static void program_DQS_calibration(unsigned long *dimm_populated,
264 unsigned char *iic0_dimm_addr,
265 unsigned long num_dimm_banks);
266 #ifdef HARD_CODED_DQS /* calibration test with hardvalues */
267 static void test(void);
269 static void DQS_calibration_process(void);
272 int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
273 void dcbz_area(u32 start_address, u32 num_bytes);
275 static unsigned char spd_read(uchar chip, uint addr)
277 unsigned char data[2];
279 if (i2c_probe(chip) == 0)
280 if (i2c_read(chip, addr, 1, data, 1) == 0)
286 /*-----------------------------------------------------------------------------+
288 *-----------------------------------------------------------------------------*/
289 static phys_size_t sdram_memsize(void)
291 phys_size_t mem_size;
292 unsigned long mcopt2;
293 unsigned long mcstat;
300 mfsdram(SDRAM_MCOPT2, mcopt2);
301 mfsdram(SDRAM_MCSTAT, mcstat);
303 /* DDR controller must be enabled and not in self-refresh. */
304 /* Otherwise memsize is zero. */
305 if (((mcopt2 & SDRAM_MCOPT2_DCEN_MASK) == SDRAM_MCOPT2_DCEN_ENABLE)
306 && ((mcopt2 & SDRAM_MCOPT2_SREN_MASK) == SDRAM_MCOPT2_SREN_EXIT)
307 && ((mcstat & (SDRAM_MCSTAT_MIC_MASK | SDRAM_MCSTAT_SRMS_MASK))
308 == (SDRAM_MCSTAT_MIC_COMP | SDRAM_MCSTAT_SRMS_NOT_SF))) {
309 for (i = 0; i < MAXBXCF; i++) {
310 mfsdram(SDRAM_MB0CF + (i << 2), mb0cf);
312 if ((mb0cf & SDRAM_BXCF_M_BE_MASK) == SDRAM_BXCF_M_BE_ENABLE) {
313 sdsz = mfdcr_any(SDRAM_R0BAS + i) & SDRAM_RXBAS_SDSZ_MASK;
316 case SDRAM_RXBAS_SDSZ_8:
319 case SDRAM_RXBAS_SDSZ_16:
322 case SDRAM_RXBAS_SDSZ_32:
325 case SDRAM_RXBAS_SDSZ_64:
328 case SDRAM_RXBAS_SDSZ_128:
331 case SDRAM_RXBAS_SDSZ_256:
334 case SDRAM_RXBAS_SDSZ_512:
337 case SDRAM_RXBAS_SDSZ_1024:
340 case SDRAM_RXBAS_SDSZ_2048:
343 case SDRAM_RXBAS_SDSZ_4096:
347 printf("WARNING: Unsupported bank size (SDSZ=0x%lx)!\n"
356 return mem_size << 20;
359 /*-----------------------------------------------------------------------------+
360 * initdram. Initializes the 440SP Memory Queue and DDR SDRAM controller.
361 * Note: This routine runs from flash with a stack set up in the chip's
362 * sram space. It is important that the routine does not require .sbss, .bss or
363 * .data sections. It also cannot call routines that require these sections.
364 *-----------------------------------------------------------------------------*/
365 /*-----------------------------------------------------------------------------
367 * Description: Configures SDRAM memory banks for DDR operation.
368 * Auto Memory Configuration option reads the DDR SDRAM EEPROMs
369 * via the IIC bus and then configures the DDR SDRAM memory
370 * banks appropriately. If Auto Memory Configuration is
371 * not used, it is assumed that no DIMM is plugged
372 *-----------------------------------------------------------------------------*/
373 phys_size_t initdram(int board_type)
375 unsigned char iic0_dimm_addr[] = SPD_EEPROM_ADDRESS;
376 unsigned char spd0[MAX_SPD_BYTES];
377 unsigned char spd1[MAX_SPD_BYTES];
378 unsigned char *dimm_spd[MAXDIMMS];
379 unsigned long dimm_populated[MAXDIMMS];
380 unsigned long num_dimm_banks; /* on board dimm banks */
382 ddr_cas_id_t selected_cas = DDR_CAS_5; /* preset to silence compiler */
384 phys_size_t dram_size = 0;
386 num_dimm_banks = sizeof(iic0_dimm_addr);
388 /*------------------------------------------------------------------
389 * Set up an array of SPD matrixes.
390 *-----------------------------------------------------------------*/
394 /*------------------------------------------------------------------
395 * Reset the DDR-SDRAM controller.
396 *-----------------------------------------------------------------*/
397 mtsdr(SDR0_SRST, (0x80000000 >> 10));
398 mtsdr(SDR0_SRST, 0x00000000);
401 * Make sure I2C controller is initialized
405 /* switch to correct I2C bus */
406 I2C_SET_BUS(CONFIG_SYS_SPD_BUS_NUM);
407 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
409 /*------------------------------------------------------------------
410 * Clear out the serial presence detect buffers.
411 * Perform IIC reads from the dimm. Fill in the spds.
412 * Check to see if the dimm slots are populated
413 *-----------------------------------------------------------------*/
414 get_spd_info(dimm_populated, iic0_dimm_addr, num_dimm_banks);
416 /*------------------------------------------------------------------
417 * Check the memory type for the dimms plugged.
418 *-----------------------------------------------------------------*/
419 check_mem_type(dimm_populated, iic0_dimm_addr, num_dimm_banks);
421 /*------------------------------------------------------------------
422 * Check the frequency supported for the dimms plugged.
423 *-----------------------------------------------------------------*/
424 check_frequency(dimm_populated, iic0_dimm_addr, num_dimm_banks);
426 /*------------------------------------------------------------------
427 * Check the total rank number.
428 *-----------------------------------------------------------------*/
429 check_rank_number(dimm_populated, iic0_dimm_addr, num_dimm_banks);
431 /*------------------------------------------------------------------
432 * Check the voltage type for the dimms plugged.
433 *-----------------------------------------------------------------*/
434 check_voltage_type(dimm_populated, iic0_dimm_addr, num_dimm_banks);
436 /*------------------------------------------------------------------
437 * Program SDRAM controller options 2 register
438 * Except Enabling of the memory controller.
439 *-----------------------------------------------------------------*/
440 mfsdram(SDRAM_MCOPT2, val);
441 mtsdram(SDRAM_MCOPT2,
443 ~(SDRAM_MCOPT2_SREN_MASK | SDRAM_MCOPT2_PMEN_MASK |
444 SDRAM_MCOPT2_IPTR_MASK | SDRAM_MCOPT2_XSRP_MASK |
445 SDRAM_MCOPT2_ISIE_MASK))
446 | (SDRAM_MCOPT2_SREN_ENTER | SDRAM_MCOPT2_PMEN_DISABLE |
447 SDRAM_MCOPT2_IPTR_IDLE | SDRAM_MCOPT2_XSRP_ALLOW |
448 SDRAM_MCOPT2_ISIE_ENABLE));
450 /*------------------------------------------------------------------
451 * Program SDRAM controller options 1 register
452 * Note: Does not enable the memory controller.
453 *-----------------------------------------------------------------*/
454 program_copt1(dimm_populated, iic0_dimm_addr, num_dimm_banks);
456 /*------------------------------------------------------------------
457 * Set the SDRAM Controller On Die Termination Register
458 *-----------------------------------------------------------------*/
459 program_codt(dimm_populated, iic0_dimm_addr, num_dimm_banks);
461 /*------------------------------------------------------------------
462 * Program SDRAM refresh register.
463 *-----------------------------------------------------------------*/
464 program_rtr(dimm_populated, iic0_dimm_addr, num_dimm_banks);
466 /*------------------------------------------------------------------
467 * Program SDRAM mode register.
468 *-----------------------------------------------------------------*/
469 program_mode(dimm_populated, iic0_dimm_addr, num_dimm_banks,
470 &selected_cas, &write_recovery);
472 /*------------------------------------------------------------------
473 * Set the SDRAM Write Data/DM/DQS Clock Timing Reg
474 *-----------------------------------------------------------------*/
475 mfsdram(SDRAM_WRDTR, val);
476 mtsdram(SDRAM_WRDTR, (val & ~(SDRAM_WRDTR_LLWP_MASK | SDRAM_WRDTR_WTR_MASK)) |
477 ddr_wrdtr(SDRAM_WRDTR_LLWP_1_CYC | SDRAM_WRDTR_WTR_90_DEG_ADV));
479 /*------------------------------------------------------------------
480 * Set the SDRAM Clock Timing Register
481 *-----------------------------------------------------------------*/
482 mfsdram(SDRAM_CLKTR, val);
483 mtsdram(SDRAM_CLKTR, (val & ~SDRAM_CLKTR_CLKP_MASK) |
484 ddr_clktr(SDRAM_CLKTR_CLKP_0_DEG));
486 /*------------------------------------------------------------------
487 * Program the BxCF registers.
488 *-----------------------------------------------------------------*/
489 program_bxcf(dimm_populated, iic0_dimm_addr, num_dimm_banks);
491 /*------------------------------------------------------------------
492 * Program SDRAM timing registers.
493 *-----------------------------------------------------------------*/
494 program_tr(dimm_populated, iic0_dimm_addr, num_dimm_banks);
496 /*------------------------------------------------------------------
497 * Set the Extended Mode register
498 *-----------------------------------------------------------------*/
499 mfsdram(SDRAM_MEMODE, val);
500 mtsdram(SDRAM_MEMODE,
501 (val & ~(SDRAM_MEMODE_DIC_MASK | SDRAM_MEMODE_DLL_MASK |
502 SDRAM_MEMODE_RTT_MASK | SDRAM_MEMODE_DQS_MASK)) |
503 (SDRAM_MEMODE_DIC_NORMAL | SDRAM_MEMODE_DLL_ENABLE
504 | SDRAM_MEMODE_RTT_150OHM | SDRAM_MEMODE_DQS_ENABLE));
506 /*------------------------------------------------------------------
507 * Program Initialization preload registers.
508 *-----------------------------------------------------------------*/
509 program_initplr(dimm_populated, iic0_dimm_addr, num_dimm_banks,
510 selected_cas, write_recovery);
512 /*------------------------------------------------------------------
513 * Delay to ensure 200usec have elapsed since reset.
514 *-----------------------------------------------------------------*/
517 /*------------------------------------------------------------------
518 * Set the memory queue core base addr.
519 *-----------------------------------------------------------------*/
520 program_memory_queue(dimm_populated, iic0_dimm_addr, num_dimm_banks);
522 /*------------------------------------------------------------------
523 * Program SDRAM controller options 2 register
524 * Enable the memory controller.
525 *-----------------------------------------------------------------*/
526 mfsdram(SDRAM_MCOPT2, val);
527 mtsdram(SDRAM_MCOPT2,
528 (val & ~(SDRAM_MCOPT2_SREN_MASK | SDRAM_MCOPT2_DCEN_MASK |
529 SDRAM_MCOPT2_IPTR_MASK | SDRAM_MCOPT2_ISIE_MASK)) |
530 SDRAM_MCOPT2_IPTR_EXECUTE);
532 /*------------------------------------------------------------------
533 * Wait for IPTR_EXECUTE init sequence to complete.
534 *-----------------------------------------------------------------*/
536 mfsdram(SDRAM_MCSTAT, val);
537 } while ((val & SDRAM_MCSTAT_MIC_MASK) == SDRAM_MCSTAT_MIC_NOTCOMP);
539 /* enable the controller only after init sequence completes */
540 mfsdram(SDRAM_MCOPT2, val);
541 mtsdram(SDRAM_MCOPT2, (val | SDRAM_MCOPT2_DCEN_ENABLE));
543 /* Make sure delay-line calibration is done before proceeding */
545 mfsdram(SDRAM_DLCR, val);
546 } while (!(val & SDRAM_DLCR_DLCS_COMPLETE));
548 /* get installed memory size */
549 dram_size = sdram_memsize();
554 if (dram_size > CONFIG_MAX_MEM_MAPPED)
555 dram_size = CONFIG_MAX_MEM_MAPPED;
557 /* and program tlb entries for this size (dynamic) */
560 * Program TLB entries with caches enabled, for best performace
561 * while auto-calibrating and ECC generation
563 program_tlb(0, 0, dram_size, 0);
565 /*------------------------------------------------------------------
567 *-----------------------------------------------------------------*/
568 #if defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION)
569 DQS_autocalibration();
571 program_DQS_calibration(dimm_populated, iic0_dimm_addr, num_dimm_banks);
574 #ifdef CONFIG_DDR_ECC
575 /*------------------------------------------------------------------
576 * If ecc is enabled, initialize the parity bits.
577 *-----------------------------------------------------------------*/
578 program_ecc(dimm_populated, iic0_dimm_addr, num_dimm_banks, 0);
582 * Now after initialization (auto-calibration and ECC generation)
583 * remove the TLB entries with caches enabled and program again with
584 * desired cache functionality
586 remove_tlb(0, dram_size);
587 program_tlb(0, 0, dram_size, MY_TLB_WORD2_I_ENABLE);
589 ppc4xx_ibm_ddr2_register_dump();
592 * Clear potential errors resulting from auto-calibration.
593 * If not done, then we could get an interrupt later on when
594 * exceptions are enabled.
596 set_mcsr(get_mcsr());
598 return sdram_memsize();
601 static void get_spd_info(unsigned long *dimm_populated,
602 unsigned char *iic0_dimm_addr,
603 unsigned long num_dimm_banks)
605 unsigned long dimm_num;
606 unsigned long dimm_found;
607 unsigned char num_of_bytes;
608 unsigned char total_size;
611 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
615 num_of_bytes = spd_read(iic0_dimm_addr[dimm_num], 0);
616 debug("\nspd_read(0x%x) returned %d\n",
617 iic0_dimm_addr[dimm_num], num_of_bytes);
618 total_size = spd_read(iic0_dimm_addr[dimm_num], 1);
619 debug("spd_read(0x%x) returned %d\n",
620 iic0_dimm_addr[dimm_num], total_size);
622 if ((num_of_bytes != 0) && (total_size != 0)) {
623 dimm_populated[dimm_num] = TRUE;
625 debug("DIMM slot %lu: populated\n", dimm_num);
627 dimm_populated[dimm_num] = FALSE;
628 debug("DIMM slot %lu: Not populated\n", dimm_num);
632 if (dimm_found == FALSE) {
633 printf("ERROR - No memory installed. Install a DDR-SDRAM DIMM.\n\n");
634 spd_ddr_init_hang ();
638 void board_add_ram_info(int use_default)
640 PPC4xx_SYS_INFO board_cfg;
643 if (is_ecc_enabled())
648 get_sys_info(&board_cfg);
650 mfsdr(SDR0_DDR0, val);
651 val = MULDIV64((board_cfg.freqPLB), SDR0_DDR0_DDRM_DECODE(val), 1);
652 printf(" enabled, %d MHz", (val * 2) / 1000000);
654 mfsdram(SDRAM_MMODE, val);
655 val = (val & SDRAM_MMODE_DCL_MASK) >> 4;
656 printf(", CL%d)", val);
659 /*------------------------------------------------------------------
660 * For the memory DIMMs installed, this routine verifies that they
661 * really are DDR specific DIMMs.
662 *-----------------------------------------------------------------*/
663 static void check_mem_type(unsigned long *dimm_populated,
664 unsigned char *iic0_dimm_addr,
665 unsigned long num_dimm_banks)
667 unsigned long dimm_num;
668 unsigned long dimm_type;
670 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
671 if (dimm_populated[dimm_num] == TRUE) {
672 dimm_type = spd_read(iic0_dimm_addr[dimm_num], 2);
675 printf("ERROR: Standard Fast Page Mode DRAM DIMM detected in "
676 "slot %d.\n", (unsigned int)dimm_num);
677 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
678 printf("Replace the DIMM module with a supported DIMM.\n\n");
679 spd_ddr_init_hang ();
682 printf("ERROR: EDO DIMM detected in slot %d.\n",
683 (unsigned int)dimm_num);
684 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
685 printf("Replace the DIMM module with a supported DIMM.\n\n");
686 spd_ddr_init_hang ();
689 printf("ERROR: Pipelined Nibble DIMM detected in slot %d.\n",
690 (unsigned int)dimm_num);
691 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
692 printf("Replace the DIMM module with a supported DIMM.\n\n");
693 spd_ddr_init_hang ();
696 printf("ERROR: SDRAM DIMM detected in slot %d.\n",
697 (unsigned int)dimm_num);
698 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
699 printf("Replace the DIMM module with a supported DIMM.\n\n");
700 spd_ddr_init_hang ();
703 printf("ERROR: Multiplexed ROM DIMM detected in slot %d.\n",
704 (unsigned int)dimm_num);
705 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
706 printf("Replace the DIMM module with a supported DIMM.\n\n");
707 spd_ddr_init_hang ();
710 printf("ERROR: SGRAM DIMM detected in slot %d.\n",
711 (unsigned int)dimm_num);
712 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
713 printf("Replace the DIMM module with a supported DIMM.\n\n");
714 spd_ddr_init_hang ();
717 debug("DIMM slot %d: DDR1 SDRAM detected\n", dimm_num);
718 dimm_populated[dimm_num] = SDRAM_DDR1;
721 debug("DIMM slot %d: DDR2 SDRAM detected\n", dimm_num);
722 dimm_populated[dimm_num] = SDRAM_DDR2;
725 printf("ERROR: Unknown DIMM detected in slot %d.\n",
726 (unsigned int)dimm_num);
727 printf("Only DDR1 and DDR2 SDRAM DIMMs are supported.\n");
728 printf("Replace the DIMM module with a supported DIMM.\n\n");
729 spd_ddr_init_hang ();
734 for (dimm_num = 1; dimm_num < num_dimm_banks; dimm_num++) {
735 if ((dimm_populated[dimm_num-1] != SDRAM_NONE)
736 && (dimm_populated[dimm_num] != SDRAM_NONE)
737 && (dimm_populated[dimm_num-1] != dimm_populated[dimm_num])) {
738 printf("ERROR: DIMM's DDR1 and DDR2 type can not be mixed.\n");
739 spd_ddr_init_hang ();
744 /*------------------------------------------------------------------
745 * For the memory DIMMs installed, this routine verifies that
746 * frequency previously calculated is supported.
747 *-----------------------------------------------------------------*/
748 static void check_frequency(unsigned long *dimm_populated,
749 unsigned char *iic0_dimm_addr,
750 unsigned long num_dimm_banks)
752 unsigned long dimm_num;
753 unsigned long tcyc_reg;
754 unsigned long cycle_time;
755 unsigned long calc_cycle_time;
756 unsigned long sdram_freq;
757 unsigned long sdr_ddrpll;
758 PPC4xx_SYS_INFO board_cfg;
760 /*------------------------------------------------------------------
761 * Get the board configuration info.
762 *-----------------------------------------------------------------*/
763 get_sys_info(&board_cfg);
765 mfsdr(SDR0_DDR0, sdr_ddrpll);
766 sdram_freq = ((board_cfg.freqPLB) * SDR0_DDR0_DDRM_DECODE(sdr_ddrpll));
769 * calc_cycle_time is calculated from DDR frequency set by board/chip
770 * and is expressed in multiple of 10 picoseconds
771 * to match the way DIMM cycle time is calculated below.
773 calc_cycle_time = MULDIV64(ONE_BILLION, 100, sdram_freq);
775 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
776 if (dimm_populated[dimm_num] != SDRAM_NONE) {
777 tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 9);
779 * Byte 9, Cycle time for CAS Latency=X, is split into two nibbles:
780 * the higher order nibble (bits 4-7) designates the cycle time
781 * to a granularity of 1ns;
782 * the value presented by the lower order nibble (bits 0-3)
783 * has a granularity of .1ns and is added to the value designated
784 * by the higher nibble. In addition, four lines of the lower order
785 * nibble are assigned to support +.25,+.33, +.66 and +.75.
787 /* Convert from hex to decimal */
788 if ((tcyc_reg & 0x0F) == 0x0D)
789 cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) + 75;
790 else if ((tcyc_reg & 0x0F) == 0x0C)
791 cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) + 66;
792 else if ((tcyc_reg & 0x0F) == 0x0B)
793 cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) + 33;
794 else if ((tcyc_reg & 0x0F) == 0x0A)
795 cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) + 25;
797 cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) +
798 ((tcyc_reg & 0x0F)*10);
799 debug("cycle_time=%d [10 picoseconds]\n", cycle_time);
801 if (cycle_time > (calc_cycle_time + 10)) {
803 * the provided sdram cycle_time is too small
804 * for the available DIMM cycle_time.
805 * The additionnal 100ps is here to accept a small incertainty.
807 printf("ERROR: DRAM DIMM detected with cycle_time %d ps in "
808 "slot %d \n while calculated cycle time is %d ps.\n",
809 (unsigned int)(cycle_time*10),
810 (unsigned int)dimm_num,
811 (unsigned int)(calc_cycle_time*10));
812 printf("Replace the DIMM, or change DDR frequency via "
813 "strapping bits.\n\n");
814 spd_ddr_init_hang ();
820 /*------------------------------------------------------------------
821 * For the memory DIMMs installed, this routine verifies two
822 * ranks/banks maximum are availables.
823 *-----------------------------------------------------------------*/
824 static void check_rank_number(unsigned long *dimm_populated,
825 unsigned char *iic0_dimm_addr,
826 unsigned long num_dimm_banks)
828 unsigned long dimm_num;
829 unsigned long dimm_rank;
830 unsigned long total_rank = 0;
832 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
833 if (dimm_populated[dimm_num] != SDRAM_NONE) {
834 dimm_rank = spd_read(iic0_dimm_addr[dimm_num], 5);
835 if (((unsigned long)spd_read(iic0_dimm_addr[dimm_num], 2)) == 0x08)
836 dimm_rank = (dimm_rank & 0x0F) +1;
838 dimm_rank = dimm_rank & 0x0F;
841 if (dimm_rank > MAXRANKS) {
842 printf("ERROR: DRAM DIMM detected with %lu ranks in "
843 "slot %lu is not supported.\n", dimm_rank, dimm_num);
844 printf("Only %d ranks are supported for all DIMM.\n", MAXRANKS);
845 printf("Replace the DIMM module with a supported DIMM.\n\n");
846 spd_ddr_init_hang ();
848 total_rank += dimm_rank;
850 if (total_rank > MAXRANKS) {
851 printf("ERROR: DRAM DIMM detected with a total of %d ranks "
852 "for all slots.\n", (unsigned int)total_rank);
853 printf("Only %d ranks are supported for all DIMM.\n", MAXRANKS);
854 printf("Remove one of the DIMM modules.\n\n");
855 spd_ddr_init_hang ();
860 /*------------------------------------------------------------------
861 * only support 2.5V modules.
862 * This routine verifies this.
863 *-----------------------------------------------------------------*/
864 static void check_voltage_type(unsigned long *dimm_populated,
865 unsigned char *iic0_dimm_addr,
866 unsigned long num_dimm_banks)
868 unsigned long dimm_num;
869 unsigned long voltage_type;
871 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
872 if (dimm_populated[dimm_num] != SDRAM_NONE) {
873 voltage_type = spd_read(iic0_dimm_addr[dimm_num], 8);
874 switch (voltage_type) {
876 printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
877 printf("This DIMM is 5.0 Volt/TTL.\n");
878 printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
879 (unsigned int)dimm_num);
880 spd_ddr_init_hang ();
883 printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
884 printf("This DIMM is LVTTL.\n");
885 printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
886 (unsigned int)dimm_num);
887 spd_ddr_init_hang ();
890 printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
891 printf("This DIMM is 1.5 Volt.\n");
892 printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
893 (unsigned int)dimm_num);
894 spd_ddr_init_hang ();
897 printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
898 printf("This DIMM is 3.3 Volt/TTL.\n");
899 printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
900 (unsigned int)dimm_num);
901 spd_ddr_init_hang ();
904 /* 2.5 Voltage only for DDR1 */
907 /* 1.8 Voltage only for DDR2 */
910 printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
911 printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
912 (unsigned int)dimm_num);
913 spd_ddr_init_hang ();
920 /*-----------------------------------------------------------------------------+
922 *-----------------------------------------------------------------------------*/
923 static void program_copt1(unsigned long *dimm_populated,
924 unsigned char *iic0_dimm_addr,
925 unsigned long num_dimm_banks)
927 unsigned long dimm_num;
928 unsigned long mcopt1;
929 unsigned long ecc_enabled;
930 unsigned long ecc = 0;
931 unsigned long data_width = 0;
932 unsigned long dimm_32bit;
933 unsigned long dimm_64bit;
934 unsigned long registered = 0;
935 unsigned long attribute = 0;
936 unsigned long buf0, buf1; /* TODO: code to be changed for IOP1.6 to support 4 DIMMs */
937 unsigned long bankcount;
938 unsigned long ddrtype;
941 #ifdef CONFIG_DDR_ECC
951 /*------------------------------------------------------------------
952 * Set memory controller options reg 1, SDRAM_MCOPT1.
953 *-----------------------------------------------------------------*/
954 mfsdram(SDRAM_MCOPT1, val);
955 mcopt1 = val & ~(SDRAM_MCOPT1_MCHK_MASK | SDRAM_MCOPT1_RDEN_MASK |
956 SDRAM_MCOPT1_PMU_MASK | SDRAM_MCOPT1_DMWD_MASK |
957 SDRAM_MCOPT1_UIOS_MASK | SDRAM_MCOPT1_BCNT_MASK |
958 SDRAM_MCOPT1_DDR_TYPE_MASK | SDRAM_MCOPT1_RWOO_MASK |
959 SDRAM_MCOPT1_WOOO_MASK | SDRAM_MCOPT1_DCOO_MASK |
960 SDRAM_MCOPT1_DREF_MASK);
962 mcopt1 |= SDRAM_MCOPT1_QDEP;
963 mcopt1 |= SDRAM_MCOPT1_PMU_OPEN;
964 mcopt1 |= SDRAM_MCOPT1_RWOO_DISABLED;
965 mcopt1 |= SDRAM_MCOPT1_WOOO_DISABLED;
966 mcopt1 |= SDRAM_MCOPT1_DCOO_DISABLED;
967 mcopt1 |= SDRAM_MCOPT1_DREF_NORMAL;
969 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
970 if (dimm_populated[dimm_num] != SDRAM_NONE) {
971 /* test ecc support */
972 ecc = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 11);
973 if (ecc != 0x02) /* ecc not supported */
976 /* test bank count */
977 bankcount = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 17);
978 if (bankcount == 0x04) /* bank count = 4 */
979 mcopt1 |= SDRAM_MCOPT1_4_BANKS;
980 else /* bank count = 8 */
981 mcopt1 |= SDRAM_MCOPT1_8_BANKS;
984 ddrtype = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 2);
985 /* test for buffered/unbuffered, registered, differential clocks */
986 registered = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 20);
987 attribute = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 21);
989 /* TODO: code to be changed for IOP1.6 to support 4 DIMMs */
991 if (dimm_populated[dimm_num] == SDRAM_DDR1) /* DDR1 type */
992 mcopt1 |= SDRAM_MCOPT1_DDR1_TYPE;
993 if (dimm_populated[dimm_num] == SDRAM_DDR2) /* DDR2 type */
994 mcopt1 |= SDRAM_MCOPT1_DDR2_TYPE;
995 if (registered == 1) { /* DDR2 always buffered */
996 /* TODO: what about above comments ? */
997 mcopt1 |= SDRAM_MCOPT1_RDEN;
1000 /* TODO: the mask 0x02 doesn't match Samsung def for byte 21. */
1001 if ((attribute & 0x02) == 0x00) {
1002 /* buffered not supported */
1005 mcopt1 |= SDRAM_MCOPT1_RDEN;
1010 else if (dimm_num == 1) {
1011 if (dimm_populated[dimm_num] == SDRAM_DDR1) /* DDR1 type */
1012 mcopt1 |= SDRAM_MCOPT1_DDR1_TYPE;
1013 if (dimm_populated[dimm_num] == SDRAM_DDR2) /* DDR2 type */
1014 mcopt1 |= SDRAM_MCOPT1_DDR2_TYPE;
1015 if (registered == 1) {
1016 /* DDR2 always buffered */
1017 mcopt1 |= SDRAM_MCOPT1_RDEN;
1020 if ((attribute & 0x02) == 0x00) {
1021 /* buffered not supported */
1024 mcopt1 |= SDRAM_MCOPT1_RDEN;
1030 /* Note that for DDR2 the byte 7 is reserved, but OK to keep code as is. */
1031 data_width = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 6) +
1032 (((unsigned long)spd_read(iic0_dimm_addr[dimm_num], 7)) << 8);
1034 switch (data_width) {
1044 printf("WARNING: Detected a DIMM with a data width of %lu bits.\n",
1046 printf("Only DIMMs with 32 or 64 bit DDR-SDRAM widths are supported.\n");
1052 /* verify matching properties */
1053 if ((dimm_populated[0] != SDRAM_NONE) && (dimm_populated[1] != SDRAM_NONE)) {
1055 printf("ERROR: DIMM's buffered/unbuffered, registered, clocking don't match.\n");
1056 spd_ddr_init_hang ();
1060 if ((dimm_64bit == TRUE) && (dimm_32bit == TRUE)) {
1061 printf("ERROR: Cannot mix 32 bit and 64 bit DDR-SDRAM DIMMs together.\n");
1062 spd_ddr_init_hang ();
1064 else if ((dimm_64bit == TRUE) && (dimm_32bit == FALSE)) {
1065 mcopt1 |= SDRAM_MCOPT1_DMWD_64;
1066 } else if ((dimm_64bit == FALSE) && (dimm_32bit == TRUE)) {
1067 mcopt1 |= SDRAM_MCOPT1_DMWD_32;
1069 printf("ERROR: Please install only 32 or 64 bit DDR-SDRAM DIMMs.\n\n");
1070 spd_ddr_init_hang ();
1073 if (ecc_enabled == TRUE)
1074 mcopt1 |= SDRAM_MCOPT1_MCHK_GEN;
1076 mcopt1 |= SDRAM_MCOPT1_MCHK_NON;
1078 mtsdram(SDRAM_MCOPT1, mcopt1);
1081 /*-----------------------------------------------------------------------------+
1083 *-----------------------------------------------------------------------------*/
1084 static void program_codt(unsigned long *dimm_populated,
1085 unsigned char *iic0_dimm_addr,
1086 unsigned long num_dimm_banks)
1089 unsigned long modt0 = 0;
1090 unsigned long modt1 = 0;
1091 unsigned long modt2 = 0;
1092 unsigned long modt3 = 0;
1093 unsigned char dimm_num;
1094 unsigned char dimm_rank;
1095 unsigned char total_rank = 0;
1096 unsigned char total_dimm = 0;
1097 unsigned char dimm_type = 0;
1098 unsigned char firstSlot = 0;
1100 /*------------------------------------------------------------------
1101 * Set the SDRAM Controller On Die Termination Register
1102 *-----------------------------------------------------------------*/
1103 mfsdram(SDRAM_CODT, codt);
1104 codt |= (SDRAM_CODT_IO_NMODE
1105 & (~SDRAM_CODT_DQS_SINGLE_END
1106 & ~SDRAM_CODT_CKSE_SINGLE_END
1107 & ~SDRAM_CODT_FEEBBACK_RCV_SINGLE_END
1108 & ~SDRAM_CODT_FEEBBACK_DRV_SINGLE_END));
1110 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1111 if (dimm_populated[dimm_num] != SDRAM_NONE) {
1112 dimm_rank = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 5);
1113 if (((unsigned long)spd_read(iic0_dimm_addr[dimm_num], 2)) == 0x08) {
1114 dimm_rank = (dimm_rank & 0x0F) + 1;
1115 dimm_type = SDRAM_DDR2;
1117 dimm_rank = dimm_rank & 0x0F;
1118 dimm_type = SDRAM_DDR1;
1121 total_rank += dimm_rank;
1123 if ((dimm_num == 0) && (total_dimm == 1))
1129 if (dimm_type == SDRAM_DDR2) {
1130 codt |= SDRAM_CODT_DQS_1_8_V_DDR2;
1131 if ((total_dimm == 1) && (firstSlot == TRUE)) {
1132 if (total_rank == 1) { /* PUUU */
1133 codt |= CALC_ODT_R(0);
1134 modt0 = CALC_ODT_W(0);
1139 if (total_rank == 2) { /* PPUU */
1140 codt |= CALC_ODT_R(0) | CALC_ODT_R(1);
1141 modt0 = CALC_ODT_W(0) | CALC_ODT_W(1);
1146 } else if ((total_dimm == 1) && (firstSlot != TRUE)) {
1147 if (total_rank == 1) { /* UUPU */
1148 codt |= CALC_ODT_R(2);
1151 modt2 = CALC_ODT_W(2);
1154 if (total_rank == 2) { /* UUPP */
1155 codt |= CALC_ODT_R(2) | CALC_ODT_R(3);
1158 modt2 = CALC_ODT_W(2) | CALC_ODT_W(3);
1162 if (total_dimm == 2) {
1163 if (total_rank == 2) { /* PUPU */
1164 codt |= CALC_ODT_R(0) | CALC_ODT_R(2);
1165 modt0 = CALC_ODT_RW(2);
1167 modt2 = CALC_ODT_RW(0);
1170 if (total_rank == 4) { /* PPPP */
1171 codt |= CALC_ODT_R(0) | CALC_ODT_R(1) |
1172 CALC_ODT_R(2) | CALC_ODT_R(3);
1173 modt0 = CALC_ODT_RW(2) | CALC_ODT_RW(3);
1175 modt2 = CALC_ODT_RW(0) | CALC_ODT_RW(1);
1180 codt |= SDRAM_CODT_DQS_2_5_V_DDR1;
1186 if (total_dimm == 1) {
1187 if (total_rank == 1)
1189 if (total_rank == 2)
1192 if (total_dimm == 2) {
1193 if (total_rank == 2)
1195 if (total_rank == 4)
1200 debug("nb of dimm %d\n", total_dimm);
1201 debug("nb of rank %d\n", total_rank);
1202 if (total_dimm == 1)
1203 debug("dimm in slot %d\n", firstSlot);
1205 mtsdram(SDRAM_CODT, codt);
1206 mtsdram(SDRAM_MODT0, modt0);
1207 mtsdram(SDRAM_MODT1, modt1);
1208 mtsdram(SDRAM_MODT2, modt2);
1209 mtsdram(SDRAM_MODT3, modt3);
1212 /*-----------------------------------------------------------------------------+
1214 *-----------------------------------------------------------------------------*/
1215 static void program_initplr(unsigned long *dimm_populated,
1216 unsigned char *iic0_dimm_addr,
1217 unsigned long num_dimm_banks,
1218 ddr_cas_id_t selected_cas,
1232 /******************************************************
1233 ** Assumption: if more than one DIMM, all DIMMs are the same
1234 ** as already checked in check_memory_type
1235 ******************************************************/
1237 if ((dimm_populated[0] == SDRAM_DDR1) || (dimm_populated[1] == SDRAM_DDR1)) {
1238 mtsdram(SDRAM_INITPLR0, 0x81B80000);
1239 mtsdram(SDRAM_INITPLR1, 0x81900400);
1240 mtsdram(SDRAM_INITPLR2, 0x81810000);
1241 mtsdram(SDRAM_INITPLR3, 0xff800162);
1242 mtsdram(SDRAM_INITPLR4, 0x81900400);
1243 mtsdram(SDRAM_INITPLR5, 0x86080000);
1244 mtsdram(SDRAM_INITPLR6, 0x86080000);
1245 mtsdram(SDRAM_INITPLR7, 0x81000062);
1246 } else if ((dimm_populated[0] == SDRAM_DDR2) || (dimm_populated[1] == SDRAM_DDR2)) {
1247 switch (selected_cas) {
1258 printf("ERROR: ucode error on selected_cas value %d", selected_cas);
1259 spd_ddr_init_hang ();
1265 * ToDo - Still a problem with the write recovery:
1266 * On the Corsair CM2X512-5400C4 module, setting write recovery
1267 * in the INITPLR reg to the value calculated in program_mode()
1268 * results in not correctly working DDR2 memory (crash after
1271 * So for now, set the write recovery to 3. This seems to work
1272 * on the Corair module too.
1276 switch (write_recovery) {
1290 printf("ERROR: write recovery not support (%d)", write_recovery);
1291 spd_ddr_init_hang ();
1295 wr = WRITE_RECOV_3; /* test-only, see description above */
1298 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++)
1299 if (dimm_populated[dimm_num] != SDRAM_NONE)
1301 if (total_dimm == 1) {
1304 } else if (total_dimm == 2) {
1308 printf("ERROR: Unsupported number of DIMM's (%d)", total_dimm);
1309 spd_ddr_init_hang ();
1312 mr = CMD_EMR | SELECT_MR | BURST_LEN_4 | wr | cas;
1313 emr = CMD_EMR | SELECT_EMR | odt | ods;
1314 emr2 = CMD_EMR | SELECT_EMR2;
1315 emr3 = CMD_EMR | SELECT_EMR3;
1316 /* NOP - Wait 106 MemClk cycles */
1317 mtsdram(SDRAM_INITPLR0, SDRAM_INITPLR_ENABLE | CMD_NOP |
1318 SDRAM_INITPLR_IMWT_ENCODE(106));
1320 /* precharge 4 MemClk cycles */
1321 mtsdram(SDRAM_INITPLR1, SDRAM_INITPLR_ENABLE | CMD_PRECHARGE |
1322 SDRAM_INITPLR_IMWT_ENCODE(4));
1323 /* EMR2 - Wait tMRD (2 MemClk cycles) */
1324 mtsdram(SDRAM_INITPLR2, SDRAM_INITPLR_ENABLE | emr2 |
1325 SDRAM_INITPLR_IMWT_ENCODE(2));
1326 /* EMR3 - Wait tMRD (2 MemClk cycles) */
1327 mtsdram(SDRAM_INITPLR3, SDRAM_INITPLR_ENABLE | emr3 |
1328 SDRAM_INITPLR_IMWT_ENCODE(2));
1329 /* EMR DLL ENABLE - Wait tMRD (2 MemClk cycles) */
1330 mtsdram(SDRAM_INITPLR4, SDRAM_INITPLR_ENABLE | emr |
1331 SDRAM_INITPLR_IMWT_ENCODE(2));
1332 /* MR w/ DLL reset - 200 cycle wait for DLL reset */
1333 mtsdram(SDRAM_INITPLR5, SDRAM_INITPLR_ENABLE | mr | DLL_RESET |
1334 SDRAM_INITPLR_IMWT_ENCODE(200));
1336 /* precharge 4 MemClk cycles */
1337 mtsdram(SDRAM_INITPLR6, SDRAM_INITPLR_ENABLE | CMD_PRECHARGE |
1338 SDRAM_INITPLR_IMWT_ENCODE(4));
1339 /* Refresh 25 MemClk cycles */
1340 mtsdram(SDRAM_INITPLR7, SDRAM_INITPLR_ENABLE | CMD_REFRESH |
1341 SDRAM_INITPLR_IMWT_ENCODE(25));
1342 /* Refresh 25 MemClk cycles */
1343 mtsdram(SDRAM_INITPLR8, SDRAM_INITPLR_ENABLE | CMD_REFRESH |
1344 SDRAM_INITPLR_IMWT_ENCODE(25));
1345 /* Refresh 25 MemClk cycles */
1346 mtsdram(SDRAM_INITPLR9, SDRAM_INITPLR_ENABLE | CMD_REFRESH |
1347 SDRAM_INITPLR_IMWT_ENCODE(25));
1348 /* Refresh 25 MemClk cycles */
1349 mtsdram(SDRAM_INITPLR10, SDRAM_INITPLR_ENABLE | CMD_REFRESH |
1350 SDRAM_INITPLR_IMWT_ENCODE(25));
1351 /* MR w/o DLL reset - Wait tMRD (2 MemClk cycles) */
1352 mtsdram(SDRAM_INITPLR11, SDRAM_INITPLR_ENABLE | mr |
1353 SDRAM_INITPLR_IMWT_ENCODE(2));
1354 /* EMR OCD Default - Wait tMRD (2 MemClk cycles) */
1355 mtsdram(SDRAM_INITPLR12, SDRAM_INITPLR_ENABLE | OCD_CALIB_DEF |
1356 SDRAM_INITPLR_IMWT_ENCODE(2) | emr);
1358 mtsdram(SDRAM_INITPLR13, SDRAM_INITPLR_ENABLE | emr |
1359 SDRAM_INITPLR_IMWT_ENCODE(2));
1361 printf("ERROR: ucode error as unknown DDR type in program_initplr");
1362 spd_ddr_init_hang ();
1366 /*------------------------------------------------------------------
1367 * This routine programs the SDRAM_MMODE register.
1368 * the selected_cas is an output parameter, that will be passed
1369 * by caller to call the above program_initplr( )
1370 *-----------------------------------------------------------------*/
1371 static void program_mode(unsigned long *dimm_populated,
1372 unsigned char *iic0_dimm_addr,
1373 unsigned long num_dimm_banks,
1374 ddr_cas_id_t *selected_cas,
1375 int *write_recovery)
1377 unsigned long dimm_num;
1378 unsigned long sdram_ddr1;
1379 unsigned long t_wr_ns;
1380 unsigned long t_wr_clk;
1381 unsigned long cas_bit;
1382 unsigned long cas_index;
1383 unsigned long sdram_freq;
1384 unsigned long ddr_check;
1385 unsigned long mmode;
1386 unsigned long tcyc_reg;
1387 unsigned long cycle_2_0_clk;
1388 unsigned long cycle_2_5_clk;
1389 unsigned long cycle_3_0_clk;
1390 unsigned long cycle_4_0_clk;
1391 unsigned long cycle_5_0_clk;
1392 unsigned long max_2_0_tcyc_ns_x_100;
1393 unsigned long max_2_5_tcyc_ns_x_100;
1394 unsigned long max_3_0_tcyc_ns_x_100;
1395 unsigned long max_4_0_tcyc_ns_x_100;
1396 unsigned long max_5_0_tcyc_ns_x_100;
1397 unsigned long cycle_time_ns_x_100[3];
1398 PPC4xx_SYS_INFO board_cfg;
1399 unsigned char cas_2_0_available;
1400 unsigned char cas_2_5_available;
1401 unsigned char cas_3_0_available;
1402 unsigned char cas_4_0_available;
1403 unsigned char cas_5_0_available;
1404 unsigned long sdr_ddrpll;
1406 /*------------------------------------------------------------------
1407 * Get the board configuration info.
1408 *-----------------------------------------------------------------*/
1409 get_sys_info(&board_cfg);
1411 mfsdr(SDR0_DDR0, sdr_ddrpll);
1412 sdram_freq = MULDIV64((board_cfg.freqPLB), SDR0_DDR0_DDRM_DECODE(sdr_ddrpll), 1);
1413 debug("sdram_freq=%d\n", sdram_freq);
1415 /*------------------------------------------------------------------
1416 * Handle the timing. We need to find the worst case timing of all
1417 * the dimm modules installed.
1418 *-----------------------------------------------------------------*/
1420 cas_2_0_available = TRUE;
1421 cas_2_5_available = TRUE;
1422 cas_3_0_available = TRUE;
1423 cas_4_0_available = TRUE;
1424 cas_5_0_available = TRUE;
1425 max_2_0_tcyc_ns_x_100 = 10;
1426 max_2_5_tcyc_ns_x_100 = 10;
1427 max_3_0_tcyc_ns_x_100 = 10;
1428 max_4_0_tcyc_ns_x_100 = 10;
1429 max_5_0_tcyc_ns_x_100 = 10;
1432 /* loop through all the DIMM slots on the board */
1433 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1434 /* If a dimm is installed in a particular slot ... */
1435 if (dimm_populated[dimm_num] != SDRAM_NONE) {
1436 if (dimm_populated[dimm_num] == SDRAM_DDR1)
1441 /* t_wr_ns = max(t_wr_ns, (unsigned long)dimm_spd[dimm_num][36] >> 2); */ /* not used in this loop. */
1442 cas_bit = spd_read(iic0_dimm_addr[dimm_num], 18);
1443 debug("cas_bit[SPD byte 18]=%02x\n", cas_bit);
1445 /* For a particular DIMM, grab the three CAS values it supports */
1446 for (cas_index = 0; cas_index < 3; cas_index++) {
1447 switch (cas_index) {
1449 tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 9);
1452 tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 23);
1455 tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 25);
1459 if ((tcyc_reg & 0x0F) >= 10) {
1460 if ((tcyc_reg & 0x0F) == 0x0D) {
1461 /* Convert from hex to decimal */
1462 cycle_time_ns_x_100[cas_index] =
1463 (((tcyc_reg & 0xF0) >> 4) * 100) + 75;
1465 printf("ERROR: SPD reported Tcyc is incorrect for DIMM "
1466 "in slot %d\n", (unsigned int)dimm_num);
1467 spd_ddr_init_hang ();
1470 /* Convert from hex to decimal */
1471 cycle_time_ns_x_100[cas_index] =
1472 (((tcyc_reg & 0xF0) >> 4) * 100) +
1473 ((tcyc_reg & 0x0F)*10);
1475 debug("cas_index=%d: cycle_time_ns_x_100=%d\n", cas_index,
1476 cycle_time_ns_x_100[cas_index]);
1479 /* The rest of this routine determines if CAS 2.0, 2.5, 3.0, 4.0 and 5.0 are */
1480 /* supported for a particular DIMM. */
1485 * DDR devices use the following bitmask for CAS latency:
1486 * Bit 7 6 5 4 3 2 1 0
1487 * TBD 4.0 3.5 3.0 2.5 2.0 1.5 1.0
1489 if (((cas_bit & 0x40) == 0x40) && (cas_index < 3) &&
1490 (cycle_time_ns_x_100[cas_index] != 0)) {
1491 max_4_0_tcyc_ns_x_100 = max(max_4_0_tcyc_ns_x_100,
1492 cycle_time_ns_x_100[cas_index]);
1497 cas_4_0_available = FALSE;
1500 if (((cas_bit & 0x10) == 0x10) && (cas_index < 3) &&
1501 (cycle_time_ns_x_100[cas_index] != 0)) {
1502 max_3_0_tcyc_ns_x_100 = max(max_3_0_tcyc_ns_x_100,
1503 cycle_time_ns_x_100[cas_index]);
1508 cas_3_0_available = FALSE;
1511 if (((cas_bit & 0x08) == 0x08) && (cas_index < 3) &&
1512 (cycle_time_ns_x_100[cas_index] != 0)) {
1513 max_2_5_tcyc_ns_x_100 = max(max_2_5_tcyc_ns_x_100,
1514 cycle_time_ns_x_100[cas_index]);
1519 cas_2_5_available = FALSE;
1522 if (((cas_bit & 0x04) == 0x04) && (cas_index < 3) &&
1523 (cycle_time_ns_x_100[cas_index] != 0)) {
1524 max_2_0_tcyc_ns_x_100 = max(max_2_0_tcyc_ns_x_100,
1525 cycle_time_ns_x_100[cas_index]);
1530 cas_2_0_available = FALSE;
1534 * DDR2 devices use the following bitmask for CAS latency:
1535 * Bit 7 6 5 4 3 2 1 0
1536 * TBD 6.0 5.0 4.0 3.0 2.0 TBD TBD
1538 if (((cas_bit & 0x20) == 0x20) && (cas_index < 3) &&
1539 (cycle_time_ns_x_100[cas_index] != 0)) {
1540 max_5_0_tcyc_ns_x_100 = max(max_5_0_tcyc_ns_x_100,
1541 cycle_time_ns_x_100[cas_index]);
1546 cas_5_0_available = FALSE;
1549 if (((cas_bit & 0x10) == 0x10) && (cas_index < 3) &&
1550 (cycle_time_ns_x_100[cas_index] != 0)) {
1551 max_4_0_tcyc_ns_x_100 = max(max_4_0_tcyc_ns_x_100,
1552 cycle_time_ns_x_100[cas_index]);
1557 cas_4_0_available = FALSE;
1560 if (((cas_bit & 0x08) == 0x08) && (cas_index < 3) &&
1561 (cycle_time_ns_x_100[cas_index] != 0)) {
1562 max_3_0_tcyc_ns_x_100 = max(max_3_0_tcyc_ns_x_100,
1563 cycle_time_ns_x_100[cas_index]);
1568 cas_3_0_available = FALSE;
1574 /*------------------------------------------------------------------
1575 * Set the SDRAM mode, SDRAM_MMODE
1576 *-----------------------------------------------------------------*/
1577 mfsdram(SDRAM_MMODE, mmode);
1578 mmode = mmode & ~(SDRAM_MMODE_WR_MASK | SDRAM_MMODE_DCL_MASK);
1580 /* add 10 here because of rounding problems */
1581 cycle_2_0_clk = MULDIV64(ONE_BILLION, 100, max_2_0_tcyc_ns_x_100) + 10;
1582 cycle_2_5_clk = MULDIV64(ONE_BILLION, 100, max_2_5_tcyc_ns_x_100) + 10;
1583 cycle_3_0_clk = MULDIV64(ONE_BILLION, 100, max_3_0_tcyc_ns_x_100) + 10;
1584 cycle_4_0_clk = MULDIV64(ONE_BILLION, 100, max_4_0_tcyc_ns_x_100) + 10;
1585 cycle_5_0_clk = MULDIV64(ONE_BILLION, 100, max_5_0_tcyc_ns_x_100) + 10;
1586 debug("cycle_3_0_clk=%d\n", cycle_3_0_clk);
1587 debug("cycle_4_0_clk=%d\n", cycle_4_0_clk);
1588 debug("cycle_5_0_clk=%d\n", cycle_5_0_clk);
1590 if (sdram_ddr1 == TRUE) { /* DDR1 */
1591 if ((cas_2_0_available == TRUE) && (sdram_freq <= cycle_2_0_clk)) {
1592 mmode |= SDRAM_MMODE_DCL_DDR1_2_0_CLK;
1593 *selected_cas = DDR_CAS_2;
1594 } else if ((cas_2_5_available == TRUE) && (sdram_freq <= cycle_2_5_clk)) {
1595 mmode |= SDRAM_MMODE_DCL_DDR1_2_5_CLK;
1596 *selected_cas = DDR_CAS_2_5;
1597 } else if ((cas_3_0_available == TRUE) && (sdram_freq <= cycle_3_0_clk)) {
1598 mmode |= SDRAM_MMODE_DCL_DDR1_3_0_CLK;
1599 *selected_cas = DDR_CAS_3;
1601 printf("ERROR: Cannot find a supported CAS latency with the installed DIMMs.\n");
1602 printf("Only DIMMs DDR1 with CAS latencies of 2.0, 2.5, and 3.0 are supported.\n");
1603 printf("Make sure the PLB speed is within the supported range of the DIMMs.\n\n");
1604 spd_ddr_init_hang ();
1607 debug("cas_3_0_available=%d\n", cas_3_0_available);
1608 debug("cas_4_0_available=%d\n", cas_4_0_available);
1609 debug("cas_5_0_available=%d\n", cas_5_0_available);
1610 if ((cas_3_0_available == TRUE) && (sdram_freq <= cycle_3_0_clk)) {
1611 mmode |= SDRAM_MMODE_DCL_DDR2_3_0_CLK;
1612 *selected_cas = DDR_CAS_3;
1613 } else if ((cas_4_0_available == TRUE) && (sdram_freq <= cycle_4_0_clk)) {
1614 mmode |= SDRAM_MMODE_DCL_DDR2_4_0_CLK;
1615 *selected_cas = DDR_CAS_4;
1616 } else if ((cas_5_0_available == TRUE) && (sdram_freq <= cycle_5_0_clk)) {
1617 mmode |= SDRAM_MMODE_DCL_DDR2_5_0_CLK;
1618 *selected_cas = DDR_CAS_5;
1620 printf("ERROR: Cannot find a supported CAS latency with the installed DIMMs.\n");
1621 printf("Only DIMMs DDR2 with CAS latencies of 3.0, 4.0, and 5.0 are supported.\n");
1622 printf("Make sure the PLB speed is within the supported range of the DIMMs.\n");
1623 printf("cas3=%d cas4=%d cas5=%d\n",
1624 cas_3_0_available, cas_4_0_available, cas_5_0_available);
1625 printf("sdram_freq=%lu cycle3=%lu cycle4=%lu cycle5=%lu\n\n",
1626 sdram_freq, cycle_3_0_clk, cycle_4_0_clk, cycle_5_0_clk);
1627 spd_ddr_init_hang ();
1631 if (sdram_ddr1 == TRUE)
1632 mmode |= SDRAM_MMODE_WR_DDR1;
1635 /* loop through all the DIMM slots on the board */
1636 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1637 /* If a dimm is installed in a particular slot ... */
1638 if (dimm_populated[dimm_num] != SDRAM_NONE)
1639 t_wr_ns = max(t_wr_ns,
1640 spd_read(iic0_dimm_addr[dimm_num], 36) >> 2);
1644 * convert from nanoseconds to ddr clocks
1645 * round up if necessary
1647 t_wr_clk = MULDIV64(sdram_freq, t_wr_ns, ONE_BILLION);
1648 ddr_check = MULDIV64(ONE_BILLION, t_wr_clk, t_wr_ns);
1649 if (sdram_freq != ddr_check)
1657 mmode |= SDRAM_MMODE_WR_DDR2_3_CYC;
1660 mmode |= SDRAM_MMODE_WR_DDR2_4_CYC;
1663 mmode |= SDRAM_MMODE_WR_DDR2_5_CYC;
1666 mmode |= SDRAM_MMODE_WR_DDR2_6_CYC;
1669 *write_recovery = t_wr_clk;
1672 debug("CAS latency = %d\n", *selected_cas);
1673 debug("Write recovery = %d\n", *write_recovery);
1675 mtsdram(SDRAM_MMODE, mmode);
1678 /*-----------------------------------------------------------------------------+
1680 *-----------------------------------------------------------------------------*/
1681 static void program_rtr(unsigned long *dimm_populated,
1682 unsigned char *iic0_dimm_addr,
1683 unsigned long num_dimm_banks)
1685 PPC4xx_SYS_INFO board_cfg;
1686 unsigned long max_refresh_rate;
1687 unsigned long dimm_num;
1688 unsigned long refresh_rate_type;
1689 unsigned long refresh_rate;
1691 unsigned long sdram_freq;
1692 unsigned long sdr_ddrpll;
1695 /*------------------------------------------------------------------
1696 * Get the board configuration info.
1697 *-----------------------------------------------------------------*/
1698 get_sys_info(&board_cfg);
1700 /*------------------------------------------------------------------
1701 * Set the SDRAM Refresh Timing Register, SDRAM_RTR
1702 *-----------------------------------------------------------------*/
1703 mfsdr(SDR0_DDR0, sdr_ddrpll);
1704 sdram_freq = ((board_cfg.freqPLB) * SDR0_DDR0_DDRM_DECODE(sdr_ddrpll));
1706 max_refresh_rate = 0;
1707 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1708 if (dimm_populated[dimm_num] != SDRAM_NONE) {
1710 refresh_rate_type = spd_read(iic0_dimm_addr[dimm_num], 12);
1711 refresh_rate_type &= 0x7F;
1712 switch (refresh_rate_type) {
1714 refresh_rate = 15625;
1717 refresh_rate = 3906;
1720 refresh_rate = 7812;
1723 refresh_rate = 31250;
1726 refresh_rate = 62500;
1729 refresh_rate = 125000;
1733 printf("ERROR: DIMM %d unsupported refresh rate/type.\n",
1734 (unsigned int)dimm_num);
1735 printf("Replace the DIMM module with a supported DIMM.\n\n");
1736 spd_ddr_init_hang ();
1740 max_refresh_rate = max(max_refresh_rate, refresh_rate);
1744 rint = MULDIV64(sdram_freq, max_refresh_rate, ONE_BILLION);
1745 mfsdram(SDRAM_RTR, val);
1746 mtsdram(SDRAM_RTR, (val & ~SDRAM_RTR_RINT_MASK) |
1747 (SDRAM_RTR_RINT_ENCODE(rint)));
1750 /*------------------------------------------------------------------
1751 * This routine programs the SDRAM_TRx registers.
1752 *-----------------------------------------------------------------*/
1753 static void program_tr(unsigned long *dimm_populated,
1754 unsigned char *iic0_dimm_addr,
1755 unsigned long num_dimm_banks)
1757 unsigned long dimm_num;
1758 unsigned long sdram_ddr1;
1759 unsigned long t_rp_ns;
1760 unsigned long t_rcd_ns;
1761 unsigned long t_rrd_ns;
1762 unsigned long t_ras_ns;
1763 unsigned long t_rc_ns;
1764 unsigned long t_rfc_ns;
1765 unsigned long t_wpc_ns;
1766 unsigned long t_wtr_ns;
1767 unsigned long t_rpc_ns;
1768 unsigned long t_rp_clk;
1769 unsigned long t_rcd_clk;
1770 unsigned long t_rrd_clk;
1771 unsigned long t_ras_clk;
1772 unsigned long t_rc_clk;
1773 unsigned long t_rfc_clk;
1774 unsigned long t_wpc_clk;
1775 unsigned long t_wtr_clk;
1776 unsigned long t_rpc_clk;
1777 unsigned long sdtr1, sdtr2, sdtr3;
1778 unsigned long ddr_check;
1779 unsigned long sdram_freq;
1780 unsigned long sdr_ddrpll;
1782 PPC4xx_SYS_INFO board_cfg;
1784 /*------------------------------------------------------------------
1785 * Get the board configuration info.
1786 *-----------------------------------------------------------------*/
1787 get_sys_info(&board_cfg);
1789 mfsdr(SDR0_DDR0, sdr_ddrpll);
1790 sdram_freq = ((board_cfg.freqPLB) * SDR0_DDR0_DDRM_DECODE(sdr_ddrpll));
1792 /*------------------------------------------------------------------
1793 * Handle the timing. We need to find the worst case timing of all
1794 * the dimm modules installed.
1795 *-----------------------------------------------------------------*/
1807 /* loop through all the DIMM slots on the board */
1808 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1809 /* If a dimm is installed in a particular slot ... */
1810 if (dimm_populated[dimm_num] != SDRAM_NONE) {
1811 if (dimm_populated[dimm_num] == SDRAM_DDR2)
1816 t_rcd_ns = max(t_rcd_ns, spd_read(iic0_dimm_addr[dimm_num], 29) >> 2);
1817 t_rrd_ns = max(t_rrd_ns, spd_read(iic0_dimm_addr[dimm_num], 28) >> 2);
1818 t_rp_ns = max(t_rp_ns, spd_read(iic0_dimm_addr[dimm_num], 27) >> 2);
1819 t_ras_ns = max(t_ras_ns, spd_read(iic0_dimm_addr[dimm_num], 30));
1820 t_rc_ns = max(t_rc_ns, spd_read(iic0_dimm_addr[dimm_num], 41));
1821 t_rfc_ns = max(t_rfc_ns, spd_read(iic0_dimm_addr[dimm_num], 42));
1825 /*------------------------------------------------------------------
1826 * Set the SDRAM Timing Reg 1, SDRAM_TR1
1827 *-----------------------------------------------------------------*/
1828 mfsdram(SDRAM_SDTR1, sdtr1);
1829 sdtr1 &= ~(SDRAM_SDTR1_LDOF_MASK | SDRAM_SDTR1_RTW_MASK |
1830 SDRAM_SDTR1_WTWO_MASK | SDRAM_SDTR1_RTRO_MASK);
1832 /* default values */
1833 sdtr1 |= SDRAM_SDTR1_LDOF_2_CLK;
1834 sdtr1 |= SDRAM_SDTR1_RTW_2_CLK;
1836 /* normal operations */
1837 sdtr1 |= SDRAM_SDTR1_WTWO_0_CLK;
1838 sdtr1 |= SDRAM_SDTR1_RTRO_1_CLK;
1840 mtsdram(SDRAM_SDTR1, sdtr1);
1842 /*------------------------------------------------------------------
1843 * Set the SDRAM Timing Reg 2, SDRAM_TR2
1844 *-----------------------------------------------------------------*/
1845 mfsdram(SDRAM_SDTR2, sdtr2);
1846 sdtr2 &= ~(SDRAM_SDTR2_RCD_MASK | SDRAM_SDTR2_WTR_MASK |
1847 SDRAM_SDTR2_XSNR_MASK | SDRAM_SDTR2_WPC_MASK |
1848 SDRAM_SDTR2_RPC_MASK | SDRAM_SDTR2_RP_MASK |
1849 SDRAM_SDTR2_RRD_MASK);
1852 * convert t_rcd from nanoseconds to ddr clocks
1853 * round up if necessary
1855 t_rcd_clk = MULDIV64(sdram_freq, t_rcd_ns, ONE_BILLION);
1856 ddr_check = MULDIV64(ONE_BILLION, t_rcd_clk, t_rcd_ns);
1857 if (sdram_freq != ddr_check)
1860 switch (t_rcd_clk) {
1863 sdtr2 |= SDRAM_SDTR2_RCD_1_CLK;
1866 sdtr2 |= SDRAM_SDTR2_RCD_2_CLK;
1869 sdtr2 |= SDRAM_SDTR2_RCD_3_CLK;
1872 sdtr2 |= SDRAM_SDTR2_RCD_4_CLK;
1875 sdtr2 |= SDRAM_SDTR2_RCD_5_CLK;
1879 if (sdram_ddr1 == TRUE) { /* DDR1 */
1880 if (sdram_freq < 200000000) {
1881 sdtr2 |= SDRAM_SDTR2_WTR_1_CLK;
1882 sdtr2 |= SDRAM_SDTR2_WPC_2_CLK;
1883 sdtr2 |= SDRAM_SDTR2_RPC_2_CLK;
1885 sdtr2 |= SDRAM_SDTR2_WTR_2_CLK;
1886 sdtr2 |= SDRAM_SDTR2_WPC_3_CLK;
1887 sdtr2 |= SDRAM_SDTR2_RPC_2_CLK;
1890 /* loop through all the DIMM slots on the board */
1891 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1892 /* If a dimm is installed in a particular slot ... */
1893 if (dimm_populated[dimm_num] != SDRAM_NONE) {
1894 t_wpc_ns = max(t_wtr_ns, spd_read(iic0_dimm_addr[dimm_num], 36) >> 2);
1895 t_wtr_ns = max(t_wtr_ns, spd_read(iic0_dimm_addr[dimm_num], 37) >> 2);
1896 t_rpc_ns = max(t_rpc_ns, spd_read(iic0_dimm_addr[dimm_num], 38) >> 2);
1901 * convert from nanoseconds to ddr clocks
1902 * round up if necessary
1904 t_wpc_clk = MULDIV64(sdram_freq, t_wpc_ns, ONE_BILLION);
1905 ddr_check = MULDIV64(ONE_BILLION, t_wpc_clk, t_wpc_ns);
1906 if (sdram_freq != ddr_check)
1909 switch (t_wpc_clk) {
1913 sdtr2 |= SDRAM_SDTR2_WPC_2_CLK;
1916 sdtr2 |= SDRAM_SDTR2_WPC_3_CLK;
1919 sdtr2 |= SDRAM_SDTR2_WPC_4_CLK;
1922 sdtr2 |= SDRAM_SDTR2_WPC_5_CLK;
1925 sdtr2 |= SDRAM_SDTR2_WPC_6_CLK;
1930 * convert from nanoseconds to ddr clocks
1931 * round up if necessary
1933 t_wtr_clk = MULDIV64(sdram_freq, t_wtr_ns, ONE_BILLION);
1934 ddr_check = MULDIV64(ONE_BILLION, t_wtr_clk, t_wtr_ns);
1935 if (sdram_freq != ddr_check)
1938 switch (t_wtr_clk) {
1941 sdtr2 |= SDRAM_SDTR2_WTR_1_CLK;
1944 sdtr2 |= SDRAM_SDTR2_WTR_2_CLK;
1947 sdtr2 |= SDRAM_SDTR2_WTR_3_CLK;
1950 sdtr2 |= SDRAM_SDTR2_WTR_4_CLK;
1955 * convert from nanoseconds to ddr clocks
1956 * round up if necessary
1958 t_rpc_clk = MULDIV64(sdram_freq, t_rpc_ns, ONE_BILLION);
1959 ddr_check = MULDIV64(ONE_BILLION, t_rpc_clk, t_rpc_ns);
1960 if (sdram_freq != ddr_check)
1963 switch (t_rpc_clk) {
1967 sdtr2 |= SDRAM_SDTR2_RPC_2_CLK;
1970 sdtr2 |= SDRAM_SDTR2_RPC_3_CLK;
1973 sdtr2 |= SDRAM_SDTR2_RPC_4_CLK;
1979 sdtr2 |= SDRAM_SDTR2_XSNR_16_CLK;
1982 * convert t_rrd from nanoseconds to ddr clocks
1983 * round up if necessary
1985 t_rrd_clk = MULDIV64(sdram_freq, t_rrd_ns, ONE_BILLION);
1986 ddr_check = MULDIV64(ONE_BILLION, t_rrd_clk, t_rrd_ns);
1987 if (sdram_freq != ddr_check)
1991 sdtr2 |= SDRAM_SDTR2_RRD_3_CLK;
1993 sdtr2 |= SDRAM_SDTR2_RRD_2_CLK;
1996 * convert t_rp from nanoseconds to ddr clocks
1997 * round up if necessary
1999 t_rp_clk = MULDIV64(sdram_freq, t_rp_ns, ONE_BILLION);
2000 ddr_check = MULDIV64(ONE_BILLION, t_rp_clk, t_rp_ns);
2001 if (sdram_freq != ddr_check)
2009 sdtr2 |= SDRAM_SDTR2_RP_3_CLK;
2012 sdtr2 |= SDRAM_SDTR2_RP_4_CLK;
2015 sdtr2 |= SDRAM_SDTR2_RP_5_CLK;
2018 sdtr2 |= SDRAM_SDTR2_RP_6_CLK;
2021 sdtr2 |= SDRAM_SDTR2_RP_7_CLK;
2025 mtsdram(SDRAM_SDTR2, sdtr2);
2027 /*------------------------------------------------------------------
2028 * Set the SDRAM Timing Reg 3, SDRAM_TR3
2029 *-----------------------------------------------------------------*/
2030 mfsdram(SDRAM_SDTR3, sdtr3);
2031 sdtr3 &= ~(SDRAM_SDTR3_RAS_MASK | SDRAM_SDTR3_RC_MASK |
2032 SDRAM_SDTR3_XCS_MASK | SDRAM_SDTR3_RFC_MASK);
2035 * convert t_ras from nanoseconds to ddr clocks
2036 * round up if necessary
2038 t_ras_clk = MULDIV64(sdram_freq, t_ras_ns, ONE_BILLION);
2039 ddr_check = MULDIV64(ONE_BILLION, t_ras_clk, t_ras_ns);
2040 if (sdram_freq != ddr_check)
2043 sdtr3 |= SDRAM_SDTR3_RAS_ENCODE(t_ras_clk);
2046 * convert t_rc from nanoseconds to ddr clocks
2047 * round up if necessary
2049 t_rc_clk = MULDIV64(sdram_freq, t_rc_ns, ONE_BILLION);
2050 ddr_check = MULDIV64(ONE_BILLION, t_rc_clk, t_rc_ns);
2051 if (sdram_freq != ddr_check)
2054 sdtr3 |= SDRAM_SDTR3_RC_ENCODE(t_rc_clk);
2056 /* default xcs value */
2057 sdtr3 |= SDRAM_SDTR3_XCS;
2060 * convert t_rfc from nanoseconds to ddr clocks
2061 * round up if necessary
2063 t_rfc_clk = MULDIV64(sdram_freq, t_rfc_ns, ONE_BILLION);
2064 ddr_check = MULDIV64(ONE_BILLION, t_rfc_clk, t_rfc_ns);
2065 if (sdram_freq != ddr_check)
2068 sdtr3 |= SDRAM_SDTR3_RFC_ENCODE(t_rfc_clk);
2070 mtsdram(SDRAM_SDTR3, sdtr3);
2073 /*-----------------------------------------------------------------------------+
2075 *-----------------------------------------------------------------------------*/
2076 static void program_bxcf(unsigned long *dimm_populated,
2077 unsigned char *iic0_dimm_addr,
2078 unsigned long num_dimm_banks)
2080 unsigned long dimm_num;
2081 unsigned long num_col_addr;
2082 unsigned long num_ranks;
2083 unsigned long num_banks;
2085 unsigned long ind_rank;
2087 unsigned long ind_bank;
2088 unsigned long bank_0_populated;
2090 /*------------------------------------------------------------------
2091 * Set the BxCF regs. First, wipe out the bank config registers.
2092 *-----------------------------------------------------------------*/
2093 mtsdram(SDRAM_MB0CF, 0x00000000);
2094 mtsdram(SDRAM_MB1CF, 0x00000000);
2095 mtsdram(SDRAM_MB2CF, 0x00000000);
2096 mtsdram(SDRAM_MB3CF, 0x00000000);
2098 mode = SDRAM_BXCF_M_BE_ENABLE;
2100 bank_0_populated = 0;
2102 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
2103 if (dimm_populated[dimm_num] != SDRAM_NONE) {
2104 num_col_addr = spd_read(iic0_dimm_addr[dimm_num], 4);
2105 num_ranks = spd_read(iic0_dimm_addr[dimm_num], 5);
2106 if ((spd_read(iic0_dimm_addr[dimm_num], 2)) == 0x08)
2107 num_ranks = (num_ranks & 0x0F) +1;
2109 num_ranks = num_ranks & 0x0F;
2111 num_banks = spd_read(iic0_dimm_addr[dimm_num], 17);
2113 for (ind_bank = 0; ind_bank < 2; ind_bank++) {
2118 switch (num_col_addr) {
2120 mode |= (SDRAM_BXCF_M_AM_0 + ind);
2123 mode |= (SDRAM_BXCF_M_AM_1 + ind);
2126 mode |= (SDRAM_BXCF_M_AM_2 + ind);
2129 mode |= (SDRAM_BXCF_M_AM_3 + ind);
2132 mode |= (SDRAM_BXCF_M_AM_4 + ind);
2135 printf("DDR-SDRAM: DIMM %d BxCF configuration.\n",
2136 (unsigned int)dimm_num);
2137 printf("ERROR: Unsupported value for number of "
2138 "column addresses: %d.\n", (unsigned int)num_col_addr);
2139 printf("Replace the DIMM module with a supported DIMM.\n\n");
2140 spd_ddr_init_hang ();
2144 if ((dimm_populated[dimm_num] != SDRAM_NONE)&& (dimm_num ==1))
2145 bank_0_populated = 1;
2147 for (ind_rank = 0; ind_rank < num_ranks; ind_rank++) {
2148 mtsdram(SDRAM_MB0CF +
2149 ((dimm_num + bank_0_populated + ind_rank) << 2),
2156 /*------------------------------------------------------------------
2157 * program memory queue.
2158 *-----------------------------------------------------------------*/
2159 static void program_memory_queue(unsigned long *dimm_populated,
2160 unsigned char *iic0_dimm_addr,
2161 unsigned long num_dimm_banks)
2163 unsigned long dimm_num;
2164 phys_size_t rank_base_addr;
2165 unsigned long rank_reg;
2166 phys_size_t rank_size_bytes;
2167 unsigned long rank_size_id;
2168 unsigned long num_ranks;
2169 unsigned long baseadd_size;
2171 unsigned long bank_0_populated = 0;
2172 phys_size_t total_size = 0;
2174 /*------------------------------------------------------------------
2175 * Reset the rank_base_address.
2176 *-----------------------------------------------------------------*/
2177 rank_reg = SDRAM_R0BAS;
2179 rank_base_addr = 0x00000000;
2181 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
2182 if (dimm_populated[dimm_num] != SDRAM_NONE) {
2183 num_ranks = spd_read(iic0_dimm_addr[dimm_num], 5);
2184 if ((spd_read(iic0_dimm_addr[dimm_num], 2)) == 0x08)
2185 num_ranks = (num_ranks & 0x0F) + 1;
2187 num_ranks = num_ranks & 0x0F;
2189 rank_size_id = spd_read(iic0_dimm_addr[dimm_num], 31);
2191 /*------------------------------------------------------------------
2193 *-----------------------------------------------------------------*/
2195 switch (rank_size_id) {
2197 baseadd_size |= SDRAM_RXBAS_SDSZ_1024;
2201 baseadd_size |= SDRAM_RXBAS_SDSZ_2048;
2205 baseadd_size |= SDRAM_RXBAS_SDSZ_4096;
2209 baseadd_size |= SDRAM_RXBAS_SDSZ_32;
2213 baseadd_size |= SDRAM_RXBAS_SDSZ_64;
2217 baseadd_size |= SDRAM_RXBAS_SDSZ_128;
2221 baseadd_size |= SDRAM_RXBAS_SDSZ_256;
2225 baseadd_size |= SDRAM_RXBAS_SDSZ_512;
2229 printf("DDR-SDRAM: DIMM %d memory queue configuration.\n",
2230 (unsigned int)dimm_num);
2231 printf("ERROR: Unsupported value for the banksize: %d.\n",
2232 (unsigned int)rank_size_id);
2233 printf("Replace the DIMM module with a supported DIMM.\n\n");
2234 spd_ddr_init_hang ();
2236 rank_size_bytes = total_size << 20;
2238 if ((dimm_populated[dimm_num] != SDRAM_NONE) && (dimm_num == 1))
2239 bank_0_populated = 1;
2241 for (i = 0; i < num_ranks; i++) {
2242 mtdcr_any(rank_reg+i+dimm_num+bank_0_populated,
2243 (SDRAM_RXBAS_SDBA_ENCODE(rank_base_addr) |
2245 rank_base_addr += rank_size_bytes;
2250 #if defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
2251 defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
2252 defined(CONFIG_460SX)
2254 * Enable high bandwidth access
2255 * This is currently not used, but with this setup
2256 * it is possible to use it later on in e.g. the Linux
2257 * EMAC driver for performance gain.
2259 mtdcr(SDRAM_PLBADDULL, 0x00000000); /* MQ0_BAUL */
2260 mtdcr(SDRAM_PLBADDUHB, 0x00000008); /* MQ0_BAUH */
2263 * Set optimal value for Memory Queue HB/LL Configuration registers
2265 mtdcr(SDRAM_CONF1HB, (mfdcr(SDRAM_CONF1HB) & ~SDRAM_CONF1HB_MASK) |
2266 SDRAM_CONF1HB_AAFR | SDRAM_CONF1HB_RPEN | SDRAM_CONF1HB_RFTE |
2267 SDRAM_CONF1HB_RPLM | SDRAM_CONF1HB_WRCL);
2268 mtdcr(SDRAM_CONF1LL, (mfdcr(SDRAM_CONF1LL) & ~SDRAM_CONF1LL_MASK) |
2269 SDRAM_CONF1LL_AAFR | SDRAM_CONF1LL_RPEN | SDRAM_CONF1LL_RFTE |
2270 SDRAM_CONF1LL_RPLM);
2271 mtdcr(SDRAM_CONFPATHB, mfdcr(SDRAM_CONFPATHB) | SDRAM_CONFPATHB_TPEN);
2275 /*-----------------------------------------------------------------------------+
2277 *-----------------------------------------------------------------------------*/
2278 static unsigned long is_ecc_enabled(void)
2280 unsigned long dimm_num;
2285 /* loop through all the DIMM slots on the board */
2286 for (dimm_num = 0; dimm_num < MAXDIMMS; dimm_num++) {
2287 mfsdram(SDRAM_MCOPT1, val);
2288 ecc = max(ecc, SDRAM_MCOPT1_MCHK_CHK_DECODE(val));
2294 #ifdef CONFIG_DDR_ECC
2295 /*-----------------------------------------------------------------------------+
2297 *-----------------------------------------------------------------------------*/
2298 static void program_ecc(unsigned long *dimm_populated,
2299 unsigned char *iic0_dimm_addr,
2300 unsigned long num_dimm_banks,
2301 unsigned long tlb_word2_i_value)
2303 unsigned long mcopt1;
2304 unsigned long mcopt2;
2305 unsigned long mcstat;
2306 unsigned long dimm_num;
2310 /* loop through all the DIMM slots on the board */
2311 for (dimm_num = 0; dimm_num < MAXDIMMS; dimm_num++) {
2312 /* If a dimm is installed in a particular slot ... */
2313 if (dimm_populated[dimm_num] != SDRAM_NONE)
2314 ecc = max(ecc, spd_read(iic0_dimm_addr[dimm_num], 11));
2319 if (sdram_memsize() > CONFIG_MAX_MEM_MAPPED) {
2320 printf("\nWarning: Can't enable ECC on systems with more than 2GB of SDRAM!\n");
2324 mfsdram(SDRAM_MCOPT1, mcopt1);
2325 mfsdram(SDRAM_MCOPT2, mcopt2);
2327 if ((mcopt1 & SDRAM_MCOPT1_MCHK_MASK) != SDRAM_MCOPT1_MCHK_NON) {
2328 /* DDR controller must be enabled and not in self-refresh. */
2329 mfsdram(SDRAM_MCSTAT, mcstat);
2330 if (((mcopt2 & SDRAM_MCOPT2_DCEN_MASK) == SDRAM_MCOPT2_DCEN_ENABLE)
2331 && ((mcopt2 & SDRAM_MCOPT2_SREN_MASK) == SDRAM_MCOPT2_SREN_EXIT)
2332 && ((mcstat & (SDRAM_MCSTAT_MIC_MASK | SDRAM_MCSTAT_SRMS_MASK))
2333 == (SDRAM_MCSTAT_MIC_COMP | SDRAM_MCSTAT_SRMS_NOT_SF))) {
2335 program_ecc_addr(0, sdram_memsize(), tlb_word2_i_value);
2342 static void wait_ddr_idle(void)
2347 mfsdram(SDRAM_MCSTAT, val);
2348 } while ((val & SDRAM_MCSTAT_IDLE_MASK) == SDRAM_MCSTAT_IDLE_NOT);
2351 /*-----------------------------------------------------------------------------+
2353 *-----------------------------------------------------------------------------*/
2354 static void program_ecc_addr(unsigned long start_address,
2355 unsigned long num_bytes,
2356 unsigned long tlb_word2_i_value)
2358 unsigned long current_address;
2359 unsigned long end_address;
2360 unsigned long address_increment;
2361 unsigned long mcopt1;
2362 char str[] = "ECC generation -";
2363 char slash[] = "\\|/-\\|/-";
2367 current_address = start_address;
2368 mfsdram(SDRAM_MCOPT1, mcopt1);
2369 if ((mcopt1 & SDRAM_MCOPT1_MCHK_MASK) != SDRAM_MCOPT1_MCHK_NON) {
2370 mtsdram(SDRAM_MCOPT1,
2371 (mcopt1 & ~SDRAM_MCOPT1_MCHK_MASK) | SDRAM_MCOPT1_MCHK_GEN);
2377 if (tlb_word2_i_value == TLB_WORD2_I_ENABLE) {
2378 /* ECC bit set method for non-cached memory */
2379 if ((mcopt1 & SDRAM_MCOPT1_DMWD_MASK) == SDRAM_MCOPT1_DMWD_32)
2380 address_increment = 4;
2382 address_increment = 8;
2383 end_address = current_address + num_bytes;
2385 while (current_address < end_address) {
2386 *((unsigned long *)current_address) = 0x00000000;
2387 current_address += address_increment;
2389 if ((loop++ % (2 << 20)) == 0) {
2391 putc(slash[loopi++ % 8]);
2396 /* ECC bit set method for cached memory */
2397 dcbz_area(start_address, num_bytes);
2398 /* Write modified dcache lines back to memory */
2399 clean_dcache_range(start_address, start_address + num_bytes);
2402 blank_string(strlen(str));
2408 /* clear ECC error repoting registers */
2409 mtsdram(SDRAM_ECCCR, 0xffffffff);
2410 mtdcr(0x4c, 0xffffffff);
2412 mtsdram(SDRAM_MCOPT1,
2413 (mcopt1 & ~SDRAM_MCOPT1_MCHK_MASK) | SDRAM_MCOPT1_MCHK_CHK_REP);
2421 #if !defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION)
2422 /*-----------------------------------------------------------------------------+
2423 * program_DQS_calibration.
2424 *-----------------------------------------------------------------------------*/
2425 static void program_DQS_calibration(unsigned long *dimm_populated,
2426 unsigned char *iic0_dimm_addr,
2427 unsigned long num_dimm_banks)
2431 #ifdef HARD_CODED_DQS /* calibration test with hardvalues */
2432 mtsdram(SDRAM_RQDC, 0x80000037);
2433 mtsdram(SDRAM_RDCC, 0x40000000);
2434 mtsdram(SDRAM_RFDC, 0x000001DF);
2438 /*------------------------------------------------------------------
2439 * Program RDCC register
2440 * Read sample cycle auto-update enable
2441 *-----------------------------------------------------------------*/
2443 mfsdram(SDRAM_RDCC, val);
2445 (val & ~(SDRAM_RDCC_RDSS_MASK | SDRAM_RDCC_RSAE_MASK))
2446 | SDRAM_RDCC_RSAE_ENABLE);
2448 /*------------------------------------------------------------------
2449 * Program RQDC register
2450 * Internal DQS delay mechanism enable
2451 *-----------------------------------------------------------------*/
2452 mtsdram(SDRAM_RQDC, (SDRAM_RQDC_RQDE_ENABLE|SDRAM_RQDC_RQFD_ENCODE(0x38)));
2454 /*------------------------------------------------------------------
2455 * Program RFDC register
2456 * Set Feedback Fractional Oversample
2457 * Auto-detect read sample cycle enable
2458 * Set RFOS to 1/4 of memclk cycle (0x3f)
2459 *-----------------------------------------------------------------*/
2460 mfsdram(SDRAM_RFDC, val);
2462 (val & ~(SDRAM_RFDC_ARSE_MASK | SDRAM_RFDC_RFOS_MASK |
2463 SDRAM_RFDC_RFFD_MASK))
2464 | (SDRAM_RFDC_ARSE_ENABLE | SDRAM_RFDC_RFOS_ENCODE(0x3f) |
2465 SDRAM_RFDC_RFFD_ENCODE(0)));
2467 DQS_calibration_process();
2471 static int short_mem_test(void)
2478 phys_size_t base_addr;
2479 u32 test[NUMMEMTESTS][NUMMEMWORDS] = {
2480 {0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
2481 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF},
2482 {0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
2483 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000},
2484 {0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
2485 0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555},
2486 {0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
2487 0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA},
2488 {0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
2489 0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A},
2490 {0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
2491 0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5},
2492 {0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
2493 0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA},
2494 {0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
2495 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55} };
2498 for (bxcr_num = 0; bxcr_num < MAXBXCF; bxcr_num++) {
2499 mfsdram(SDRAM_MB0CF + (bxcr_num << 2), bxcf);
2502 if ((bxcf & SDRAM_BXCF_M_BE_MASK) == SDRAM_BXCF_M_BE_ENABLE) {
2503 /* Bank is enabled */
2506 * Only run test on accessable memory (below 2GB)
2508 base_addr = SDRAM_RXBAS_SDBA_DECODE(mfdcr_any(SDRAM_R0BAS+bxcr_num));
2509 if (base_addr >= CONFIG_MAX_MEM_MAPPED)
2512 /*------------------------------------------------------------------
2513 * Run the short memory test.
2514 *-----------------------------------------------------------------*/
2515 membase = (u32 *)(u32)base_addr;
2517 for (i = 0; i < NUMMEMTESTS; i++) {
2518 for (j = 0; j < NUMMEMWORDS; j++) {
2519 membase[j] = test[i][j];
2520 ppcDcbf((u32)&(membase[j]));
2523 for (l=0; l<NUMLOOPS; l++) {
2524 for (j = 0; j < NUMMEMWORDS; j++) {
2525 if (membase[j] != test[i][j]) {
2526 ppcDcbf((u32)&(membase[j]));
2529 ppcDcbf((u32)&(membase[j]));
2534 } /* if bank enabled */
2535 } /* for bxcf_num */
2540 #ifndef HARD_CODED_DQS
2541 /*-----------------------------------------------------------------------------+
2542 * DQS_calibration_process.
2543 *-----------------------------------------------------------------------------*/
2544 static void DQS_calibration_process(void)
2546 unsigned long rfdc_reg;
2552 unsigned long begin_rqfd[MAXRANKS];
2553 unsigned long begin_rffd[MAXRANKS];
2554 unsigned long end_rqfd[MAXRANKS];
2555 unsigned long end_rffd[MAXRANKS];
2557 unsigned long dlycal;
2558 unsigned long dly_val;
2559 unsigned long max_pass_length;
2560 unsigned long current_pass_length;
2561 unsigned long current_fail_length;
2562 unsigned long current_start;
2564 unsigned char fail_found;
2565 unsigned char pass_found;
2566 #if !defined(CONFIG_DDR_RQDC_FIXED)
2572 char str[] = "Auto calibration -";
2573 char slash[] = "\\|/-\\|/-";
2575 /*------------------------------------------------------------------
2576 * Test to determine the best read clock delay tuning bits.
2578 * Before the DDR controller can be used, the read clock delay needs to be
2579 * set. This is SDRAM_RQDC[RQFD] and SDRAM_RFDC[RFFD].
2580 * This value cannot be hardcoded into the program because it changes
2581 * depending on the board's setup and environment.
2582 * To do this, all delay values are tested to see if they
2583 * work or not. By doing this, you get groups of fails with groups of
2584 * passing values. The idea is to find the start and end of a passing
2585 * window and take the center of it to use as the read clock delay.
2587 * A failure has to be seen first so that when we hit a pass, we know
2588 * that it is truely the start of the window. If we get passing values
2589 * to start off with, we don't know if we are at the start of the window.
2591 * The code assumes that a failure will always be found.
2592 * If a failure is not found, there is no easy way to get the middle
2593 * of the passing window. I guess we can pretty much pick any value
2594 * but some values will be better than others. Since the lowest speed
2595 * we can clock the DDR interface at is 200 MHz (2x 100 MHz PLB speed),
2596 * from experimentation it is safe to say you will always have a failure.
2597 *-----------------------------------------------------------------*/
2599 /* first fix RQDC[RQFD] to an average of 80 degre phase shift to find RFDC[RFFD] */
2600 rqfd_start = 64; /* test-only: don't know if this is the _best_ start value */
2605 mfsdram(SDRAM_RQDC, rqdc_reg);
2606 mtsdram(SDRAM_RQDC, (rqdc_reg & ~SDRAM_RQDC_RQFD_MASK) |
2607 SDRAM_RQDC_RQFD_ENCODE(rqfd_start));
2608 #else /* CONFIG_DDR_RQDC_FIXED */
2610 * On Katmai the complete auto-calibration somehow doesn't seem to
2611 * produce the best results, meaning optimal values for RQFD/RFFD.
2612 * This was discovered by GDA using a high bandwidth scope,
2613 * analyzing the DDR2 signals. GDA provided a fixed value for RQFD,
2614 * so now on Katmai "only" RFFD is auto-calibrated.
2616 mtsdram(SDRAM_RQDC, CONFIG_DDR_RQDC_FIXED);
2617 #endif /* CONFIG_DDR_RQDC_FIXED */
2629 window_found = FALSE;
2631 max_pass_length = 0;
2634 current_pass_length = 0;
2635 current_fail_length = 0;
2637 window_found = FALSE;
2642 * get the delay line calibration register value
2644 mfsdram(SDRAM_DLCR, dlycal);
2645 dly_val = SDRAM_DLYCAL_DLCV_DECODE(dlycal) << 2;
2647 for (rffd = 0; rffd <= SDRAM_RFDC_RFFD_MAX; rffd++) {
2648 mfsdram(SDRAM_RFDC, rfdc_reg);
2649 rfdc_reg &= ~(SDRAM_RFDC_RFFD_MASK);
2651 /*------------------------------------------------------------------
2652 * Set the timing reg for the test.
2653 *-----------------------------------------------------------------*/
2654 mtsdram(SDRAM_RFDC, rfdc_reg | SDRAM_RFDC_RFFD_ENCODE(rffd));
2656 /*------------------------------------------------------------------
2657 * See if the rffd value passed.
2658 *-----------------------------------------------------------------*/
2659 if (short_mem_test()) {
2660 if (fail_found == TRUE) {
2662 if (current_pass_length == 0)
2663 current_start = rffd;
2665 current_fail_length = 0;
2666 current_pass_length++;
2668 if (current_pass_length > max_pass_length) {
2669 max_pass_length = current_pass_length;
2670 max_start = current_start;
2675 current_pass_length = 0;
2676 current_fail_length++;
2678 if (current_fail_length >= (dly_val >> 2)) {
2679 if (fail_found == FALSE) {
2681 } else if (pass_found == TRUE) {
2682 window_found = TRUE;
2689 /*------------------------------------------------------------------
2690 * Set the average RFFD value
2691 *-----------------------------------------------------------------*/
2692 rffd_average = ((max_start + max_end) >> 1);
2694 if (rffd_average < 0)
2697 if (rffd_average > SDRAM_RFDC_RFFD_MAX)
2698 rffd_average = SDRAM_RFDC_RFFD_MAX;
2699 /* now fix RFDC[RFFD] found and find RQDC[RQFD] */
2700 mtsdram(SDRAM_RFDC, rfdc_reg | SDRAM_RFDC_RFFD_ENCODE(rffd_average));
2702 #if !defined(CONFIG_DDR_RQDC_FIXED)
2703 max_pass_length = 0;
2706 current_pass_length = 0;
2707 current_fail_length = 0;
2709 window_found = FALSE;
2713 for (rqfd = 0; rqfd <= SDRAM_RQDC_RQFD_MAX; rqfd++) {
2714 mfsdram(SDRAM_RQDC, rqdc_reg);
2715 rqdc_reg &= ~(SDRAM_RQDC_RQFD_MASK);
2717 /*------------------------------------------------------------------
2718 * Set the timing reg for the test.
2719 *-----------------------------------------------------------------*/
2720 mtsdram(SDRAM_RQDC, rqdc_reg | SDRAM_RQDC_RQFD_ENCODE(rqfd));
2722 /*------------------------------------------------------------------
2723 * See if the rffd value passed.
2724 *-----------------------------------------------------------------*/
2725 if (short_mem_test()) {
2726 if (fail_found == TRUE) {
2728 if (current_pass_length == 0)
2729 current_start = rqfd;
2731 current_fail_length = 0;
2732 current_pass_length++;
2734 if (current_pass_length > max_pass_length) {
2735 max_pass_length = current_pass_length;
2736 max_start = current_start;
2741 current_pass_length = 0;
2742 current_fail_length++;
2744 if (fail_found == FALSE) {
2746 } else if (pass_found == TRUE) {
2747 window_found = TRUE;
2753 rqfd_average = ((max_start + max_end) >> 1);
2755 /*------------------------------------------------------------------
2756 * Make sure we found the valid read passing window. Halt if not
2757 *-----------------------------------------------------------------*/
2758 if (window_found == FALSE) {
2759 if (rqfd_start < SDRAM_RQDC_RQFD_MAX) {
2761 putc(slash[loopi++ % 8]);
2763 /* try again from with a different RQFD start value */
2765 goto calibration_loop;
2768 printf("\nERROR: Cannot determine a common read delay for the "
2769 "DIMM(s) installed.\n");
2770 debug("%s[%d] ERROR : \n", __FUNCTION__,__LINE__);
2771 ppc4xx_ibm_ddr2_register_dump();
2772 spd_ddr_init_hang ();
2775 if (rqfd_average < 0)
2778 if (rqfd_average > SDRAM_RQDC_RQFD_MAX)
2779 rqfd_average = SDRAM_RQDC_RQFD_MAX;
2782 (rqdc_reg & ~SDRAM_RQDC_RQFD_MASK) |
2783 SDRAM_RQDC_RQFD_ENCODE(rqfd_average));
2785 blank_string(strlen(str));
2786 #endif /* CONFIG_DDR_RQDC_FIXED */
2789 * Now complete RDSS configuration as mentioned on page 7 of the AMCC
2790 * PowerPC440SP/SPe DDR2 application note:
2791 * "DDR1/DDR2 Initialization Sequence and Dynamic Tuning"
2793 mfsdram(SDRAM_RTSR, val);
2794 if ((val & SDRAM_RTSR_TRK1SM_MASK) == SDRAM_RTSR_TRK1SM_ATPLS1) {
2795 mfsdram(SDRAM_RDCC, val);
2796 if ((val & SDRAM_RDCC_RDSS_MASK) != SDRAM_RDCC_RDSS_T4) {
2798 mtsdram(SDRAM_RDCC, val);
2802 mfsdram(SDRAM_DLCR, val);
2803 debug("%s[%d] DLCR: 0x%08X\n", __FUNCTION__, __LINE__, val);
2804 mfsdram(SDRAM_RQDC, val);
2805 debug("%s[%d] RQDC: 0x%08X\n", __FUNCTION__, __LINE__, val);
2806 mfsdram(SDRAM_RFDC, val);
2807 debug("%s[%d] RFDC: 0x%08X\n", __FUNCTION__, __LINE__, val);
2808 mfsdram(SDRAM_RDCC, val);
2809 debug("%s[%d] RDCC: 0x%08X\n", __FUNCTION__, __LINE__, val);
2811 #else /* calibration test with hardvalues */
2812 /*-----------------------------------------------------------------------------+
2813 * DQS_calibration_process.
2814 *-----------------------------------------------------------------------------*/
2815 static void test(void)
2817 unsigned long dimm_num;
2818 unsigned long ecc_temp;
2820 unsigned long *membase;
2821 unsigned long bxcf[MAXRANKS];
2824 char begin_found[MAXDIMMS];
2825 char end_found[MAXDIMMS];
2826 char search_end[MAXDIMMS];
2827 unsigned long test[NUMMEMTESTS][NUMMEMWORDS] = {
2828 {0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
2829 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF},
2830 {0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
2831 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000},
2832 {0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
2833 0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555},
2834 {0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
2835 0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA},
2836 {0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
2837 0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A},
2838 {0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
2839 0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5},
2840 {0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
2841 0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA},
2842 {0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
2843 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55} };
2845 /*------------------------------------------------------------------
2846 * Test to determine the best read clock delay tuning bits.
2848 * Before the DDR controller can be used, the read clock delay needs to be
2849 * set. This is SDRAM_RQDC[RQFD] and SDRAM_RFDC[RFFD].
2850 * This value cannot be hardcoded into the program because it changes
2851 * depending on the board's setup and environment.
2852 * To do this, all delay values are tested to see if they
2853 * work or not. By doing this, you get groups of fails with groups of
2854 * passing values. The idea is to find the start and end of a passing
2855 * window and take the center of it to use as the read clock delay.
2857 * A failure has to be seen first so that when we hit a pass, we know
2858 * that it is truely the start of the window. If we get passing values
2859 * to start off with, we don't know if we are at the start of the window.
2861 * The code assumes that a failure will always be found.
2862 * If a failure is not found, there is no easy way to get the middle
2863 * of the passing window. I guess we can pretty much pick any value
2864 * but some values will be better than others. Since the lowest speed
2865 * we can clock the DDR interface at is 200 MHz (2x 100 MHz PLB speed),
2866 * from experimentation it is safe to say you will always have a failure.
2867 *-----------------------------------------------------------------*/
2868 mfsdram(SDRAM_MCOPT1, ecc_temp);
2869 ecc_temp &= SDRAM_MCOPT1_MCHK_MASK;
2870 mfsdram(SDRAM_MCOPT1, val);
2871 mtsdram(SDRAM_MCOPT1, (val & ~SDRAM_MCOPT1_MCHK_MASK) |
2872 SDRAM_MCOPT1_MCHK_NON);
2874 window_found = FALSE;
2875 begin_found[0] = FALSE;
2876 end_found[0] = FALSE;
2877 search_end[0] = FALSE;
2878 begin_found[1] = FALSE;
2879 end_found[1] = FALSE;
2880 search_end[1] = FALSE;
2882 for (dimm_num = 0; dimm_num < MAXDIMMS; dimm_num++) {
2883 mfsdram(SDRAM_MB0CF + (bxcr_num << 2), bxcf[bxcr_num]);
2886 if ((bxcf[dimm_num] & SDRAM_BXCF_M_BE_MASK) == SDRAM_BXCF_M_BE_ENABLE) {
2888 /* Bank is enabled */
2890 (unsigned long*)(SDRAM_RXBAS_SDBA_DECODE(mfdcr_any(SDRAM_R0BAS+dimm_num)));
2892 /*------------------------------------------------------------------
2893 * Run the short memory test.
2894 *-----------------------------------------------------------------*/
2895 for (i = 0; i < NUMMEMTESTS; i++) {
2896 for (j = 0; j < NUMMEMWORDS; j++) {
2897 membase[j] = test[i][j];
2898 ppcDcbf((u32)&(membase[j]));
2901 for (j = 0; j < NUMMEMWORDS; j++) {
2902 if (membase[j] != test[i][j]) {
2903 ppcDcbf((u32)&(membase[j]));
2906 ppcDcbf((u32)&(membase[j]));
2909 if (j < NUMMEMWORDS)
2913 /*------------------------------------------------------------------
2914 * See if the rffd value passed.
2915 *-----------------------------------------------------------------*/
2916 if (i < NUMMEMTESTS) {
2917 if ((end_found[dimm_num] == FALSE) &&
2918 (search_end[dimm_num] == TRUE)) {
2919 end_found[dimm_num] = TRUE;
2921 if ((end_found[0] == TRUE) &&
2922 (end_found[1] == TRUE))
2925 if (begin_found[dimm_num] == FALSE) {
2926 begin_found[dimm_num] = TRUE;
2927 search_end[dimm_num] = TRUE;
2931 begin_found[dimm_num] = TRUE;
2932 end_found[dimm_num] = TRUE;
2936 if ((begin_found[0] == TRUE) && (begin_found[1] == TRUE))
2937 window_found = TRUE;
2939 /*------------------------------------------------------------------
2940 * Make sure we found the valid read passing window. Halt if not
2941 *-----------------------------------------------------------------*/
2942 if (window_found == FALSE) {
2943 printf("ERROR: Cannot determine a common read delay for the "
2944 "DIMM(s) installed.\n");
2945 spd_ddr_init_hang ();
2948 /*------------------------------------------------------------------
2949 * Restore the ECC variable to what it originally was
2950 *-----------------------------------------------------------------*/
2951 mtsdram(SDRAM_MCOPT1,
2952 (ppcMfdcr_sdram(SDRAM_MCOPT1) & ~SDRAM_MCOPT1_MCHK_MASK)
2955 #endif /* !HARD_CODED_DQS */
2956 #endif /* !defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION) */
2958 #else /* CONFIG_SPD_EEPROM */
2960 /*-----------------------------------------------------------------------------
2961 * Function: initdram
2962 * Description: Configures the PPC4xx IBM DDR1/DDR2 SDRAM memory controller.
2963 * The configuration is performed using static, compile-
2965 * Configures the PPC405EX(r) and PPC460EX/GT
2966 *---------------------------------------------------------------------------*/
2967 phys_size_t initdram(int board_type)
2970 * Only run this SDRAM init code once. For NAND booting
2971 * targets like Kilauea, we call initdram() early from the
2972 * 4k NAND booting image (CONFIG_NAND_SPL) from nand_boot().
2973 * Later on the NAND U-Boot image runs (CONFIG_NAND_U_BOOT)
2974 * which calls initdram() again. This time the controller
2975 * mustn't be reconfigured again since we're already running
2978 #if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
2981 #if defined(CONFIG_440)
2982 mtdcr(SDRAM_R0BAS, CONFIG_SYS_SDRAM_R0BAS);
2983 mtdcr(SDRAM_R1BAS, CONFIG_SYS_SDRAM_R1BAS);
2984 mtdcr(SDRAM_R2BAS, CONFIG_SYS_SDRAM_R2BAS);
2985 mtdcr(SDRAM_R3BAS, CONFIG_SYS_SDRAM_R3BAS);
2986 mtdcr(SDRAM_PLBADDULL, CONFIG_SYS_SDRAM_PLBADDULL); /* MQ0_BAUL */
2987 mtdcr(SDRAM_PLBADDUHB, CONFIG_SYS_SDRAM_PLBADDUHB); /* MQ0_BAUH */
2988 mtdcr(SDRAM_CONF1LL, CONFIG_SYS_SDRAM_CONF1LL);
2989 mtdcr(SDRAM_CONF1HB, CONFIG_SYS_SDRAM_CONF1HB);
2990 mtdcr(SDRAM_CONFPATHB, CONFIG_SYS_SDRAM_CONFPATHB);
2993 /* Set Memory Bank Configuration Registers */
2995 mtsdram(SDRAM_MB0CF, CONFIG_SYS_SDRAM0_MB0CF);
2996 mtsdram(SDRAM_MB1CF, CONFIG_SYS_SDRAM0_MB1CF);
2997 mtsdram(SDRAM_MB2CF, CONFIG_SYS_SDRAM0_MB2CF);
2998 mtsdram(SDRAM_MB3CF, CONFIG_SYS_SDRAM0_MB3CF);
3000 /* Set Memory Clock Timing Register */
3002 mtsdram(SDRAM_CLKTR, CONFIG_SYS_SDRAM0_CLKTR);
3004 /* Set Refresh Time Register */
3006 mtsdram(SDRAM_RTR, CONFIG_SYS_SDRAM0_RTR);
3008 /* Set SDRAM Timing Registers */
3010 mtsdram(SDRAM_SDTR1, CONFIG_SYS_SDRAM0_SDTR1);
3011 mtsdram(SDRAM_SDTR2, CONFIG_SYS_SDRAM0_SDTR2);
3012 mtsdram(SDRAM_SDTR3, CONFIG_SYS_SDRAM0_SDTR3);
3014 /* Set Mode and Extended Mode Registers */
3016 mtsdram(SDRAM_MMODE, CONFIG_SYS_SDRAM0_MMODE);
3017 mtsdram(SDRAM_MEMODE, CONFIG_SYS_SDRAM0_MEMODE);
3019 /* Set Memory Controller Options 1 Register */
3021 mtsdram(SDRAM_MCOPT1, CONFIG_SYS_SDRAM0_MCOPT1);
3023 /* Set Manual Initialization Control Registers */
3025 mtsdram(SDRAM_INITPLR0, CONFIG_SYS_SDRAM0_INITPLR0);
3026 mtsdram(SDRAM_INITPLR1, CONFIG_SYS_SDRAM0_INITPLR1);
3027 mtsdram(SDRAM_INITPLR2, CONFIG_SYS_SDRAM0_INITPLR2);
3028 mtsdram(SDRAM_INITPLR3, CONFIG_SYS_SDRAM0_INITPLR3);
3029 mtsdram(SDRAM_INITPLR4, CONFIG_SYS_SDRAM0_INITPLR4);
3030 mtsdram(SDRAM_INITPLR5, CONFIG_SYS_SDRAM0_INITPLR5);
3031 mtsdram(SDRAM_INITPLR6, CONFIG_SYS_SDRAM0_INITPLR6);
3032 mtsdram(SDRAM_INITPLR7, CONFIG_SYS_SDRAM0_INITPLR7);
3033 mtsdram(SDRAM_INITPLR8, CONFIG_SYS_SDRAM0_INITPLR8);
3034 mtsdram(SDRAM_INITPLR9, CONFIG_SYS_SDRAM0_INITPLR9);
3035 mtsdram(SDRAM_INITPLR10, CONFIG_SYS_SDRAM0_INITPLR10);
3036 mtsdram(SDRAM_INITPLR11, CONFIG_SYS_SDRAM0_INITPLR11);
3037 mtsdram(SDRAM_INITPLR12, CONFIG_SYS_SDRAM0_INITPLR12);
3038 mtsdram(SDRAM_INITPLR13, CONFIG_SYS_SDRAM0_INITPLR13);
3039 mtsdram(SDRAM_INITPLR14, CONFIG_SYS_SDRAM0_INITPLR14);
3040 mtsdram(SDRAM_INITPLR15, CONFIG_SYS_SDRAM0_INITPLR15);
3042 /* Set On-Die Termination Registers */
3044 mtsdram(SDRAM_CODT, CONFIG_SYS_SDRAM0_CODT);
3045 mtsdram(SDRAM_MODT0, CONFIG_SYS_SDRAM0_MODT0);
3046 mtsdram(SDRAM_MODT1, CONFIG_SYS_SDRAM0_MODT1);
3048 /* Set Write Timing Register */
3050 mtsdram(SDRAM_WRDTR, CONFIG_SYS_SDRAM0_WRDTR);
3053 * Start Initialization by SDRAM0_MCOPT2[SREN] = 0 and
3054 * SDRAM0_MCOPT2[IPTR] = 1
3057 mtsdram(SDRAM_MCOPT2, (SDRAM_MCOPT2_SREN_EXIT |
3058 SDRAM_MCOPT2_IPTR_EXECUTE));
3061 * Poll SDRAM0_MCSTAT[MIC] for assertion to indicate the
3062 * completion of initialization.
3066 mfsdram(SDRAM_MCSTAT, val);
3067 } while ((val & SDRAM_MCSTAT_MIC_MASK) != SDRAM_MCSTAT_MIC_COMP);
3069 /* Set Delay Control Registers */
3071 mtsdram(SDRAM_DLCR, CONFIG_SYS_SDRAM0_DLCR);
3073 #if !defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION)
3074 mtsdram(SDRAM_RDCC, CONFIG_SYS_SDRAM0_RDCC);
3075 mtsdram(SDRAM_RQDC, CONFIG_SYS_SDRAM0_RQDC);
3076 mtsdram(SDRAM_RFDC, CONFIG_SYS_SDRAM0_RFDC);
3077 #endif /* !CONFIG_PPC4xx_DDR_AUTOCALIBRATION */
3080 * Enable Controller by SDRAM0_MCOPT2[DCEN] = 1:
3083 mfsdram(SDRAM_MCOPT2, val);
3084 mtsdram(SDRAM_MCOPT2, val | SDRAM_MCOPT2_DCEN_ENABLE);
3086 #if defined(CONFIG_440)
3088 * Program TLB entries with caches enabled, for best performace
3089 * while auto-calibrating and ECC generation
3091 program_tlb(0, 0, (CONFIG_SYS_MBYTES_SDRAM << 20), 0);
3094 #if defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION)
3095 #if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
3096 /*------------------------------------------------------------------
3098 +-----------------------------------------------------------------*/
3099 DQS_autocalibration();
3100 #endif /* !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) */
3101 #endif /* CONFIG_PPC4xx_DDR_AUTOCALIBRATION */
3103 #if defined(CONFIG_DDR_ECC)
3104 ecc_init(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MBYTES_SDRAM << 20);
3105 #endif /* defined(CONFIG_DDR_ECC) */
3107 #if defined(CONFIG_440)
3109 * Now after initialization (auto-calibration and ECC generation)
3110 * remove the TLB entries with caches enabled and program again with
3111 * desired cache functionality
3113 remove_tlb(0, (CONFIG_SYS_MBYTES_SDRAM << 20));
3114 program_tlb(0, 0, (CONFIG_SYS_MBYTES_SDRAM << 20), MY_TLB_WORD2_I_ENABLE);
3117 ppc4xx_ibm_ddr2_register_dump();
3119 #if defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION)
3121 * Clear potential errors resulting from auto-calibration.
3122 * If not done, then we could get an interrupt later on when
3123 * exceptions are enabled.
3125 set_mcsr(get_mcsr());
3126 #endif /* CONFIG_PPC4xx_DDR_AUTOCALIBRATION */
3128 #endif /* !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) */
3130 return (CONFIG_SYS_MBYTES_SDRAM << 20);
3132 #endif /* CONFIG_SPD_EEPROM */
3134 #if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
3135 #if defined(CONFIG_440)
3136 u32 mfdcr_any(u32 dcr)
3141 case SDRAM_R0BAS + 0:
3142 val = mfdcr(SDRAM_R0BAS + 0);
3144 case SDRAM_R0BAS + 1:
3145 val = mfdcr(SDRAM_R0BAS + 1);
3147 case SDRAM_R0BAS + 2:
3148 val = mfdcr(SDRAM_R0BAS + 2);
3150 case SDRAM_R0BAS + 3:
3151 val = mfdcr(SDRAM_R0BAS + 3);
3154 printf("DCR %d not defined in case statement!!!\n", dcr);
3155 val = 0; /* just to satisfy the compiler */
3161 void mtdcr_any(u32 dcr, u32 val)
3164 case SDRAM_R0BAS + 0:
3165 mtdcr(SDRAM_R0BAS + 0, val);
3167 case SDRAM_R0BAS + 1:
3168 mtdcr(SDRAM_R0BAS + 1, val);
3170 case SDRAM_R0BAS + 2:
3171 mtdcr(SDRAM_R0BAS + 2, val);
3173 case SDRAM_R0BAS + 3:
3174 mtdcr(SDRAM_R0BAS + 3, val);
3177 printf("DCR %d not defined in case statement!!!\n", dcr);
3180 #endif /* defined(CONFIG_440) */
3182 void blank_string(int size)
3186 for (i = 0; i < size; i++)
3188 for (i = 0; i < size; i++)
3190 for (i = 0; i < size; i++)
3193 #endif /* !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) */
3195 inline void ppc4xx_ibm_ddr2_register_dump(void)
3198 printf("\nPPC4xx IBM DDR2 Register Dump:\n");
3200 #if (defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
3201 defined(CONFIG_460EX) || defined(CONFIG_460GT))
3202 PPC4xx_IBM_DDR2_DUMP_REGISTER(R0BAS);
3203 PPC4xx_IBM_DDR2_DUMP_REGISTER(R1BAS);
3204 PPC4xx_IBM_DDR2_DUMP_REGISTER(R2BAS);
3205 PPC4xx_IBM_DDR2_DUMP_REGISTER(R3BAS);
3206 #endif /* (defined(CONFIG_440SP) || ... */
3207 #if defined(CONFIG_405EX)
3208 PPC4xx_IBM_DDR2_DUMP_REGISTER(BESR);
3209 PPC4xx_IBM_DDR2_DUMP_REGISTER(BEARL);
3210 PPC4xx_IBM_DDR2_DUMP_REGISTER(BEARH);
3211 PPC4xx_IBM_DDR2_DUMP_REGISTER(WMIRQ);
3212 PPC4xx_IBM_DDR2_DUMP_REGISTER(PLBOPT);
3213 PPC4xx_IBM_DDR2_DUMP_REGISTER(PUABA);
3214 #endif /* defined(CONFIG_405EX) */
3215 PPC4xx_IBM_DDR2_DUMP_REGISTER(MB0CF);
3216 PPC4xx_IBM_DDR2_DUMP_REGISTER(MB1CF);
3217 PPC4xx_IBM_DDR2_DUMP_REGISTER(MB2CF);
3218 PPC4xx_IBM_DDR2_DUMP_REGISTER(MB3CF);
3219 PPC4xx_IBM_DDR2_DUMP_REGISTER(MCSTAT);
3220 PPC4xx_IBM_DDR2_DUMP_REGISTER(MCOPT1);
3221 PPC4xx_IBM_DDR2_DUMP_REGISTER(MCOPT2);
3222 PPC4xx_IBM_DDR2_DUMP_REGISTER(MODT0);
3223 PPC4xx_IBM_DDR2_DUMP_REGISTER(MODT1);
3224 PPC4xx_IBM_DDR2_DUMP_REGISTER(MODT2);
3225 PPC4xx_IBM_DDR2_DUMP_REGISTER(MODT3);
3226 PPC4xx_IBM_DDR2_DUMP_REGISTER(CODT);
3227 #if (defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
3228 defined(CONFIG_460EX) || defined(CONFIG_460GT))
3229 PPC4xx_IBM_DDR2_DUMP_REGISTER(VVPR);
3230 PPC4xx_IBM_DDR2_DUMP_REGISTER(OPARS);
3232 * OPART is only used as a trigger register.
3234 * No data is contained in this register, and reading or writing
3235 * to is can cause bad things to happen (hangs). Just skip it and
3238 printf("%20s = N/A\n", "SDRAM_OPART");
3239 #endif /* defined(CONFIG_440SP) || ... */
3240 PPC4xx_IBM_DDR2_DUMP_REGISTER(RTR);
3241 PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR0);
3242 PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR1);
3243 PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR2);
3244 PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR3);
3245 PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR4);
3246 PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR5);
3247 PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR6);
3248 PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR7);
3249 PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR8);
3250 PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR9);
3251 PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR10);
3252 PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR11);
3253 PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR12);
3254 PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR13);
3255 PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR14);
3256 PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR15);
3257 PPC4xx_IBM_DDR2_DUMP_REGISTER(RQDC);
3258 PPC4xx_IBM_DDR2_DUMP_REGISTER(RFDC);
3259 PPC4xx_IBM_DDR2_DUMP_REGISTER(RDCC);
3260 PPC4xx_IBM_DDR2_DUMP_REGISTER(DLCR);
3261 PPC4xx_IBM_DDR2_DUMP_REGISTER(CLKTR);
3262 PPC4xx_IBM_DDR2_DUMP_REGISTER(WRDTR);
3263 PPC4xx_IBM_DDR2_DUMP_REGISTER(SDTR1);
3264 PPC4xx_IBM_DDR2_DUMP_REGISTER(SDTR2);
3265 PPC4xx_IBM_DDR2_DUMP_REGISTER(SDTR3);
3266 PPC4xx_IBM_DDR2_DUMP_REGISTER(MMODE);
3267 PPC4xx_IBM_DDR2_DUMP_REGISTER(MEMODE);
3268 PPC4xx_IBM_DDR2_DUMP_REGISTER(ECCCR);
3269 #if (defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
3270 defined(CONFIG_460EX) || defined(CONFIG_460GT))
3271 PPC4xx_IBM_DDR2_DUMP_REGISTER(CID);
3272 #endif /* defined(CONFIG_440SP) || ... */
3273 PPC4xx_IBM_DDR2_DUMP_REGISTER(RID);
3274 PPC4xx_IBM_DDR2_DUMP_REGISTER(FCSR);
3275 PPC4xx_IBM_DDR2_DUMP_REGISTER(RTSR);
3276 #endif /* defined(DEBUG) */
3279 #endif /* CONFIG_SDRAM_PPC4xx_IBM_DDR2 */