2 * cpu/ppc4xx/44x_spd_ddr2.c
3 * This SPD SDRAM detection code supports AMCC PPC44x cpu's with a
4 * DDR2 controller (non Denali Core). Those currently are:
7 * 440/460: 440SP/440SPe/460EX/460GT
9 * Copyright (c) 2008 Nuovation System Designs, LLC
10 * Grant Erickson <gerickson@nuovations.com>
12 * (C) Copyright 2007-2008
13 * Stefan Roese, DENX Software Engineering, sr@denx.de.
15 * COPYRIGHT AMCC CORPORATION 2004
17 * See file CREDITS for list of people who contributed to this
20 * This program is free software; you can redistribute it and/or
21 * modify it under the terms of the GNU General Public License as
22 * published by the Free Software Foundation; either version 2 of
23 * the License, or (at your option) any later version.
25 * This program is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU General Public License for more details.
30 * You should have received a copy of the GNU General Public License
31 * along with this program; if not, write to the Free Software
32 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
37 /* define DEBUG for debugging output (obviously ;-)) */
47 #include <asm/processor.h>
49 #include <asm/cache.h>
53 #if defined(CONFIG_SDRAM_PPC4xx_IBM_DDR2)
55 #define PPC4xx_IBM_DDR2_DUMP_REGISTER(mnemonic) \
58 mfsdram(SDRAM_##mnemonic, data); \
59 printf("%20s[%02x] = 0x%08X\n", \
60 "SDRAM_" #mnemonic, SDRAM_##mnemonic, data); \
63 #if defined(CONFIG_440)
65 * This DDR2 setup code can dynamically setup the TLB entries for the DDR2
66 * memory region. Right now the cache should still be disabled in U-Boot
67 * because of the EMAC driver, that need its buffer descriptor to be located
68 * in non cached memory.
70 * If at some time this restriction doesn't apply anymore, just define
71 * CONFIG_4xx_DCACHE in the board config file and this code should setup
72 * everything correctly.
74 #ifdef CONFIG_4xx_DCACHE
75 /* enable caching on SDRAM */
76 #define MY_TLB_WORD2_I_ENABLE 0
78 /* disable caching on SDRAM */
79 #define MY_TLB_WORD2_I_ENABLE TLB_WORD2_I_ENABLE
80 #endif /* CONFIG_4xx_DCACHE */
81 #endif /* CONFIG_440 */
83 #if defined(CONFIG_SPD_EEPROM)
85 /*-----------------------------------------------------------------------------+
87 *-----------------------------------------------------------------------------*/
102 #define MAX_SPD_BYTES 256 /* Max number of bytes on the DIMM's SPD EEPROM */
104 #define ONE_BILLION 1000000000
106 #define MULDIV64(m1, m2, d) (u32)(((u64)(m1) * (u64)(m2)) / (u64)(d))
108 #define CMD_NOP (7 << 19)
109 #define CMD_PRECHARGE (2 << 19)
110 #define CMD_REFRESH (1 << 19)
111 #define CMD_EMR (0 << 19)
112 #define CMD_READ (5 << 19)
113 #define CMD_WRITE (4 << 19)
115 #define SELECT_MR (0 << 16)
116 #define SELECT_EMR (1 << 16)
117 #define SELECT_EMR2 (2 << 16)
118 #define SELECT_EMR3 (3 << 16)
121 #define DLL_RESET 0x00000100
123 #define WRITE_RECOV_2 (1 << 9)
124 #define WRITE_RECOV_3 (2 << 9)
125 #define WRITE_RECOV_4 (3 << 9)
126 #define WRITE_RECOV_5 (4 << 9)
127 #define WRITE_RECOV_6 (5 << 9)
129 #define BURST_LEN_4 0x00000002
132 #define ODT_0_OHM 0x00000000
133 #define ODT_50_OHM 0x00000044
134 #define ODT_75_OHM 0x00000004
135 #define ODT_150_OHM 0x00000040
137 #define ODS_FULL 0x00000000
138 #define ODS_REDUCED 0x00000002
139 #define OCD_CALIB_DEF 0x00000380
141 /* defines for ODT (On Die Termination) of the 440SP(e) DDR2 controller */
142 #define ODT_EB0R (0x80000000 >> 8)
143 #define ODT_EB0W (0x80000000 >> 7)
144 #define CALC_ODT_R(n) (ODT_EB0R << (n << 1))
145 #define CALC_ODT_W(n) (ODT_EB0W << (n << 1))
146 #define CALC_ODT_RW(n) (CALC_ODT_R(n) | CALC_ODT_W(n))
148 /* Defines for the Read Cycle Delay test */
149 #define NUMMEMTESTS 8
150 #define NUMMEMWORDS 8
151 #define NUMLOOPS 64 /* memory test loops */
154 * Newer PPC's like 440SPe, 460EX/GT can be equipped with more than 2GB of SDRAM.
155 * To support such configurations, we "only" map the first 2GB via the TLB's. We
156 * need some free virtual address space for the remaining peripherals like, SoC
157 * devices, FLASH etc.
159 * Note that ECC is currently not supported on configurations with more than 2GB
160 * SDRAM. This is because we only map the first 2GB on such systems, and therefore
161 * the ECC parity byte of the remaining area can't be written.
163 #ifndef CONFIG_MAX_MEM_MAPPED
164 #define CONFIG_MAX_MEM_MAPPED ((phys_size_t)2 << 30)
168 * Board-specific Platform code can reimplement spd_ddr_init_hang () if needed
170 void __spd_ddr_init_hang (void)
174 void spd_ddr_init_hang (void) __attribute__((weak, alias("__spd_ddr_init_hang")));
177 * To provide an interface for board specific config values in this common
178 * DDR setup code, we implement he "weak" default functions here. They return
179 * the default value back to the caller.
181 * Please see include/configs/yucca.h for an example fora board specific
184 u32 __ddr_wrdtr(u32 default_val)
188 u32 ddr_wrdtr(u32) __attribute__((weak, alias("__ddr_wrdtr")));
190 u32 __ddr_clktr(u32 default_val)
194 u32 ddr_clktr(u32) __attribute__((weak, alias("__ddr_clktr")));
197 /* Private Structure Definitions */
199 /* enum only to ease code for cas latency setting */
200 typedef enum ddr_cas_id {
208 /*-----------------------------------------------------------------------------+
210 *-----------------------------------------------------------------------------*/
211 static phys_size_t sdram_memsize(void);
212 static void get_spd_info(unsigned long *dimm_populated,
213 unsigned char *iic0_dimm_addr,
214 unsigned long num_dimm_banks);
215 static void check_mem_type(unsigned long *dimm_populated,
216 unsigned char *iic0_dimm_addr,
217 unsigned long num_dimm_banks);
218 static void check_frequency(unsigned long *dimm_populated,
219 unsigned char *iic0_dimm_addr,
220 unsigned long num_dimm_banks);
221 static void check_rank_number(unsigned long *dimm_populated,
222 unsigned char *iic0_dimm_addr,
223 unsigned long num_dimm_banks);
224 static void check_voltage_type(unsigned long *dimm_populated,
225 unsigned char *iic0_dimm_addr,
226 unsigned long num_dimm_banks);
227 static void program_memory_queue(unsigned long *dimm_populated,
228 unsigned char *iic0_dimm_addr,
229 unsigned long num_dimm_banks);
230 static void program_codt(unsigned long *dimm_populated,
231 unsigned char *iic0_dimm_addr,
232 unsigned long num_dimm_banks);
233 static void program_mode(unsigned long *dimm_populated,
234 unsigned char *iic0_dimm_addr,
235 unsigned long num_dimm_banks,
236 ddr_cas_id_t *selected_cas,
237 int *write_recovery);
238 static void program_tr(unsigned long *dimm_populated,
239 unsigned char *iic0_dimm_addr,
240 unsigned long num_dimm_banks);
241 static void program_rtr(unsigned long *dimm_populated,
242 unsigned char *iic0_dimm_addr,
243 unsigned long num_dimm_banks);
244 static void program_bxcf(unsigned long *dimm_populated,
245 unsigned char *iic0_dimm_addr,
246 unsigned long num_dimm_banks);
247 static void program_copt1(unsigned long *dimm_populated,
248 unsigned char *iic0_dimm_addr,
249 unsigned long num_dimm_banks);
250 static void program_initplr(unsigned long *dimm_populated,
251 unsigned char *iic0_dimm_addr,
252 unsigned long num_dimm_banks,
253 ddr_cas_id_t selected_cas,
255 static unsigned long is_ecc_enabled(void);
256 #ifdef CONFIG_DDR_ECC
257 static void program_ecc(unsigned long *dimm_populated,
258 unsigned char *iic0_dimm_addr,
259 unsigned long num_dimm_banks,
260 unsigned long tlb_word2_i_value);
261 static void program_ecc_addr(unsigned long start_address,
262 unsigned long num_bytes,
263 unsigned long tlb_word2_i_value);
265 #if !defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION)
266 static void program_DQS_calibration(unsigned long *dimm_populated,
267 unsigned char *iic0_dimm_addr,
268 unsigned long num_dimm_banks);
269 #ifdef HARD_CODED_DQS /* calibration test with hardvalues */
270 static void test(void);
272 static void DQS_calibration_process(void);
275 int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
276 void dcbz_area(u32 start_address, u32 num_bytes);
278 static unsigned char spd_read(uchar chip, uint addr)
280 unsigned char data[2];
282 if (i2c_probe(chip) == 0)
283 if (i2c_read(chip, addr, 1, data, 1) == 0)
289 /*-----------------------------------------------------------------------------+
291 *-----------------------------------------------------------------------------*/
292 static phys_size_t sdram_memsize(void)
294 phys_size_t mem_size;
295 unsigned long mcopt2;
296 unsigned long mcstat;
303 mfsdram(SDRAM_MCOPT2, mcopt2);
304 mfsdram(SDRAM_MCSTAT, mcstat);
306 /* DDR controller must be enabled and not in self-refresh. */
307 /* Otherwise memsize is zero. */
308 if (((mcopt2 & SDRAM_MCOPT2_DCEN_MASK) == SDRAM_MCOPT2_DCEN_ENABLE)
309 && ((mcopt2 & SDRAM_MCOPT2_SREN_MASK) == SDRAM_MCOPT2_SREN_EXIT)
310 && ((mcstat & (SDRAM_MCSTAT_MIC_MASK | SDRAM_MCSTAT_SRMS_MASK))
311 == (SDRAM_MCSTAT_MIC_COMP | SDRAM_MCSTAT_SRMS_NOT_SF))) {
312 for (i = 0; i < MAXBXCF; i++) {
313 mfsdram(SDRAM_MB0CF + (i << 2), mb0cf);
315 if ((mb0cf & SDRAM_BXCF_M_BE_MASK) == SDRAM_BXCF_M_BE_ENABLE) {
316 sdsz = mfdcr_any(SDRAM_R0BAS + i) & SDRAM_RXBAS_SDSZ_MASK;
319 case SDRAM_RXBAS_SDSZ_8:
322 case SDRAM_RXBAS_SDSZ_16:
325 case SDRAM_RXBAS_SDSZ_32:
328 case SDRAM_RXBAS_SDSZ_64:
331 case SDRAM_RXBAS_SDSZ_128:
334 case SDRAM_RXBAS_SDSZ_256:
337 case SDRAM_RXBAS_SDSZ_512:
340 case SDRAM_RXBAS_SDSZ_1024:
343 case SDRAM_RXBAS_SDSZ_2048:
346 case SDRAM_RXBAS_SDSZ_4096:
350 printf("WARNING: Unsupported bank size (SDSZ=0x%lx)!\n"
359 return mem_size << 20;
362 /*-----------------------------------------------------------------------------+
363 * initdram. Initializes the 440SP Memory Queue and DDR SDRAM controller.
364 * Note: This routine runs from flash with a stack set up in the chip's
365 * sram space. It is important that the routine does not require .sbss, .bss or
366 * .data sections. It also cannot call routines that require these sections.
367 *-----------------------------------------------------------------------------*/
368 /*-----------------------------------------------------------------------------
370 * Description: Configures SDRAM memory banks for DDR operation.
371 * Auto Memory Configuration option reads the DDR SDRAM EEPROMs
372 * via the IIC bus and then configures the DDR SDRAM memory
373 * banks appropriately. If Auto Memory Configuration is
374 * not used, it is assumed that no DIMM is plugged
375 *-----------------------------------------------------------------------------*/
376 phys_size_t initdram(int board_type)
378 unsigned char iic0_dimm_addr[] = SPD_EEPROM_ADDRESS;
379 unsigned char spd0[MAX_SPD_BYTES];
380 unsigned char spd1[MAX_SPD_BYTES];
381 unsigned char *dimm_spd[MAXDIMMS];
382 unsigned long dimm_populated[MAXDIMMS];
383 unsigned long num_dimm_banks; /* on board dimm banks */
385 ddr_cas_id_t selected_cas = DDR_CAS_5; /* preset to silence compiler */
387 phys_size_t dram_size = 0;
389 num_dimm_banks = sizeof(iic0_dimm_addr);
391 /*------------------------------------------------------------------
392 * Set up an array of SPD matrixes.
393 *-----------------------------------------------------------------*/
397 /*------------------------------------------------------------------
398 * Reset the DDR-SDRAM controller.
399 *-----------------------------------------------------------------*/
400 mtsdr(SDR0_SRST, (0x80000000 >> 10));
401 mtsdr(SDR0_SRST, 0x00000000);
404 * Make sure I2C controller is initialized
408 /* switch to correct I2C bus */
409 I2C_SET_BUS(CONFIG_SYS_SPD_BUS_NUM);
410 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
412 /*------------------------------------------------------------------
413 * Clear out the serial presence detect buffers.
414 * Perform IIC reads from the dimm. Fill in the spds.
415 * Check to see if the dimm slots are populated
416 *-----------------------------------------------------------------*/
417 get_spd_info(dimm_populated, iic0_dimm_addr, num_dimm_banks);
419 /*------------------------------------------------------------------
420 * Check the memory type for the dimms plugged.
421 *-----------------------------------------------------------------*/
422 check_mem_type(dimm_populated, iic0_dimm_addr, num_dimm_banks);
424 /*------------------------------------------------------------------
425 * Check the frequency supported for the dimms plugged.
426 *-----------------------------------------------------------------*/
427 check_frequency(dimm_populated, iic0_dimm_addr, num_dimm_banks);
429 /*------------------------------------------------------------------
430 * Check the total rank number.
431 *-----------------------------------------------------------------*/
432 check_rank_number(dimm_populated, iic0_dimm_addr, num_dimm_banks);
434 /*------------------------------------------------------------------
435 * Check the voltage type for the dimms plugged.
436 *-----------------------------------------------------------------*/
437 check_voltage_type(dimm_populated, iic0_dimm_addr, num_dimm_banks);
439 /*------------------------------------------------------------------
440 * Program SDRAM controller options 2 register
441 * Except Enabling of the memory controller.
442 *-----------------------------------------------------------------*/
443 mfsdram(SDRAM_MCOPT2, val);
444 mtsdram(SDRAM_MCOPT2,
446 ~(SDRAM_MCOPT2_SREN_MASK | SDRAM_MCOPT2_PMEN_MASK |
447 SDRAM_MCOPT2_IPTR_MASK | SDRAM_MCOPT2_XSRP_MASK |
448 SDRAM_MCOPT2_ISIE_MASK))
449 | (SDRAM_MCOPT2_SREN_ENTER | SDRAM_MCOPT2_PMEN_DISABLE |
450 SDRAM_MCOPT2_IPTR_IDLE | SDRAM_MCOPT2_XSRP_ALLOW |
451 SDRAM_MCOPT2_ISIE_ENABLE));
453 /*------------------------------------------------------------------
454 * Program SDRAM controller options 1 register
455 * Note: Does not enable the memory controller.
456 *-----------------------------------------------------------------*/
457 program_copt1(dimm_populated, iic0_dimm_addr, num_dimm_banks);
459 /*------------------------------------------------------------------
460 * Set the SDRAM Controller On Die Termination Register
461 *-----------------------------------------------------------------*/
462 program_codt(dimm_populated, iic0_dimm_addr, num_dimm_banks);
464 /*------------------------------------------------------------------
465 * Program SDRAM refresh register.
466 *-----------------------------------------------------------------*/
467 program_rtr(dimm_populated, iic0_dimm_addr, num_dimm_banks);
469 /*------------------------------------------------------------------
470 * Program SDRAM mode register.
471 *-----------------------------------------------------------------*/
472 program_mode(dimm_populated, iic0_dimm_addr, num_dimm_banks,
473 &selected_cas, &write_recovery);
475 /*------------------------------------------------------------------
476 * Set the SDRAM Write Data/DM/DQS Clock Timing Reg
477 *-----------------------------------------------------------------*/
478 mfsdram(SDRAM_WRDTR, val);
479 mtsdram(SDRAM_WRDTR, (val & ~(SDRAM_WRDTR_LLWP_MASK | SDRAM_WRDTR_WTR_MASK)) |
480 ddr_wrdtr(SDRAM_WRDTR_LLWP_1_CYC | SDRAM_WRDTR_WTR_90_DEG_ADV));
482 /*------------------------------------------------------------------
483 * Set the SDRAM Clock Timing Register
484 *-----------------------------------------------------------------*/
485 mfsdram(SDRAM_CLKTR, val);
486 mtsdram(SDRAM_CLKTR, (val & ~SDRAM_CLKTR_CLKP_MASK) |
487 ddr_clktr(SDRAM_CLKTR_CLKP_0_DEG));
489 /*------------------------------------------------------------------
490 * Program the BxCF registers.
491 *-----------------------------------------------------------------*/
492 program_bxcf(dimm_populated, iic0_dimm_addr, num_dimm_banks);
494 /*------------------------------------------------------------------
495 * Program SDRAM timing registers.
496 *-----------------------------------------------------------------*/
497 program_tr(dimm_populated, iic0_dimm_addr, num_dimm_banks);
499 /*------------------------------------------------------------------
500 * Set the Extended Mode register
501 *-----------------------------------------------------------------*/
502 mfsdram(SDRAM_MEMODE, val);
503 mtsdram(SDRAM_MEMODE,
504 (val & ~(SDRAM_MEMODE_DIC_MASK | SDRAM_MEMODE_DLL_MASK |
505 SDRAM_MEMODE_RTT_MASK | SDRAM_MEMODE_DQS_MASK)) |
506 (SDRAM_MEMODE_DIC_NORMAL | SDRAM_MEMODE_DLL_ENABLE
507 | SDRAM_MEMODE_RTT_150OHM | SDRAM_MEMODE_DQS_ENABLE));
509 /*------------------------------------------------------------------
510 * Program Initialization preload registers.
511 *-----------------------------------------------------------------*/
512 program_initplr(dimm_populated, iic0_dimm_addr, num_dimm_banks,
513 selected_cas, write_recovery);
515 /*------------------------------------------------------------------
516 * Delay to ensure 200usec have elapsed since reset.
517 *-----------------------------------------------------------------*/
520 /*------------------------------------------------------------------
521 * Set the memory queue core base addr.
522 *-----------------------------------------------------------------*/
523 program_memory_queue(dimm_populated, iic0_dimm_addr, num_dimm_banks);
525 /*------------------------------------------------------------------
526 * Program SDRAM controller options 2 register
527 * Enable the memory controller.
528 *-----------------------------------------------------------------*/
529 mfsdram(SDRAM_MCOPT2, val);
530 mtsdram(SDRAM_MCOPT2,
531 (val & ~(SDRAM_MCOPT2_SREN_MASK | SDRAM_MCOPT2_DCEN_MASK |
532 SDRAM_MCOPT2_IPTR_MASK | SDRAM_MCOPT2_ISIE_MASK)) |
533 SDRAM_MCOPT2_IPTR_EXECUTE);
535 /*------------------------------------------------------------------
536 * Wait for IPTR_EXECUTE init sequence to complete.
537 *-----------------------------------------------------------------*/
539 mfsdram(SDRAM_MCSTAT, val);
540 } while ((val & SDRAM_MCSTAT_MIC_MASK) == SDRAM_MCSTAT_MIC_NOTCOMP);
542 /* enable the controller only after init sequence completes */
543 mfsdram(SDRAM_MCOPT2, val);
544 mtsdram(SDRAM_MCOPT2, (val | SDRAM_MCOPT2_DCEN_ENABLE));
546 /* Make sure delay-line calibration is done before proceeding */
548 mfsdram(SDRAM_DLCR, val);
549 } while (!(val & SDRAM_DLCR_DLCS_COMPLETE));
551 /* get installed memory size */
552 dram_size = sdram_memsize();
557 if (dram_size > CONFIG_MAX_MEM_MAPPED)
558 dram_size = CONFIG_MAX_MEM_MAPPED;
560 /* and program tlb entries for this size (dynamic) */
563 * Program TLB entries with caches enabled, for best performace
564 * while auto-calibrating and ECC generation
566 program_tlb(0, 0, dram_size, 0);
568 /*------------------------------------------------------------------
570 *-----------------------------------------------------------------*/
571 #if defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION)
572 DQS_autocalibration();
574 program_DQS_calibration(dimm_populated, iic0_dimm_addr, num_dimm_banks);
577 #ifdef CONFIG_DDR_ECC
578 /*------------------------------------------------------------------
579 * If ecc is enabled, initialize the parity bits.
580 *-----------------------------------------------------------------*/
581 program_ecc(dimm_populated, iic0_dimm_addr, num_dimm_banks, 0);
585 * Now after initialization (auto-calibration and ECC generation)
586 * remove the TLB entries with caches enabled and program again with
587 * desired cache functionality
589 remove_tlb(0, dram_size);
590 program_tlb(0, 0, dram_size, MY_TLB_WORD2_I_ENABLE);
592 ppc4xx_ibm_ddr2_register_dump();
595 * Clear potential errors resulting from auto-calibration.
596 * If not done, then we could get an interrupt later on when
597 * exceptions are enabled.
599 set_mcsr(get_mcsr());
601 return sdram_memsize();
604 static void get_spd_info(unsigned long *dimm_populated,
605 unsigned char *iic0_dimm_addr,
606 unsigned long num_dimm_banks)
608 unsigned long dimm_num;
609 unsigned long dimm_found;
610 unsigned char num_of_bytes;
611 unsigned char total_size;
614 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
618 num_of_bytes = spd_read(iic0_dimm_addr[dimm_num], 0);
619 debug("\nspd_read(0x%x) returned %d\n",
620 iic0_dimm_addr[dimm_num], num_of_bytes);
621 total_size = spd_read(iic0_dimm_addr[dimm_num], 1);
622 debug("spd_read(0x%x) returned %d\n",
623 iic0_dimm_addr[dimm_num], total_size);
625 if ((num_of_bytes != 0) && (total_size != 0)) {
626 dimm_populated[dimm_num] = TRUE;
628 debug("DIMM slot %lu: populated\n", dimm_num);
630 dimm_populated[dimm_num] = FALSE;
631 debug("DIMM slot %lu: Not populated\n", dimm_num);
635 if (dimm_found == FALSE) {
636 printf("ERROR - No memory installed. Install a DDR-SDRAM DIMM.\n\n");
637 spd_ddr_init_hang ();
641 void board_add_ram_info(int use_default)
643 PPC4xx_SYS_INFO board_cfg;
646 if (is_ecc_enabled())
651 get_sys_info(&board_cfg);
653 mfsdr(SDR0_DDR0, val);
654 val = MULDIV64((board_cfg.freqPLB), SDR0_DDR0_DDRM_DECODE(val), 1);
655 printf(" enabled, %d MHz", (val * 2) / 1000000);
657 mfsdram(SDRAM_MMODE, val);
658 val = (val & SDRAM_MMODE_DCL_MASK) >> 4;
659 printf(", CL%d)", val);
662 /*------------------------------------------------------------------
663 * For the memory DIMMs installed, this routine verifies that they
664 * really are DDR specific DIMMs.
665 *-----------------------------------------------------------------*/
666 static void check_mem_type(unsigned long *dimm_populated,
667 unsigned char *iic0_dimm_addr,
668 unsigned long num_dimm_banks)
670 unsigned long dimm_num;
671 unsigned long dimm_type;
673 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
674 if (dimm_populated[dimm_num] == TRUE) {
675 dimm_type = spd_read(iic0_dimm_addr[dimm_num], 2);
678 printf("ERROR: Standard Fast Page Mode DRAM DIMM detected in "
679 "slot %d.\n", (unsigned int)dimm_num);
680 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
681 printf("Replace the DIMM module with a supported DIMM.\n\n");
682 spd_ddr_init_hang ();
685 printf("ERROR: EDO DIMM detected in slot %d.\n",
686 (unsigned int)dimm_num);
687 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
688 printf("Replace the DIMM module with a supported DIMM.\n\n");
689 spd_ddr_init_hang ();
692 printf("ERROR: Pipelined Nibble DIMM detected in slot %d.\n",
693 (unsigned int)dimm_num);
694 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
695 printf("Replace the DIMM module with a supported DIMM.\n\n");
696 spd_ddr_init_hang ();
699 printf("ERROR: SDRAM DIMM detected in slot %d.\n",
700 (unsigned int)dimm_num);
701 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
702 printf("Replace the DIMM module with a supported DIMM.\n\n");
703 spd_ddr_init_hang ();
706 printf("ERROR: Multiplexed ROM DIMM detected in slot %d.\n",
707 (unsigned int)dimm_num);
708 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
709 printf("Replace the DIMM module with a supported DIMM.\n\n");
710 spd_ddr_init_hang ();
713 printf("ERROR: SGRAM DIMM detected in slot %d.\n",
714 (unsigned int)dimm_num);
715 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
716 printf("Replace the DIMM module with a supported DIMM.\n\n");
717 spd_ddr_init_hang ();
720 debug("DIMM slot %d: DDR1 SDRAM detected\n", dimm_num);
721 dimm_populated[dimm_num] = SDRAM_DDR1;
724 debug("DIMM slot %d: DDR2 SDRAM detected\n", dimm_num);
725 dimm_populated[dimm_num] = SDRAM_DDR2;
728 printf("ERROR: Unknown DIMM detected in slot %d.\n",
729 (unsigned int)dimm_num);
730 printf("Only DDR1 and DDR2 SDRAM DIMMs are supported.\n");
731 printf("Replace the DIMM module with a supported DIMM.\n\n");
732 spd_ddr_init_hang ();
737 for (dimm_num = 1; dimm_num < num_dimm_banks; dimm_num++) {
738 if ((dimm_populated[dimm_num-1] != SDRAM_NONE)
739 && (dimm_populated[dimm_num] != SDRAM_NONE)
740 && (dimm_populated[dimm_num-1] != dimm_populated[dimm_num])) {
741 printf("ERROR: DIMM's DDR1 and DDR2 type can not be mixed.\n");
742 spd_ddr_init_hang ();
747 /*------------------------------------------------------------------
748 * For the memory DIMMs installed, this routine verifies that
749 * frequency previously calculated is supported.
750 *-----------------------------------------------------------------*/
751 static void check_frequency(unsigned long *dimm_populated,
752 unsigned char *iic0_dimm_addr,
753 unsigned long num_dimm_banks)
755 unsigned long dimm_num;
756 unsigned long tcyc_reg;
757 unsigned long cycle_time;
758 unsigned long calc_cycle_time;
759 unsigned long sdram_freq;
760 unsigned long sdr_ddrpll;
761 PPC4xx_SYS_INFO board_cfg;
763 /*------------------------------------------------------------------
764 * Get the board configuration info.
765 *-----------------------------------------------------------------*/
766 get_sys_info(&board_cfg);
768 mfsdr(SDR0_DDR0, sdr_ddrpll);
769 sdram_freq = ((board_cfg.freqPLB) * SDR0_DDR0_DDRM_DECODE(sdr_ddrpll));
772 * calc_cycle_time is calculated from DDR frequency set by board/chip
773 * and is expressed in multiple of 10 picoseconds
774 * to match the way DIMM cycle time is calculated below.
776 calc_cycle_time = MULDIV64(ONE_BILLION, 100, sdram_freq);
778 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
779 if (dimm_populated[dimm_num] != SDRAM_NONE) {
780 tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 9);
782 * Byte 9, Cycle time for CAS Latency=X, is split into two nibbles:
783 * the higher order nibble (bits 4-7) designates the cycle time
784 * to a granularity of 1ns;
785 * the value presented by the lower order nibble (bits 0-3)
786 * has a granularity of .1ns and is added to the value designated
787 * by the higher nibble. In addition, four lines of the lower order
788 * nibble are assigned to support +.25,+.33, +.66 and +.75.
790 /* Convert from hex to decimal */
791 if ((tcyc_reg & 0x0F) == 0x0D)
792 cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) + 75;
793 else if ((tcyc_reg & 0x0F) == 0x0C)
794 cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) + 66;
795 else if ((tcyc_reg & 0x0F) == 0x0B)
796 cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) + 33;
797 else if ((tcyc_reg & 0x0F) == 0x0A)
798 cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) + 25;
800 cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) +
801 ((tcyc_reg & 0x0F)*10);
802 debug("cycle_time=%d [10 picoseconds]\n", cycle_time);
804 if (cycle_time > (calc_cycle_time + 10)) {
806 * the provided sdram cycle_time is too small
807 * for the available DIMM cycle_time.
808 * The additionnal 100ps is here to accept a small incertainty.
810 printf("ERROR: DRAM DIMM detected with cycle_time %d ps in "
811 "slot %d \n while calculated cycle time is %d ps.\n",
812 (unsigned int)(cycle_time*10),
813 (unsigned int)dimm_num,
814 (unsigned int)(calc_cycle_time*10));
815 printf("Replace the DIMM, or change DDR frequency via "
816 "strapping bits.\n\n");
817 spd_ddr_init_hang ();
823 /*------------------------------------------------------------------
824 * For the memory DIMMs installed, this routine verifies two
825 * ranks/banks maximum are availables.
826 *-----------------------------------------------------------------*/
827 static void check_rank_number(unsigned long *dimm_populated,
828 unsigned char *iic0_dimm_addr,
829 unsigned long num_dimm_banks)
831 unsigned long dimm_num;
832 unsigned long dimm_rank;
833 unsigned long total_rank = 0;
835 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
836 if (dimm_populated[dimm_num] != SDRAM_NONE) {
837 dimm_rank = spd_read(iic0_dimm_addr[dimm_num], 5);
838 if (((unsigned long)spd_read(iic0_dimm_addr[dimm_num], 2)) == 0x08)
839 dimm_rank = (dimm_rank & 0x0F) +1;
841 dimm_rank = dimm_rank & 0x0F;
844 if (dimm_rank > MAXRANKS) {
845 printf("ERROR: DRAM DIMM detected with %lu ranks in "
846 "slot %lu is not supported.\n", dimm_rank, dimm_num);
847 printf("Only %d ranks are supported for all DIMM.\n", MAXRANKS);
848 printf("Replace the DIMM module with a supported DIMM.\n\n");
849 spd_ddr_init_hang ();
851 total_rank += dimm_rank;
853 if (total_rank > MAXRANKS) {
854 printf("ERROR: DRAM DIMM detected with a total of %d ranks "
855 "for all slots.\n", (unsigned int)total_rank);
856 printf("Only %d ranks are supported for all DIMM.\n", MAXRANKS);
857 printf("Remove one of the DIMM modules.\n\n");
858 spd_ddr_init_hang ();
863 /*------------------------------------------------------------------
864 * only support 2.5V modules.
865 * This routine verifies this.
866 *-----------------------------------------------------------------*/
867 static void check_voltage_type(unsigned long *dimm_populated,
868 unsigned char *iic0_dimm_addr,
869 unsigned long num_dimm_banks)
871 unsigned long dimm_num;
872 unsigned long voltage_type;
874 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
875 if (dimm_populated[dimm_num] != SDRAM_NONE) {
876 voltage_type = spd_read(iic0_dimm_addr[dimm_num], 8);
877 switch (voltage_type) {
879 printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
880 printf("This DIMM is 5.0 Volt/TTL.\n");
881 printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
882 (unsigned int)dimm_num);
883 spd_ddr_init_hang ();
886 printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
887 printf("This DIMM is LVTTL.\n");
888 printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
889 (unsigned int)dimm_num);
890 spd_ddr_init_hang ();
893 printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
894 printf("This DIMM is 1.5 Volt.\n");
895 printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
896 (unsigned int)dimm_num);
897 spd_ddr_init_hang ();
900 printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
901 printf("This DIMM is 3.3 Volt/TTL.\n");
902 printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
903 (unsigned int)dimm_num);
904 spd_ddr_init_hang ();
907 /* 2.5 Voltage only for DDR1 */
910 /* 1.8 Voltage only for DDR2 */
913 printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
914 printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
915 (unsigned int)dimm_num);
916 spd_ddr_init_hang ();
923 /*-----------------------------------------------------------------------------+
925 *-----------------------------------------------------------------------------*/
926 static void program_copt1(unsigned long *dimm_populated,
927 unsigned char *iic0_dimm_addr,
928 unsigned long num_dimm_banks)
930 unsigned long dimm_num;
931 unsigned long mcopt1;
932 unsigned long ecc_enabled;
933 unsigned long ecc = 0;
934 unsigned long data_width = 0;
935 unsigned long dimm_32bit;
936 unsigned long dimm_64bit;
937 unsigned long registered = 0;
938 unsigned long attribute = 0;
939 unsigned long buf0, buf1; /* TODO: code to be changed for IOP1.6 to support 4 DIMMs */
940 unsigned long bankcount;
941 unsigned long ddrtype;
944 #ifdef CONFIG_DDR_ECC
954 /*------------------------------------------------------------------
955 * Set memory controller options reg 1, SDRAM_MCOPT1.
956 *-----------------------------------------------------------------*/
957 mfsdram(SDRAM_MCOPT1, val);
958 mcopt1 = val & ~(SDRAM_MCOPT1_MCHK_MASK | SDRAM_MCOPT1_RDEN_MASK |
959 SDRAM_MCOPT1_PMU_MASK | SDRAM_MCOPT1_DMWD_MASK |
960 SDRAM_MCOPT1_UIOS_MASK | SDRAM_MCOPT1_BCNT_MASK |
961 SDRAM_MCOPT1_DDR_TYPE_MASK | SDRAM_MCOPT1_RWOO_MASK |
962 SDRAM_MCOPT1_WOOO_MASK | SDRAM_MCOPT1_DCOO_MASK |
963 SDRAM_MCOPT1_DREF_MASK);
965 mcopt1 |= SDRAM_MCOPT1_QDEP;
966 mcopt1 |= SDRAM_MCOPT1_PMU_OPEN;
967 mcopt1 |= SDRAM_MCOPT1_RWOO_DISABLED;
968 mcopt1 |= SDRAM_MCOPT1_WOOO_DISABLED;
969 mcopt1 |= SDRAM_MCOPT1_DCOO_DISABLED;
970 mcopt1 |= SDRAM_MCOPT1_DREF_NORMAL;
972 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
973 if (dimm_populated[dimm_num] != SDRAM_NONE) {
974 /* test ecc support */
975 ecc = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 11);
976 if (ecc != 0x02) /* ecc not supported */
979 /* test bank count */
980 bankcount = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 17);
981 if (bankcount == 0x04) /* bank count = 4 */
982 mcopt1 |= SDRAM_MCOPT1_4_BANKS;
983 else /* bank count = 8 */
984 mcopt1 |= SDRAM_MCOPT1_8_BANKS;
987 ddrtype = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 2);
988 /* test for buffered/unbuffered, registered, differential clocks */
989 registered = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 20);
990 attribute = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 21);
992 /* TODO: code to be changed for IOP1.6 to support 4 DIMMs */
994 if (dimm_populated[dimm_num] == SDRAM_DDR1) /* DDR1 type */
995 mcopt1 |= SDRAM_MCOPT1_DDR1_TYPE;
996 if (dimm_populated[dimm_num] == SDRAM_DDR2) /* DDR2 type */
997 mcopt1 |= SDRAM_MCOPT1_DDR2_TYPE;
998 if (registered == 1) { /* DDR2 always buffered */
999 /* TODO: what about above comments ? */
1000 mcopt1 |= SDRAM_MCOPT1_RDEN;
1003 /* TODO: the mask 0x02 doesn't match Samsung def for byte 21. */
1004 if ((attribute & 0x02) == 0x00) {
1005 /* buffered not supported */
1008 mcopt1 |= SDRAM_MCOPT1_RDEN;
1013 else if (dimm_num == 1) {
1014 if (dimm_populated[dimm_num] == SDRAM_DDR1) /* DDR1 type */
1015 mcopt1 |= SDRAM_MCOPT1_DDR1_TYPE;
1016 if (dimm_populated[dimm_num] == SDRAM_DDR2) /* DDR2 type */
1017 mcopt1 |= SDRAM_MCOPT1_DDR2_TYPE;
1018 if (registered == 1) {
1019 /* DDR2 always buffered */
1020 mcopt1 |= SDRAM_MCOPT1_RDEN;
1023 if ((attribute & 0x02) == 0x00) {
1024 /* buffered not supported */
1027 mcopt1 |= SDRAM_MCOPT1_RDEN;
1033 /* Note that for DDR2 the byte 7 is reserved, but OK to keep code as is. */
1034 data_width = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 6) +
1035 (((unsigned long)spd_read(iic0_dimm_addr[dimm_num], 7)) << 8);
1037 switch (data_width) {
1047 printf("WARNING: Detected a DIMM with a data width of %lu bits.\n",
1049 printf("Only DIMMs with 32 or 64 bit DDR-SDRAM widths are supported.\n");
1055 /* verify matching properties */
1056 if ((dimm_populated[0] != SDRAM_NONE) && (dimm_populated[1] != SDRAM_NONE)) {
1058 printf("ERROR: DIMM's buffered/unbuffered, registered, clocking don't match.\n");
1059 spd_ddr_init_hang ();
1063 if ((dimm_64bit == TRUE) && (dimm_32bit == TRUE)) {
1064 printf("ERROR: Cannot mix 32 bit and 64 bit DDR-SDRAM DIMMs together.\n");
1065 spd_ddr_init_hang ();
1067 else if ((dimm_64bit == TRUE) && (dimm_32bit == FALSE)) {
1068 mcopt1 |= SDRAM_MCOPT1_DMWD_64;
1069 } else if ((dimm_64bit == FALSE) && (dimm_32bit == TRUE)) {
1070 mcopt1 |= SDRAM_MCOPT1_DMWD_32;
1072 printf("ERROR: Please install only 32 or 64 bit DDR-SDRAM DIMMs.\n\n");
1073 spd_ddr_init_hang ();
1076 if (ecc_enabled == TRUE)
1077 mcopt1 |= SDRAM_MCOPT1_MCHK_GEN;
1079 mcopt1 |= SDRAM_MCOPT1_MCHK_NON;
1081 mtsdram(SDRAM_MCOPT1, mcopt1);
1084 /*-----------------------------------------------------------------------------+
1086 *-----------------------------------------------------------------------------*/
1087 static void program_codt(unsigned long *dimm_populated,
1088 unsigned char *iic0_dimm_addr,
1089 unsigned long num_dimm_banks)
1092 unsigned long modt0 = 0;
1093 unsigned long modt1 = 0;
1094 unsigned long modt2 = 0;
1095 unsigned long modt3 = 0;
1096 unsigned char dimm_num;
1097 unsigned char dimm_rank;
1098 unsigned char total_rank = 0;
1099 unsigned char total_dimm = 0;
1100 unsigned char dimm_type = 0;
1101 unsigned char firstSlot = 0;
1103 /*------------------------------------------------------------------
1104 * Set the SDRAM Controller On Die Termination Register
1105 *-----------------------------------------------------------------*/
1106 mfsdram(SDRAM_CODT, codt);
1107 codt |= (SDRAM_CODT_IO_NMODE
1108 & (~SDRAM_CODT_DQS_SINGLE_END
1109 & ~SDRAM_CODT_CKSE_SINGLE_END
1110 & ~SDRAM_CODT_FEEBBACK_RCV_SINGLE_END
1111 & ~SDRAM_CODT_FEEBBACK_DRV_SINGLE_END));
1113 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1114 if (dimm_populated[dimm_num] != SDRAM_NONE) {
1115 dimm_rank = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 5);
1116 if (((unsigned long)spd_read(iic0_dimm_addr[dimm_num], 2)) == 0x08) {
1117 dimm_rank = (dimm_rank & 0x0F) + 1;
1118 dimm_type = SDRAM_DDR2;
1120 dimm_rank = dimm_rank & 0x0F;
1121 dimm_type = SDRAM_DDR1;
1124 total_rank += dimm_rank;
1126 if ((dimm_num == 0) && (total_dimm == 1))
1132 if (dimm_type == SDRAM_DDR2) {
1133 codt |= SDRAM_CODT_DQS_1_8_V_DDR2;
1134 if ((total_dimm == 1) && (firstSlot == TRUE)) {
1135 if (total_rank == 1) { /* PUUU */
1136 codt |= CALC_ODT_R(0);
1137 modt0 = CALC_ODT_W(0);
1142 if (total_rank == 2) { /* PPUU */
1143 codt |= CALC_ODT_R(0) | CALC_ODT_R(1);
1144 modt0 = CALC_ODT_W(0) | CALC_ODT_W(1);
1149 } else if ((total_dimm == 1) && (firstSlot != TRUE)) {
1150 if (total_rank == 1) { /* UUPU */
1151 codt |= CALC_ODT_R(2);
1154 modt2 = CALC_ODT_W(2);
1157 if (total_rank == 2) { /* UUPP */
1158 codt |= CALC_ODT_R(2) | CALC_ODT_R(3);
1161 modt2 = CALC_ODT_W(2) | CALC_ODT_W(3);
1165 if (total_dimm == 2) {
1166 if (total_rank == 2) { /* PUPU */
1167 codt |= CALC_ODT_R(0) | CALC_ODT_R(2);
1168 modt0 = CALC_ODT_RW(2);
1170 modt2 = CALC_ODT_RW(0);
1173 if (total_rank == 4) { /* PPPP */
1174 codt |= CALC_ODT_R(0) | CALC_ODT_R(1) |
1175 CALC_ODT_R(2) | CALC_ODT_R(3);
1176 modt0 = CALC_ODT_RW(2) | CALC_ODT_RW(3);
1178 modt2 = CALC_ODT_RW(0) | CALC_ODT_RW(1);
1183 codt |= SDRAM_CODT_DQS_2_5_V_DDR1;
1189 if (total_dimm == 1) {
1190 if (total_rank == 1)
1192 if (total_rank == 2)
1195 if (total_dimm == 2) {
1196 if (total_rank == 2)
1198 if (total_rank == 4)
1203 debug("nb of dimm %d\n", total_dimm);
1204 debug("nb of rank %d\n", total_rank);
1205 if (total_dimm == 1)
1206 debug("dimm in slot %d\n", firstSlot);
1208 mtsdram(SDRAM_CODT, codt);
1209 mtsdram(SDRAM_MODT0, modt0);
1210 mtsdram(SDRAM_MODT1, modt1);
1211 mtsdram(SDRAM_MODT2, modt2);
1212 mtsdram(SDRAM_MODT3, modt3);
1215 /*-----------------------------------------------------------------------------+
1217 *-----------------------------------------------------------------------------*/
1218 static void program_initplr(unsigned long *dimm_populated,
1219 unsigned char *iic0_dimm_addr,
1220 unsigned long num_dimm_banks,
1221 ddr_cas_id_t selected_cas,
1235 /******************************************************
1236 ** Assumption: if more than one DIMM, all DIMMs are the same
1237 ** as already checked in check_memory_type
1238 ******************************************************/
1240 if ((dimm_populated[0] == SDRAM_DDR1) || (dimm_populated[1] == SDRAM_DDR1)) {
1241 mtsdram(SDRAM_INITPLR0, 0x81B80000);
1242 mtsdram(SDRAM_INITPLR1, 0x81900400);
1243 mtsdram(SDRAM_INITPLR2, 0x81810000);
1244 mtsdram(SDRAM_INITPLR3, 0xff800162);
1245 mtsdram(SDRAM_INITPLR4, 0x81900400);
1246 mtsdram(SDRAM_INITPLR5, 0x86080000);
1247 mtsdram(SDRAM_INITPLR6, 0x86080000);
1248 mtsdram(SDRAM_INITPLR7, 0x81000062);
1249 } else if ((dimm_populated[0] == SDRAM_DDR2) || (dimm_populated[1] == SDRAM_DDR2)) {
1250 switch (selected_cas) {
1261 printf("ERROR: ucode error on selected_cas value %d", selected_cas);
1262 spd_ddr_init_hang ();
1268 * ToDo - Still a problem with the write recovery:
1269 * On the Corsair CM2X512-5400C4 module, setting write recovery
1270 * in the INITPLR reg to the value calculated in program_mode()
1271 * results in not correctly working DDR2 memory (crash after
1274 * So for now, set the write recovery to 3. This seems to work
1275 * on the Corair module too.
1279 switch (write_recovery) {
1293 printf("ERROR: write recovery not support (%d)", write_recovery);
1294 spd_ddr_init_hang ();
1298 wr = WRITE_RECOV_3; /* test-only, see description above */
1301 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++)
1302 if (dimm_populated[dimm_num] != SDRAM_NONE)
1304 if (total_dimm == 1) {
1307 } else if (total_dimm == 2) {
1311 printf("ERROR: Unsupported number of DIMM's (%d)", total_dimm);
1312 spd_ddr_init_hang ();
1315 mr = CMD_EMR | SELECT_MR | BURST_LEN_4 | wr | cas;
1316 emr = CMD_EMR | SELECT_EMR | odt | ods;
1317 emr2 = CMD_EMR | SELECT_EMR2;
1318 emr3 = CMD_EMR | SELECT_EMR3;
1319 /* NOP - Wait 106 MemClk cycles */
1320 mtsdram(SDRAM_INITPLR0, SDRAM_INITPLR_ENABLE | CMD_NOP |
1321 SDRAM_INITPLR_IMWT_ENCODE(106));
1323 /* precharge 4 MemClk cycles */
1324 mtsdram(SDRAM_INITPLR1, SDRAM_INITPLR_ENABLE | CMD_PRECHARGE |
1325 SDRAM_INITPLR_IMWT_ENCODE(4));
1326 /* EMR2 - Wait tMRD (2 MemClk cycles) */
1327 mtsdram(SDRAM_INITPLR2, SDRAM_INITPLR_ENABLE | emr2 |
1328 SDRAM_INITPLR_IMWT_ENCODE(2));
1329 /* EMR3 - Wait tMRD (2 MemClk cycles) */
1330 mtsdram(SDRAM_INITPLR3, SDRAM_INITPLR_ENABLE | emr3 |
1331 SDRAM_INITPLR_IMWT_ENCODE(2));
1332 /* EMR DLL ENABLE - Wait tMRD (2 MemClk cycles) */
1333 mtsdram(SDRAM_INITPLR4, SDRAM_INITPLR_ENABLE | emr |
1334 SDRAM_INITPLR_IMWT_ENCODE(2));
1335 /* MR w/ DLL reset - 200 cycle wait for DLL reset */
1336 mtsdram(SDRAM_INITPLR5, SDRAM_INITPLR_ENABLE | mr | DLL_RESET |
1337 SDRAM_INITPLR_IMWT_ENCODE(200));
1339 /* precharge 4 MemClk cycles */
1340 mtsdram(SDRAM_INITPLR6, SDRAM_INITPLR_ENABLE | CMD_PRECHARGE |
1341 SDRAM_INITPLR_IMWT_ENCODE(4));
1342 /* Refresh 25 MemClk cycles */
1343 mtsdram(SDRAM_INITPLR7, SDRAM_INITPLR_ENABLE | CMD_REFRESH |
1344 SDRAM_INITPLR_IMWT_ENCODE(25));
1345 /* Refresh 25 MemClk cycles */
1346 mtsdram(SDRAM_INITPLR8, SDRAM_INITPLR_ENABLE | CMD_REFRESH |
1347 SDRAM_INITPLR_IMWT_ENCODE(25));
1348 /* Refresh 25 MemClk cycles */
1349 mtsdram(SDRAM_INITPLR9, SDRAM_INITPLR_ENABLE | CMD_REFRESH |
1350 SDRAM_INITPLR_IMWT_ENCODE(25));
1351 /* Refresh 25 MemClk cycles */
1352 mtsdram(SDRAM_INITPLR10, SDRAM_INITPLR_ENABLE | CMD_REFRESH |
1353 SDRAM_INITPLR_IMWT_ENCODE(25));
1354 /* MR w/o DLL reset - Wait tMRD (2 MemClk cycles) */
1355 mtsdram(SDRAM_INITPLR11, SDRAM_INITPLR_ENABLE | mr |
1356 SDRAM_INITPLR_IMWT_ENCODE(2));
1357 /* EMR OCD Default - Wait tMRD (2 MemClk cycles) */
1358 mtsdram(SDRAM_INITPLR12, SDRAM_INITPLR_ENABLE | OCD_CALIB_DEF |
1359 SDRAM_INITPLR_IMWT_ENCODE(2) | emr);
1361 mtsdram(SDRAM_INITPLR13, SDRAM_INITPLR_ENABLE | emr |
1362 SDRAM_INITPLR_IMWT_ENCODE(2));
1364 printf("ERROR: ucode error as unknown DDR type in program_initplr");
1365 spd_ddr_init_hang ();
1369 /*------------------------------------------------------------------
1370 * This routine programs the SDRAM_MMODE register.
1371 * the selected_cas is an output parameter, that will be passed
1372 * by caller to call the above program_initplr( )
1373 *-----------------------------------------------------------------*/
1374 static void program_mode(unsigned long *dimm_populated,
1375 unsigned char *iic0_dimm_addr,
1376 unsigned long num_dimm_banks,
1377 ddr_cas_id_t *selected_cas,
1378 int *write_recovery)
1380 unsigned long dimm_num;
1381 unsigned long sdram_ddr1;
1382 unsigned long t_wr_ns;
1383 unsigned long t_wr_clk;
1384 unsigned long cas_bit;
1385 unsigned long cas_index;
1386 unsigned long sdram_freq;
1387 unsigned long ddr_check;
1388 unsigned long mmode;
1389 unsigned long tcyc_reg;
1390 unsigned long cycle_2_0_clk;
1391 unsigned long cycle_2_5_clk;
1392 unsigned long cycle_3_0_clk;
1393 unsigned long cycle_4_0_clk;
1394 unsigned long cycle_5_0_clk;
1395 unsigned long max_2_0_tcyc_ns_x_100;
1396 unsigned long max_2_5_tcyc_ns_x_100;
1397 unsigned long max_3_0_tcyc_ns_x_100;
1398 unsigned long max_4_0_tcyc_ns_x_100;
1399 unsigned long max_5_0_tcyc_ns_x_100;
1400 unsigned long cycle_time_ns_x_100[3];
1401 PPC4xx_SYS_INFO board_cfg;
1402 unsigned char cas_2_0_available;
1403 unsigned char cas_2_5_available;
1404 unsigned char cas_3_0_available;
1405 unsigned char cas_4_0_available;
1406 unsigned char cas_5_0_available;
1407 unsigned long sdr_ddrpll;
1409 /*------------------------------------------------------------------
1410 * Get the board configuration info.
1411 *-----------------------------------------------------------------*/
1412 get_sys_info(&board_cfg);
1414 mfsdr(SDR0_DDR0, sdr_ddrpll);
1415 sdram_freq = MULDIV64((board_cfg.freqPLB), SDR0_DDR0_DDRM_DECODE(sdr_ddrpll), 1);
1416 debug("sdram_freq=%d\n", sdram_freq);
1418 /*------------------------------------------------------------------
1419 * Handle the timing. We need to find the worst case timing of all
1420 * the dimm modules installed.
1421 *-----------------------------------------------------------------*/
1423 cas_2_0_available = TRUE;
1424 cas_2_5_available = TRUE;
1425 cas_3_0_available = TRUE;
1426 cas_4_0_available = TRUE;
1427 cas_5_0_available = TRUE;
1428 max_2_0_tcyc_ns_x_100 = 10;
1429 max_2_5_tcyc_ns_x_100 = 10;
1430 max_3_0_tcyc_ns_x_100 = 10;
1431 max_4_0_tcyc_ns_x_100 = 10;
1432 max_5_0_tcyc_ns_x_100 = 10;
1435 /* loop through all the DIMM slots on the board */
1436 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1437 /* If a dimm is installed in a particular slot ... */
1438 if (dimm_populated[dimm_num] != SDRAM_NONE) {
1439 if (dimm_populated[dimm_num] == SDRAM_DDR1)
1444 /* t_wr_ns = max(t_wr_ns, (unsigned long)dimm_spd[dimm_num][36] >> 2); */ /* not used in this loop. */
1445 cas_bit = spd_read(iic0_dimm_addr[dimm_num], 18);
1446 debug("cas_bit[SPD byte 18]=%02x\n", cas_bit);
1448 /* For a particular DIMM, grab the three CAS values it supports */
1449 for (cas_index = 0; cas_index < 3; cas_index++) {
1450 switch (cas_index) {
1452 tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 9);
1455 tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 23);
1458 tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 25);
1462 if ((tcyc_reg & 0x0F) >= 10) {
1463 if ((tcyc_reg & 0x0F) == 0x0D) {
1464 /* Convert from hex to decimal */
1465 cycle_time_ns_x_100[cas_index] =
1466 (((tcyc_reg & 0xF0) >> 4) * 100) + 75;
1468 printf("ERROR: SPD reported Tcyc is incorrect for DIMM "
1469 "in slot %d\n", (unsigned int)dimm_num);
1470 spd_ddr_init_hang ();
1473 /* Convert from hex to decimal */
1474 cycle_time_ns_x_100[cas_index] =
1475 (((tcyc_reg & 0xF0) >> 4) * 100) +
1476 ((tcyc_reg & 0x0F)*10);
1478 debug("cas_index=%d: cycle_time_ns_x_100=%d\n", cas_index,
1479 cycle_time_ns_x_100[cas_index]);
1482 /* The rest of this routine determines if CAS 2.0, 2.5, 3.0, 4.0 and 5.0 are */
1483 /* supported for a particular DIMM. */
1488 * DDR devices use the following bitmask for CAS latency:
1489 * Bit 7 6 5 4 3 2 1 0
1490 * TBD 4.0 3.5 3.0 2.5 2.0 1.5 1.0
1492 if (((cas_bit & 0x40) == 0x40) && (cas_index < 3) &&
1493 (cycle_time_ns_x_100[cas_index] != 0)) {
1494 max_4_0_tcyc_ns_x_100 = max(max_4_0_tcyc_ns_x_100,
1495 cycle_time_ns_x_100[cas_index]);
1500 cas_4_0_available = FALSE;
1503 if (((cas_bit & 0x10) == 0x10) && (cas_index < 3) &&
1504 (cycle_time_ns_x_100[cas_index] != 0)) {
1505 max_3_0_tcyc_ns_x_100 = max(max_3_0_tcyc_ns_x_100,
1506 cycle_time_ns_x_100[cas_index]);
1511 cas_3_0_available = FALSE;
1514 if (((cas_bit & 0x08) == 0x08) && (cas_index < 3) &&
1515 (cycle_time_ns_x_100[cas_index] != 0)) {
1516 max_2_5_tcyc_ns_x_100 = max(max_2_5_tcyc_ns_x_100,
1517 cycle_time_ns_x_100[cas_index]);
1522 cas_2_5_available = FALSE;
1525 if (((cas_bit & 0x04) == 0x04) && (cas_index < 3) &&
1526 (cycle_time_ns_x_100[cas_index] != 0)) {
1527 max_2_0_tcyc_ns_x_100 = max(max_2_0_tcyc_ns_x_100,
1528 cycle_time_ns_x_100[cas_index]);
1533 cas_2_0_available = FALSE;
1537 * DDR2 devices use the following bitmask for CAS latency:
1538 * Bit 7 6 5 4 3 2 1 0
1539 * TBD 6.0 5.0 4.0 3.0 2.0 TBD TBD
1541 if (((cas_bit & 0x20) == 0x20) && (cas_index < 3) &&
1542 (cycle_time_ns_x_100[cas_index] != 0)) {
1543 max_5_0_tcyc_ns_x_100 = max(max_5_0_tcyc_ns_x_100,
1544 cycle_time_ns_x_100[cas_index]);
1549 cas_5_0_available = FALSE;
1552 if (((cas_bit & 0x10) == 0x10) && (cas_index < 3) &&
1553 (cycle_time_ns_x_100[cas_index] != 0)) {
1554 max_4_0_tcyc_ns_x_100 = max(max_4_0_tcyc_ns_x_100,
1555 cycle_time_ns_x_100[cas_index]);
1560 cas_4_0_available = FALSE;
1563 if (((cas_bit & 0x08) == 0x08) && (cas_index < 3) &&
1564 (cycle_time_ns_x_100[cas_index] != 0)) {
1565 max_3_0_tcyc_ns_x_100 = max(max_3_0_tcyc_ns_x_100,
1566 cycle_time_ns_x_100[cas_index]);
1571 cas_3_0_available = FALSE;
1577 /*------------------------------------------------------------------
1578 * Set the SDRAM mode, SDRAM_MMODE
1579 *-----------------------------------------------------------------*/
1580 mfsdram(SDRAM_MMODE, mmode);
1581 mmode = mmode & ~(SDRAM_MMODE_WR_MASK | SDRAM_MMODE_DCL_MASK);
1583 /* add 10 here because of rounding problems */
1584 cycle_2_0_clk = MULDIV64(ONE_BILLION, 100, max_2_0_tcyc_ns_x_100) + 10;
1585 cycle_2_5_clk = MULDIV64(ONE_BILLION, 100, max_2_5_tcyc_ns_x_100) + 10;
1586 cycle_3_0_clk = MULDIV64(ONE_BILLION, 100, max_3_0_tcyc_ns_x_100) + 10;
1587 cycle_4_0_clk = MULDIV64(ONE_BILLION, 100, max_4_0_tcyc_ns_x_100) + 10;
1588 cycle_5_0_clk = MULDIV64(ONE_BILLION, 100, max_5_0_tcyc_ns_x_100) + 10;
1589 debug("cycle_3_0_clk=%d\n", cycle_3_0_clk);
1590 debug("cycle_4_0_clk=%d\n", cycle_4_0_clk);
1591 debug("cycle_5_0_clk=%d\n", cycle_5_0_clk);
1593 if (sdram_ddr1 == TRUE) { /* DDR1 */
1594 if ((cas_2_0_available == TRUE) && (sdram_freq <= cycle_2_0_clk)) {
1595 mmode |= SDRAM_MMODE_DCL_DDR1_2_0_CLK;
1596 *selected_cas = DDR_CAS_2;
1597 } else if ((cas_2_5_available == TRUE) && (sdram_freq <= cycle_2_5_clk)) {
1598 mmode |= SDRAM_MMODE_DCL_DDR1_2_5_CLK;
1599 *selected_cas = DDR_CAS_2_5;
1600 } else if ((cas_3_0_available == TRUE) && (sdram_freq <= cycle_3_0_clk)) {
1601 mmode |= SDRAM_MMODE_DCL_DDR1_3_0_CLK;
1602 *selected_cas = DDR_CAS_3;
1604 printf("ERROR: Cannot find a supported CAS latency with the installed DIMMs.\n");
1605 printf("Only DIMMs DDR1 with CAS latencies of 2.0, 2.5, and 3.0 are supported.\n");
1606 printf("Make sure the PLB speed is within the supported range of the DIMMs.\n\n");
1607 spd_ddr_init_hang ();
1610 debug("cas_3_0_available=%d\n", cas_3_0_available);
1611 debug("cas_4_0_available=%d\n", cas_4_0_available);
1612 debug("cas_5_0_available=%d\n", cas_5_0_available);
1613 if ((cas_3_0_available == TRUE) && (sdram_freq <= cycle_3_0_clk)) {
1614 mmode |= SDRAM_MMODE_DCL_DDR2_3_0_CLK;
1615 *selected_cas = DDR_CAS_3;
1616 } else if ((cas_4_0_available == TRUE) && (sdram_freq <= cycle_4_0_clk)) {
1617 mmode |= SDRAM_MMODE_DCL_DDR2_4_0_CLK;
1618 *selected_cas = DDR_CAS_4;
1619 } else if ((cas_5_0_available == TRUE) && (sdram_freq <= cycle_5_0_clk)) {
1620 mmode |= SDRAM_MMODE_DCL_DDR2_5_0_CLK;
1621 *selected_cas = DDR_CAS_5;
1623 printf("ERROR: Cannot find a supported CAS latency with the installed DIMMs.\n");
1624 printf("Only DIMMs DDR2 with CAS latencies of 3.0, 4.0, and 5.0 are supported.\n");
1625 printf("Make sure the PLB speed is within the supported range of the DIMMs.\n");
1626 printf("cas3=%d cas4=%d cas5=%d\n",
1627 cas_3_0_available, cas_4_0_available, cas_5_0_available);
1628 printf("sdram_freq=%lu cycle3=%lu cycle4=%lu cycle5=%lu\n\n",
1629 sdram_freq, cycle_3_0_clk, cycle_4_0_clk, cycle_5_0_clk);
1630 spd_ddr_init_hang ();
1634 if (sdram_ddr1 == TRUE)
1635 mmode |= SDRAM_MMODE_WR_DDR1;
1638 /* loop through all the DIMM slots on the board */
1639 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1640 /* If a dimm is installed in a particular slot ... */
1641 if (dimm_populated[dimm_num] != SDRAM_NONE)
1642 t_wr_ns = max(t_wr_ns,
1643 spd_read(iic0_dimm_addr[dimm_num], 36) >> 2);
1647 * convert from nanoseconds to ddr clocks
1648 * round up if necessary
1650 t_wr_clk = MULDIV64(sdram_freq, t_wr_ns, ONE_BILLION);
1651 ddr_check = MULDIV64(ONE_BILLION, t_wr_clk, t_wr_ns);
1652 if (sdram_freq != ddr_check)
1660 mmode |= SDRAM_MMODE_WR_DDR2_3_CYC;
1663 mmode |= SDRAM_MMODE_WR_DDR2_4_CYC;
1666 mmode |= SDRAM_MMODE_WR_DDR2_5_CYC;
1669 mmode |= SDRAM_MMODE_WR_DDR2_6_CYC;
1672 *write_recovery = t_wr_clk;
1675 debug("CAS latency = %d\n", *selected_cas);
1676 debug("Write recovery = %d\n", *write_recovery);
1678 mtsdram(SDRAM_MMODE, mmode);
1681 /*-----------------------------------------------------------------------------+
1683 *-----------------------------------------------------------------------------*/
1684 static void program_rtr(unsigned long *dimm_populated,
1685 unsigned char *iic0_dimm_addr,
1686 unsigned long num_dimm_banks)
1688 PPC4xx_SYS_INFO board_cfg;
1689 unsigned long max_refresh_rate;
1690 unsigned long dimm_num;
1691 unsigned long refresh_rate_type;
1692 unsigned long refresh_rate;
1694 unsigned long sdram_freq;
1695 unsigned long sdr_ddrpll;
1698 /*------------------------------------------------------------------
1699 * Get the board configuration info.
1700 *-----------------------------------------------------------------*/
1701 get_sys_info(&board_cfg);
1703 /*------------------------------------------------------------------
1704 * Set the SDRAM Refresh Timing Register, SDRAM_RTR
1705 *-----------------------------------------------------------------*/
1706 mfsdr(SDR0_DDR0, sdr_ddrpll);
1707 sdram_freq = ((board_cfg.freqPLB) * SDR0_DDR0_DDRM_DECODE(sdr_ddrpll));
1709 max_refresh_rate = 0;
1710 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1711 if (dimm_populated[dimm_num] != SDRAM_NONE) {
1713 refresh_rate_type = spd_read(iic0_dimm_addr[dimm_num], 12);
1714 refresh_rate_type &= 0x7F;
1715 switch (refresh_rate_type) {
1717 refresh_rate = 15625;
1720 refresh_rate = 3906;
1723 refresh_rate = 7812;
1726 refresh_rate = 31250;
1729 refresh_rate = 62500;
1732 refresh_rate = 125000;
1736 printf("ERROR: DIMM %d unsupported refresh rate/type.\n",
1737 (unsigned int)dimm_num);
1738 printf("Replace the DIMM module with a supported DIMM.\n\n");
1739 spd_ddr_init_hang ();
1743 max_refresh_rate = max(max_refresh_rate, refresh_rate);
1747 rint = MULDIV64(sdram_freq, max_refresh_rate, ONE_BILLION);
1748 mfsdram(SDRAM_RTR, val);
1749 mtsdram(SDRAM_RTR, (val & ~SDRAM_RTR_RINT_MASK) |
1750 (SDRAM_RTR_RINT_ENCODE(rint)));
1753 /*------------------------------------------------------------------
1754 * This routine programs the SDRAM_TRx registers.
1755 *-----------------------------------------------------------------*/
1756 static void program_tr(unsigned long *dimm_populated,
1757 unsigned char *iic0_dimm_addr,
1758 unsigned long num_dimm_banks)
1760 unsigned long dimm_num;
1761 unsigned long sdram_ddr1;
1762 unsigned long t_rp_ns;
1763 unsigned long t_rcd_ns;
1764 unsigned long t_rrd_ns;
1765 unsigned long t_ras_ns;
1766 unsigned long t_rc_ns;
1767 unsigned long t_rfc_ns;
1768 unsigned long t_wpc_ns;
1769 unsigned long t_wtr_ns;
1770 unsigned long t_rpc_ns;
1771 unsigned long t_rp_clk;
1772 unsigned long t_rcd_clk;
1773 unsigned long t_rrd_clk;
1774 unsigned long t_ras_clk;
1775 unsigned long t_rc_clk;
1776 unsigned long t_rfc_clk;
1777 unsigned long t_wpc_clk;
1778 unsigned long t_wtr_clk;
1779 unsigned long t_rpc_clk;
1780 unsigned long sdtr1, sdtr2, sdtr3;
1781 unsigned long ddr_check;
1782 unsigned long sdram_freq;
1783 unsigned long sdr_ddrpll;
1785 PPC4xx_SYS_INFO board_cfg;
1787 /*------------------------------------------------------------------
1788 * Get the board configuration info.
1789 *-----------------------------------------------------------------*/
1790 get_sys_info(&board_cfg);
1792 mfsdr(SDR0_DDR0, sdr_ddrpll);
1793 sdram_freq = ((board_cfg.freqPLB) * SDR0_DDR0_DDRM_DECODE(sdr_ddrpll));
1795 /*------------------------------------------------------------------
1796 * Handle the timing. We need to find the worst case timing of all
1797 * the dimm modules installed.
1798 *-----------------------------------------------------------------*/
1810 /* loop through all the DIMM slots on the board */
1811 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1812 /* If a dimm is installed in a particular slot ... */
1813 if (dimm_populated[dimm_num] != SDRAM_NONE) {
1814 if (dimm_populated[dimm_num] == SDRAM_DDR2)
1819 t_rcd_ns = max(t_rcd_ns, spd_read(iic0_dimm_addr[dimm_num], 29) >> 2);
1820 t_rrd_ns = max(t_rrd_ns, spd_read(iic0_dimm_addr[dimm_num], 28) >> 2);
1821 t_rp_ns = max(t_rp_ns, spd_read(iic0_dimm_addr[dimm_num], 27) >> 2);
1822 t_ras_ns = max(t_ras_ns, spd_read(iic0_dimm_addr[dimm_num], 30));
1823 t_rc_ns = max(t_rc_ns, spd_read(iic0_dimm_addr[dimm_num], 41));
1824 t_rfc_ns = max(t_rfc_ns, spd_read(iic0_dimm_addr[dimm_num], 42));
1828 /*------------------------------------------------------------------
1829 * Set the SDRAM Timing Reg 1, SDRAM_TR1
1830 *-----------------------------------------------------------------*/
1831 mfsdram(SDRAM_SDTR1, sdtr1);
1832 sdtr1 &= ~(SDRAM_SDTR1_LDOF_MASK | SDRAM_SDTR1_RTW_MASK |
1833 SDRAM_SDTR1_WTWO_MASK | SDRAM_SDTR1_RTRO_MASK);
1835 /* default values */
1836 sdtr1 |= SDRAM_SDTR1_LDOF_2_CLK;
1837 sdtr1 |= SDRAM_SDTR1_RTW_2_CLK;
1839 /* normal operations */
1840 sdtr1 |= SDRAM_SDTR1_WTWO_0_CLK;
1841 sdtr1 |= SDRAM_SDTR1_RTRO_1_CLK;
1843 mtsdram(SDRAM_SDTR1, sdtr1);
1845 /*------------------------------------------------------------------
1846 * Set the SDRAM Timing Reg 2, SDRAM_TR2
1847 *-----------------------------------------------------------------*/
1848 mfsdram(SDRAM_SDTR2, sdtr2);
1849 sdtr2 &= ~(SDRAM_SDTR2_RCD_MASK | SDRAM_SDTR2_WTR_MASK |
1850 SDRAM_SDTR2_XSNR_MASK | SDRAM_SDTR2_WPC_MASK |
1851 SDRAM_SDTR2_RPC_MASK | SDRAM_SDTR2_RP_MASK |
1852 SDRAM_SDTR2_RRD_MASK);
1855 * convert t_rcd from nanoseconds to ddr clocks
1856 * round up if necessary
1858 t_rcd_clk = MULDIV64(sdram_freq, t_rcd_ns, ONE_BILLION);
1859 ddr_check = MULDIV64(ONE_BILLION, t_rcd_clk, t_rcd_ns);
1860 if (sdram_freq != ddr_check)
1863 switch (t_rcd_clk) {
1866 sdtr2 |= SDRAM_SDTR2_RCD_1_CLK;
1869 sdtr2 |= SDRAM_SDTR2_RCD_2_CLK;
1872 sdtr2 |= SDRAM_SDTR2_RCD_3_CLK;
1875 sdtr2 |= SDRAM_SDTR2_RCD_4_CLK;
1878 sdtr2 |= SDRAM_SDTR2_RCD_5_CLK;
1882 if (sdram_ddr1 == TRUE) { /* DDR1 */
1883 if (sdram_freq < 200000000) {
1884 sdtr2 |= SDRAM_SDTR2_WTR_1_CLK;
1885 sdtr2 |= SDRAM_SDTR2_WPC_2_CLK;
1886 sdtr2 |= SDRAM_SDTR2_RPC_2_CLK;
1888 sdtr2 |= SDRAM_SDTR2_WTR_2_CLK;
1889 sdtr2 |= SDRAM_SDTR2_WPC_3_CLK;
1890 sdtr2 |= SDRAM_SDTR2_RPC_2_CLK;
1893 /* loop through all the DIMM slots on the board */
1894 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1895 /* If a dimm is installed in a particular slot ... */
1896 if (dimm_populated[dimm_num] != SDRAM_NONE) {
1897 t_wpc_ns = max(t_wtr_ns, spd_read(iic0_dimm_addr[dimm_num], 36) >> 2);
1898 t_wtr_ns = max(t_wtr_ns, spd_read(iic0_dimm_addr[dimm_num], 37) >> 2);
1899 t_rpc_ns = max(t_rpc_ns, spd_read(iic0_dimm_addr[dimm_num], 38) >> 2);
1904 * convert from nanoseconds to ddr clocks
1905 * round up if necessary
1907 t_wpc_clk = MULDIV64(sdram_freq, t_wpc_ns, ONE_BILLION);
1908 ddr_check = MULDIV64(ONE_BILLION, t_wpc_clk, t_wpc_ns);
1909 if (sdram_freq != ddr_check)
1912 switch (t_wpc_clk) {
1916 sdtr2 |= SDRAM_SDTR2_WPC_2_CLK;
1919 sdtr2 |= SDRAM_SDTR2_WPC_3_CLK;
1922 sdtr2 |= SDRAM_SDTR2_WPC_4_CLK;
1925 sdtr2 |= SDRAM_SDTR2_WPC_5_CLK;
1928 sdtr2 |= SDRAM_SDTR2_WPC_6_CLK;
1933 * convert from nanoseconds to ddr clocks
1934 * round up if necessary
1936 t_wtr_clk = MULDIV64(sdram_freq, t_wtr_ns, ONE_BILLION);
1937 ddr_check = MULDIV64(ONE_BILLION, t_wtr_clk, t_wtr_ns);
1938 if (sdram_freq != ddr_check)
1941 switch (t_wtr_clk) {
1944 sdtr2 |= SDRAM_SDTR2_WTR_1_CLK;
1947 sdtr2 |= SDRAM_SDTR2_WTR_2_CLK;
1950 sdtr2 |= SDRAM_SDTR2_WTR_3_CLK;
1953 sdtr2 |= SDRAM_SDTR2_WTR_4_CLK;
1958 * convert from nanoseconds to ddr clocks
1959 * round up if necessary
1961 t_rpc_clk = MULDIV64(sdram_freq, t_rpc_ns, ONE_BILLION);
1962 ddr_check = MULDIV64(ONE_BILLION, t_rpc_clk, t_rpc_ns);
1963 if (sdram_freq != ddr_check)
1966 switch (t_rpc_clk) {
1970 sdtr2 |= SDRAM_SDTR2_RPC_2_CLK;
1973 sdtr2 |= SDRAM_SDTR2_RPC_3_CLK;
1976 sdtr2 |= SDRAM_SDTR2_RPC_4_CLK;
1982 sdtr2 |= SDRAM_SDTR2_XSNR_16_CLK;
1985 * convert t_rrd from nanoseconds to ddr clocks
1986 * round up if necessary
1988 t_rrd_clk = MULDIV64(sdram_freq, t_rrd_ns, ONE_BILLION);
1989 ddr_check = MULDIV64(ONE_BILLION, t_rrd_clk, t_rrd_ns);
1990 if (sdram_freq != ddr_check)
1994 sdtr2 |= SDRAM_SDTR2_RRD_3_CLK;
1996 sdtr2 |= SDRAM_SDTR2_RRD_2_CLK;
1999 * convert t_rp from nanoseconds to ddr clocks
2000 * round up if necessary
2002 t_rp_clk = MULDIV64(sdram_freq, t_rp_ns, ONE_BILLION);
2003 ddr_check = MULDIV64(ONE_BILLION, t_rp_clk, t_rp_ns);
2004 if (sdram_freq != ddr_check)
2012 sdtr2 |= SDRAM_SDTR2_RP_3_CLK;
2015 sdtr2 |= SDRAM_SDTR2_RP_4_CLK;
2018 sdtr2 |= SDRAM_SDTR2_RP_5_CLK;
2021 sdtr2 |= SDRAM_SDTR2_RP_6_CLK;
2024 sdtr2 |= SDRAM_SDTR2_RP_7_CLK;
2028 mtsdram(SDRAM_SDTR2, sdtr2);
2030 /*------------------------------------------------------------------
2031 * Set the SDRAM Timing Reg 3, SDRAM_TR3
2032 *-----------------------------------------------------------------*/
2033 mfsdram(SDRAM_SDTR3, sdtr3);
2034 sdtr3 &= ~(SDRAM_SDTR3_RAS_MASK | SDRAM_SDTR3_RC_MASK |
2035 SDRAM_SDTR3_XCS_MASK | SDRAM_SDTR3_RFC_MASK);
2038 * convert t_ras from nanoseconds to ddr clocks
2039 * round up if necessary
2041 t_ras_clk = MULDIV64(sdram_freq, t_ras_ns, ONE_BILLION);
2042 ddr_check = MULDIV64(ONE_BILLION, t_ras_clk, t_ras_ns);
2043 if (sdram_freq != ddr_check)
2046 sdtr3 |= SDRAM_SDTR3_RAS_ENCODE(t_ras_clk);
2049 * convert t_rc from nanoseconds to ddr clocks
2050 * round up if necessary
2052 t_rc_clk = MULDIV64(sdram_freq, t_rc_ns, ONE_BILLION);
2053 ddr_check = MULDIV64(ONE_BILLION, t_rc_clk, t_rc_ns);
2054 if (sdram_freq != ddr_check)
2057 sdtr3 |= SDRAM_SDTR3_RC_ENCODE(t_rc_clk);
2059 /* default xcs value */
2060 sdtr3 |= SDRAM_SDTR3_XCS;
2063 * convert t_rfc from nanoseconds to ddr clocks
2064 * round up if necessary
2066 t_rfc_clk = MULDIV64(sdram_freq, t_rfc_ns, ONE_BILLION);
2067 ddr_check = MULDIV64(ONE_BILLION, t_rfc_clk, t_rfc_ns);
2068 if (sdram_freq != ddr_check)
2071 sdtr3 |= SDRAM_SDTR3_RFC_ENCODE(t_rfc_clk);
2073 mtsdram(SDRAM_SDTR3, sdtr3);
2076 /*-----------------------------------------------------------------------------+
2078 *-----------------------------------------------------------------------------*/
2079 static void program_bxcf(unsigned long *dimm_populated,
2080 unsigned char *iic0_dimm_addr,
2081 unsigned long num_dimm_banks)
2083 unsigned long dimm_num;
2084 unsigned long num_col_addr;
2085 unsigned long num_ranks;
2086 unsigned long num_banks;
2088 unsigned long ind_rank;
2090 unsigned long ind_bank;
2091 unsigned long bank_0_populated;
2093 /*------------------------------------------------------------------
2094 * Set the BxCF regs. First, wipe out the bank config registers.
2095 *-----------------------------------------------------------------*/
2096 mtsdram(SDRAM_MB0CF, 0x00000000);
2097 mtsdram(SDRAM_MB1CF, 0x00000000);
2098 mtsdram(SDRAM_MB2CF, 0x00000000);
2099 mtsdram(SDRAM_MB3CF, 0x00000000);
2101 mode = SDRAM_BXCF_M_BE_ENABLE;
2103 bank_0_populated = 0;
2105 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
2106 if (dimm_populated[dimm_num] != SDRAM_NONE) {
2107 num_col_addr = spd_read(iic0_dimm_addr[dimm_num], 4);
2108 num_ranks = spd_read(iic0_dimm_addr[dimm_num], 5);
2109 if ((spd_read(iic0_dimm_addr[dimm_num], 2)) == 0x08)
2110 num_ranks = (num_ranks & 0x0F) +1;
2112 num_ranks = num_ranks & 0x0F;
2114 num_banks = spd_read(iic0_dimm_addr[dimm_num], 17);
2116 for (ind_bank = 0; ind_bank < 2; ind_bank++) {
2121 switch (num_col_addr) {
2123 mode |= (SDRAM_BXCF_M_AM_0 + ind);
2126 mode |= (SDRAM_BXCF_M_AM_1 + ind);
2129 mode |= (SDRAM_BXCF_M_AM_2 + ind);
2132 mode |= (SDRAM_BXCF_M_AM_3 + ind);
2135 mode |= (SDRAM_BXCF_M_AM_4 + ind);
2138 printf("DDR-SDRAM: DIMM %d BxCF configuration.\n",
2139 (unsigned int)dimm_num);
2140 printf("ERROR: Unsupported value for number of "
2141 "column addresses: %d.\n", (unsigned int)num_col_addr);
2142 printf("Replace the DIMM module with a supported DIMM.\n\n");
2143 spd_ddr_init_hang ();
2147 if ((dimm_populated[dimm_num] != SDRAM_NONE)&& (dimm_num ==1))
2148 bank_0_populated = 1;
2150 for (ind_rank = 0; ind_rank < num_ranks; ind_rank++) {
2151 mtsdram(SDRAM_MB0CF +
2152 ((dimm_num + bank_0_populated + ind_rank) << 2),
2159 /*------------------------------------------------------------------
2160 * program memory queue.
2161 *-----------------------------------------------------------------*/
2162 static void program_memory_queue(unsigned long *dimm_populated,
2163 unsigned char *iic0_dimm_addr,
2164 unsigned long num_dimm_banks)
2166 unsigned long dimm_num;
2167 phys_size_t rank_base_addr;
2168 unsigned long rank_reg;
2169 phys_size_t rank_size_bytes;
2170 unsigned long rank_size_id;
2171 unsigned long num_ranks;
2172 unsigned long baseadd_size;
2174 unsigned long bank_0_populated = 0;
2175 phys_size_t total_size = 0;
2177 /*------------------------------------------------------------------
2178 * Reset the rank_base_address.
2179 *-----------------------------------------------------------------*/
2180 rank_reg = SDRAM_R0BAS;
2182 rank_base_addr = 0x00000000;
2184 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
2185 if (dimm_populated[dimm_num] != SDRAM_NONE) {
2186 num_ranks = spd_read(iic0_dimm_addr[dimm_num], 5);
2187 if ((spd_read(iic0_dimm_addr[dimm_num], 2)) == 0x08)
2188 num_ranks = (num_ranks & 0x0F) + 1;
2190 num_ranks = num_ranks & 0x0F;
2192 rank_size_id = spd_read(iic0_dimm_addr[dimm_num], 31);
2194 /*------------------------------------------------------------------
2196 *-----------------------------------------------------------------*/
2198 switch (rank_size_id) {
2200 baseadd_size |= SDRAM_RXBAS_SDSZ_1024;
2204 baseadd_size |= SDRAM_RXBAS_SDSZ_2048;
2208 baseadd_size |= SDRAM_RXBAS_SDSZ_4096;
2212 baseadd_size |= SDRAM_RXBAS_SDSZ_32;
2216 baseadd_size |= SDRAM_RXBAS_SDSZ_64;
2220 baseadd_size |= SDRAM_RXBAS_SDSZ_128;
2224 baseadd_size |= SDRAM_RXBAS_SDSZ_256;
2228 baseadd_size |= SDRAM_RXBAS_SDSZ_512;
2232 printf("DDR-SDRAM: DIMM %d memory queue configuration.\n",
2233 (unsigned int)dimm_num);
2234 printf("ERROR: Unsupported value for the banksize: %d.\n",
2235 (unsigned int)rank_size_id);
2236 printf("Replace the DIMM module with a supported DIMM.\n\n");
2237 spd_ddr_init_hang ();
2239 rank_size_bytes = total_size << 20;
2241 if ((dimm_populated[dimm_num] != SDRAM_NONE) && (dimm_num == 1))
2242 bank_0_populated = 1;
2244 for (i = 0; i < num_ranks; i++) {
2245 mtdcr_any(rank_reg+i+dimm_num+bank_0_populated,
2246 (SDRAM_RXBAS_SDBA_ENCODE(rank_base_addr) |
2248 rank_base_addr += rank_size_bytes;
2253 #if defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
2254 defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
2255 defined(CONFIG_460SX)
2257 * Enable high bandwidth access
2258 * This is currently not used, but with this setup
2259 * it is possible to use it later on in e.g. the Linux
2260 * EMAC driver for performance gain.
2262 mtdcr(SDRAM_PLBADDULL, 0x00000000); /* MQ0_BAUL */
2263 mtdcr(SDRAM_PLBADDUHB, 0x00000008); /* MQ0_BAUH */
2266 * Set optimal value for Memory Queue HB/LL Configuration registers
2268 mtdcr(SDRAM_CONF1HB, (mfdcr(SDRAM_CONF1HB) & ~SDRAM_CONF1HB_MASK) |
2269 SDRAM_CONF1HB_AAFR | SDRAM_CONF1HB_RPEN | SDRAM_CONF1HB_RFTE |
2270 SDRAM_CONF1HB_RPLM | SDRAM_CONF1HB_WRCL);
2271 mtdcr(SDRAM_CONF1LL, (mfdcr(SDRAM_CONF1LL) & ~SDRAM_CONF1LL_MASK) |
2272 SDRAM_CONF1LL_AAFR | SDRAM_CONF1LL_RPEN | SDRAM_CONF1LL_RFTE |
2273 SDRAM_CONF1LL_RPLM);
2274 mtdcr(SDRAM_CONFPATHB, mfdcr(SDRAM_CONFPATHB) | SDRAM_CONFPATHB_TPEN);
2278 /*-----------------------------------------------------------------------------+
2280 *-----------------------------------------------------------------------------*/
2281 static unsigned long is_ecc_enabled(void)
2283 unsigned long dimm_num;
2288 /* loop through all the DIMM slots on the board */
2289 for (dimm_num = 0; dimm_num < MAXDIMMS; dimm_num++) {
2290 mfsdram(SDRAM_MCOPT1, val);
2291 ecc = max(ecc, SDRAM_MCOPT1_MCHK_CHK_DECODE(val));
2297 #ifdef CONFIG_DDR_ECC
2298 /*-----------------------------------------------------------------------------+
2300 *-----------------------------------------------------------------------------*/
2301 static void program_ecc(unsigned long *dimm_populated,
2302 unsigned char *iic0_dimm_addr,
2303 unsigned long num_dimm_banks,
2304 unsigned long tlb_word2_i_value)
2306 unsigned long mcopt1;
2307 unsigned long mcopt2;
2308 unsigned long mcstat;
2309 unsigned long dimm_num;
2313 /* loop through all the DIMM slots on the board */
2314 for (dimm_num = 0; dimm_num < MAXDIMMS; dimm_num++) {
2315 /* If a dimm is installed in a particular slot ... */
2316 if (dimm_populated[dimm_num] != SDRAM_NONE)
2317 ecc = max(ecc, spd_read(iic0_dimm_addr[dimm_num], 11));
2322 if (sdram_memsize() > CONFIG_MAX_MEM_MAPPED) {
2323 printf("\nWarning: Can't enable ECC on systems with more than 2GB of SDRAM!\n");
2327 mfsdram(SDRAM_MCOPT1, mcopt1);
2328 mfsdram(SDRAM_MCOPT2, mcopt2);
2330 if ((mcopt1 & SDRAM_MCOPT1_MCHK_MASK) != SDRAM_MCOPT1_MCHK_NON) {
2331 /* DDR controller must be enabled and not in self-refresh. */
2332 mfsdram(SDRAM_MCSTAT, mcstat);
2333 if (((mcopt2 & SDRAM_MCOPT2_DCEN_MASK) == SDRAM_MCOPT2_DCEN_ENABLE)
2334 && ((mcopt2 & SDRAM_MCOPT2_SREN_MASK) == SDRAM_MCOPT2_SREN_EXIT)
2335 && ((mcstat & (SDRAM_MCSTAT_MIC_MASK | SDRAM_MCSTAT_SRMS_MASK))
2336 == (SDRAM_MCSTAT_MIC_COMP | SDRAM_MCSTAT_SRMS_NOT_SF))) {
2338 program_ecc_addr(0, sdram_memsize(), tlb_word2_i_value);
2345 static void wait_ddr_idle(void)
2350 mfsdram(SDRAM_MCSTAT, val);
2351 } while ((val & SDRAM_MCSTAT_IDLE_MASK) == SDRAM_MCSTAT_IDLE_NOT);
2354 /*-----------------------------------------------------------------------------+
2356 *-----------------------------------------------------------------------------*/
2357 static void program_ecc_addr(unsigned long start_address,
2358 unsigned long num_bytes,
2359 unsigned long tlb_word2_i_value)
2361 unsigned long current_address;
2362 unsigned long end_address;
2363 unsigned long address_increment;
2364 unsigned long mcopt1;
2365 char str[] = "ECC generation -";
2366 char slash[] = "\\|/-\\|/-";
2370 current_address = start_address;
2371 mfsdram(SDRAM_MCOPT1, mcopt1);
2372 if ((mcopt1 & SDRAM_MCOPT1_MCHK_MASK) != SDRAM_MCOPT1_MCHK_NON) {
2373 mtsdram(SDRAM_MCOPT1,
2374 (mcopt1 & ~SDRAM_MCOPT1_MCHK_MASK) | SDRAM_MCOPT1_MCHK_GEN);
2380 if (tlb_word2_i_value == TLB_WORD2_I_ENABLE) {
2381 /* ECC bit set method for non-cached memory */
2382 if ((mcopt1 & SDRAM_MCOPT1_DMWD_MASK) == SDRAM_MCOPT1_DMWD_32)
2383 address_increment = 4;
2385 address_increment = 8;
2386 end_address = current_address + num_bytes;
2388 while (current_address < end_address) {
2389 *((unsigned long *)current_address) = 0x00000000;
2390 current_address += address_increment;
2392 if ((loop++ % (2 << 20)) == 0) {
2394 putc(slash[loopi++ % 8]);
2399 /* ECC bit set method for cached memory */
2400 dcbz_area(start_address, num_bytes);
2401 /* Write modified dcache lines back to memory */
2402 clean_dcache_range(start_address, start_address + num_bytes);
2405 blank_string(strlen(str));
2411 /* clear ECC error repoting registers */
2412 mtsdram(SDRAM_ECCCR, 0xffffffff);
2413 mtdcr(0x4c, 0xffffffff);
2415 mtsdram(SDRAM_MCOPT1,
2416 (mcopt1 & ~SDRAM_MCOPT1_MCHK_MASK) | SDRAM_MCOPT1_MCHK_CHK_REP);
2424 #if !defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION)
2425 /*-----------------------------------------------------------------------------+
2426 * program_DQS_calibration.
2427 *-----------------------------------------------------------------------------*/
2428 static void program_DQS_calibration(unsigned long *dimm_populated,
2429 unsigned char *iic0_dimm_addr,
2430 unsigned long num_dimm_banks)
2434 #ifdef HARD_CODED_DQS /* calibration test with hardvalues */
2435 mtsdram(SDRAM_RQDC, 0x80000037);
2436 mtsdram(SDRAM_RDCC, 0x40000000);
2437 mtsdram(SDRAM_RFDC, 0x000001DF);
2441 /*------------------------------------------------------------------
2442 * Program RDCC register
2443 * Read sample cycle auto-update enable
2444 *-----------------------------------------------------------------*/
2446 mfsdram(SDRAM_RDCC, val);
2448 (val & ~(SDRAM_RDCC_RDSS_MASK | SDRAM_RDCC_RSAE_MASK))
2449 | SDRAM_RDCC_RSAE_ENABLE);
2451 /*------------------------------------------------------------------
2452 * Program RQDC register
2453 * Internal DQS delay mechanism enable
2454 *-----------------------------------------------------------------*/
2455 mtsdram(SDRAM_RQDC, (SDRAM_RQDC_RQDE_ENABLE|SDRAM_RQDC_RQFD_ENCODE(0x38)));
2457 /*------------------------------------------------------------------
2458 * Program RFDC register
2459 * Set Feedback Fractional Oversample
2460 * Auto-detect read sample cycle enable
2461 * Set RFOS to 1/4 of memclk cycle (0x3f)
2462 *-----------------------------------------------------------------*/
2463 mfsdram(SDRAM_RFDC, val);
2465 (val & ~(SDRAM_RFDC_ARSE_MASK | SDRAM_RFDC_RFOS_MASK |
2466 SDRAM_RFDC_RFFD_MASK))
2467 | (SDRAM_RFDC_ARSE_ENABLE | SDRAM_RFDC_RFOS_ENCODE(0x3f) |
2468 SDRAM_RFDC_RFFD_ENCODE(0)));
2470 DQS_calibration_process();
2474 static int short_mem_test(void)
2481 phys_size_t base_addr;
2482 u32 test[NUMMEMTESTS][NUMMEMWORDS] = {
2483 {0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
2484 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF},
2485 {0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
2486 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000},
2487 {0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
2488 0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555},
2489 {0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
2490 0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA},
2491 {0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
2492 0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A},
2493 {0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
2494 0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5},
2495 {0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
2496 0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA},
2497 {0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
2498 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55} };
2501 for (bxcr_num = 0; bxcr_num < MAXBXCF; bxcr_num++) {
2502 mfsdram(SDRAM_MB0CF + (bxcr_num << 2), bxcf);
2505 if ((bxcf & SDRAM_BXCF_M_BE_MASK) == SDRAM_BXCF_M_BE_ENABLE) {
2506 /* Bank is enabled */
2509 * Only run test on accessable memory (below 2GB)
2511 base_addr = SDRAM_RXBAS_SDBA_DECODE(mfdcr_any(SDRAM_R0BAS+bxcr_num));
2512 if (base_addr >= CONFIG_MAX_MEM_MAPPED)
2515 /*------------------------------------------------------------------
2516 * Run the short memory test.
2517 *-----------------------------------------------------------------*/
2518 membase = (u32 *)(u32)base_addr;
2520 for (i = 0; i < NUMMEMTESTS; i++) {
2521 for (j = 0; j < NUMMEMWORDS; j++) {
2522 membase[j] = test[i][j];
2523 ppcDcbf((u32)&(membase[j]));
2526 for (l=0; l<NUMLOOPS; l++) {
2527 for (j = 0; j < NUMMEMWORDS; j++) {
2528 if (membase[j] != test[i][j]) {
2529 ppcDcbf((u32)&(membase[j]));
2532 ppcDcbf((u32)&(membase[j]));
2537 } /* if bank enabled */
2538 } /* for bxcf_num */
2543 #ifndef HARD_CODED_DQS
2544 /*-----------------------------------------------------------------------------+
2545 * DQS_calibration_process.
2546 *-----------------------------------------------------------------------------*/
2547 static void DQS_calibration_process(void)
2549 unsigned long rfdc_reg;
2555 unsigned long begin_rqfd[MAXRANKS];
2556 unsigned long begin_rffd[MAXRANKS];
2557 unsigned long end_rqfd[MAXRANKS];
2558 unsigned long end_rffd[MAXRANKS];
2560 unsigned long dlycal;
2561 unsigned long dly_val;
2562 unsigned long max_pass_length;
2563 unsigned long current_pass_length;
2564 unsigned long current_fail_length;
2565 unsigned long current_start;
2567 unsigned char fail_found;
2568 unsigned char pass_found;
2569 #if !defined(CONFIG_DDR_RQDC_FIXED)
2575 char str[] = "Auto calibration -";
2576 char slash[] = "\\|/-\\|/-";
2578 /*------------------------------------------------------------------
2579 * Test to determine the best read clock delay tuning bits.
2581 * Before the DDR controller can be used, the read clock delay needs to be
2582 * set. This is SDRAM_RQDC[RQFD] and SDRAM_RFDC[RFFD].
2583 * This value cannot be hardcoded into the program because it changes
2584 * depending on the board's setup and environment.
2585 * To do this, all delay values are tested to see if they
2586 * work or not. By doing this, you get groups of fails with groups of
2587 * passing values. The idea is to find the start and end of a passing
2588 * window and take the center of it to use as the read clock delay.
2590 * A failure has to be seen first so that when we hit a pass, we know
2591 * that it is truely the start of the window. If we get passing values
2592 * to start off with, we don't know if we are at the start of the window.
2594 * The code assumes that a failure will always be found.
2595 * If a failure is not found, there is no easy way to get the middle
2596 * of the passing window. I guess we can pretty much pick any value
2597 * but some values will be better than others. Since the lowest speed
2598 * we can clock the DDR interface at is 200 MHz (2x 100 MHz PLB speed),
2599 * from experimentation it is safe to say you will always have a failure.
2600 *-----------------------------------------------------------------*/
2602 /* first fix RQDC[RQFD] to an average of 80 degre phase shift to find RFDC[RFFD] */
2603 rqfd_start = 64; /* test-only: don't know if this is the _best_ start value */
2608 mfsdram(SDRAM_RQDC, rqdc_reg);
2609 mtsdram(SDRAM_RQDC, (rqdc_reg & ~SDRAM_RQDC_RQFD_MASK) |
2610 SDRAM_RQDC_RQFD_ENCODE(rqfd_start));
2611 #else /* CONFIG_DDR_RQDC_FIXED */
2613 * On Katmai the complete auto-calibration somehow doesn't seem to
2614 * produce the best results, meaning optimal values for RQFD/RFFD.
2615 * This was discovered by GDA using a high bandwidth scope,
2616 * analyzing the DDR2 signals. GDA provided a fixed value for RQFD,
2617 * so now on Katmai "only" RFFD is auto-calibrated.
2619 mtsdram(SDRAM_RQDC, CONFIG_DDR_RQDC_FIXED);
2620 #endif /* CONFIG_DDR_RQDC_FIXED */
2632 window_found = FALSE;
2634 max_pass_length = 0;
2637 current_pass_length = 0;
2638 current_fail_length = 0;
2640 window_found = FALSE;
2645 * get the delay line calibration register value
2647 mfsdram(SDRAM_DLCR, dlycal);
2648 dly_val = SDRAM_DLYCAL_DLCV_DECODE(dlycal) << 2;
2650 for (rffd = 0; rffd <= SDRAM_RFDC_RFFD_MAX; rffd++) {
2651 mfsdram(SDRAM_RFDC, rfdc_reg);
2652 rfdc_reg &= ~(SDRAM_RFDC_RFFD_MASK);
2654 /*------------------------------------------------------------------
2655 * Set the timing reg for the test.
2656 *-----------------------------------------------------------------*/
2657 mtsdram(SDRAM_RFDC, rfdc_reg | SDRAM_RFDC_RFFD_ENCODE(rffd));
2659 /*------------------------------------------------------------------
2660 * See if the rffd value passed.
2661 *-----------------------------------------------------------------*/
2662 if (short_mem_test()) {
2663 if (fail_found == TRUE) {
2665 if (current_pass_length == 0)
2666 current_start = rffd;
2668 current_fail_length = 0;
2669 current_pass_length++;
2671 if (current_pass_length > max_pass_length) {
2672 max_pass_length = current_pass_length;
2673 max_start = current_start;
2678 current_pass_length = 0;
2679 current_fail_length++;
2681 if (current_fail_length >= (dly_val >> 2)) {
2682 if (fail_found == FALSE) {
2684 } else if (pass_found == TRUE) {
2685 window_found = TRUE;
2692 /*------------------------------------------------------------------
2693 * Set the average RFFD value
2694 *-----------------------------------------------------------------*/
2695 rffd_average = ((max_start + max_end) >> 1);
2697 if (rffd_average < 0)
2700 if (rffd_average > SDRAM_RFDC_RFFD_MAX)
2701 rffd_average = SDRAM_RFDC_RFFD_MAX;
2702 /* now fix RFDC[RFFD] found and find RQDC[RQFD] */
2703 mtsdram(SDRAM_RFDC, rfdc_reg | SDRAM_RFDC_RFFD_ENCODE(rffd_average));
2705 #if !defined(CONFIG_DDR_RQDC_FIXED)
2706 max_pass_length = 0;
2709 current_pass_length = 0;
2710 current_fail_length = 0;
2712 window_found = FALSE;
2716 for (rqfd = 0; rqfd <= SDRAM_RQDC_RQFD_MAX; rqfd++) {
2717 mfsdram(SDRAM_RQDC, rqdc_reg);
2718 rqdc_reg &= ~(SDRAM_RQDC_RQFD_MASK);
2720 /*------------------------------------------------------------------
2721 * Set the timing reg for the test.
2722 *-----------------------------------------------------------------*/
2723 mtsdram(SDRAM_RQDC, rqdc_reg | SDRAM_RQDC_RQFD_ENCODE(rqfd));
2725 /*------------------------------------------------------------------
2726 * See if the rffd value passed.
2727 *-----------------------------------------------------------------*/
2728 if (short_mem_test()) {
2729 if (fail_found == TRUE) {
2731 if (current_pass_length == 0)
2732 current_start = rqfd;
2734 current_fail_length = 0;
2735 current_pass_length++;
2737 if (current_pass_length > max_pass_length) {
2738 max_pass_length = current_pass_length;
2739 max_start = current_start;
2744 current_pass_length = 0;
2745 current_fail_length++;
2747 if (fail_found == FALSE) {
2749 } else if (pass_found == TRUE) {
2750 window_found = TRUE;
2756 rqfd_average = ((max_start + max_end) >> 1);
2758 /*------------------------------------------------------------------
2759 * Make sure we found the valid read passing window. Halt if not
2760 *-----------------------------------------------------------------*/
2761 if (window_found == FALSE) {
2762 if (rqfd_start < SDRAM_RQDC_RQFD_MAX) {
2764 putc(slash[loopi++ % 8]);
2766 /* try again from with a different RQFD start value */
2768 goto calibration_loop;
2771 printf("\nERROR: Cannot determine a common read delay for the "
2772 "DIMM(s) installed.\n");
2773 debug("%s[%d] ERROR : \n", __FUNCTION__,__LINE__);
2774 ppc4xx_ibm_ddr2_register_dump();
2775 spd_ddr_init_hang ();
2778 if (rqfd_average < 0)
2781 if (rqfd_average > SDRAM_RQDC_RQFD_MAX)
2782 rqfd_average = SDRAM_RQDC_RQFD_MAX;
2785 (rqdc_reg & ~SDRAM_RQDC_RQFD_MASK) |
2786 SDRAM_RQDC_RQFD_ENCODE(rqfd_average));
2788 blank_string(strlen(str));
2789 #endif /* CONFIG_DDR_RQDC_FIXED */
2792 * Now complete RDSS configuration as mentioned on page 7 of the AMCC
2793 * PowerPC440SP/SPe DDR2 application note:
2794 * "DDR1/DDR2 Initialization Sequence and Dynamic Tuning"
2796 mfsdram(SDRAM_RTSR, val);
2797 if ((val & SDRAM_RTSR_TRK1SM_MASK) == SDRAM_RTSR_TRK1SM_ATPLS1) {
2798 mfsdram(SDRAM_RDCC, val);
2799 if ((val & SDRAM_RDCC_RDSS_MASK) != SDRAM_RDCC_RDSS_T4) {
2801 mtsdram(SDRAM_RDCC, val);
2805 mfsdram(SDRAM_DLCR, val);
2806 debug("%s[%d] DLCR: 0x%08X\n", __FUNCTION__, __LINE__, val);
2807 mfsdram(SDRAM_RQDC, val);
2808 debug("%s[%d] RQDC: 0x%08X\n", __FUNCTION__, __LINE__, val);
2809 mfsdram(SDRAM_RFDC, val);
2810 debug("%s[%d] RFDC: 0x%08X\n", __FUNCTION__, __LINE__, val);
2811 mfsdram(SDRAM_RDCC, val);
2812 debug("%s[%d] RDCC: 0x%08X\n", __FUNCTION__, __LINE__, val);
2814 #else /* calibration test with hardvalues */
2815 /*-----------------------------------------------------------------------------+
2816 * DQS_calibration_process.
2817 *-----------------------------------------------------------------------------*/
2818 static void test(void)
2820 unsigned long dimm_num;
2821 unsigned long ecc_temp;
2823 unsigned long *membase;
2824 unsigned long bxcf[MAXRANKS];
2827 char begin_found[MAXDIMMS];
2828 char end_found[MAXDIMMS];
2829 char search_end[MAXDIMMS];
2830 unsigned long test[NUMMEMTESTS][NUMMEMWORDS] = {
2831 {0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
2832 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF},
2833 {0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
2834 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000},
2835 {0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
2836 0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555},
2837 {0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
2838 0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA},
2839 {0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
2840 0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A},
2841 {0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
2842 0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5},
2843 {0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
2844 0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA},
2845 {0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
2846 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55} };
2848 /*------------------------------------------------------------------
2849 * Test to determine the best read clock delay tuning bits.
2851 * Before the DDR controller can be used, the read clock delay needs to be
2852 * set. This is SDRAM_RQDC[RQFD] and SDRAM_RFDC[RFFD].
2853 * This value cannot be hardcoded into the program because it changes
2854 * depending on the board's setup and environment.
2855 * To do this, all delay values are tested to see if they
2856 * work or not. By doing this, you get groups of fails with groups of
2857 * passing values. The idea is to find the start and end of a passing
2858 * window and take the center of it to use as the read clock delay.
2860 * A failure has to be seen first so that when we hit a pass, we know
2861 * that it is truely the start of the window. If we get passing values
2862 * to start off with, we don't know if we are at the start of the window.
2864 * The code assumes that a failure will always be found.
2865 * If a failure is not found, there is no easy way to get the middle
2866 * of the passing window. I guess we can pretty much pick any value
2867 * but some values will be better than others. Since the lowest speed
2868 * we can clock the DDR interface at is 200 MHz (2x 100 MHz PLB speed),
2869 * from experimentation it is safe to say you will always have a failure.
2870 *-----------------------------------------------------------------*/
2871 mfsdram(SDRAM_MCOPT1, ecc_temp);
2872 ecc_temp &= SDRAM_MCOPT1_MCHK_MASK;
2873 mfsdram(SDRAM_MCOPT1, val);
2874 mtsdram(SDRAM_MCOPT1, (val & ~SDRAM_MCOPT1_MCHK_MASK) |
2875 SDRAM_MCOPT1_MCHK_NON);
2877 window_found = FALSE;
2878 begin_found[0] = FALSE;
2879 end_found[0] = FALSE;
2880 search_end[0] = FALSE;
2881 begin_found[1] = FALSE;
2882 end_found[1] = FALSE;
2883 search_end[1] = FALSE;
2885 for (dimm_num = 0; dimm_num < MAXDIMMS; dimm_num++) {
2886 mfsdram(SDRAM_MB0CF + (bxcr_num << 2), bxcf[bxcr_num]);
2889 if ((bxcf[dimm_num] & SDRAM_BXCF_M_BE_MASK) == SDRAM_BXCF_M_BE_ENABLE) {
2891 /* Bank is enabled */
2893 (unsigned long*)(SDRAM_RXBAS_SDBA_DECODE(mfdcr_any(SDRAM_R0BAS+dimm_num)));
2895 /*------------------------------------------------------------------
2896 * Run the short memory test.
2897 *-----------------------------------------------------------------*/
2898 for (i = 0; i < NUMMEMTESTS; i++) {
2899 for (j = 0; j < NUMMEMWORDS; j++) {
2900 membase[j] = test[i][j];
2901 ppcDcbf((u32)&(membase[j]));
2904 for (j = 0; j < NUMMEMWORDS; j++) {
2905 if (membase[j] != test[i][j]) {
2906 ppcDcbf((u32)&(membase[j]));
2909 ppcDcbf((u32)&(membase[j]));
2912 if (j < NUMMEMWORDS)
2916 /*------------------------------------------------------------------
2917 * See if the rffd value passed.
2918 *-----------------------------------------------------------------*/
2919 if (i < NUMMEMTESTS) {
2920 if ((end_found[dimm_num] == FALSE) &&
2921 (search_end[dimm_num] == TRUE)) {
2922 end_found[dimm_num] = TRUE;
2924 if ((end_found[0] == TRUE) &&
2925 (end_found[1] == TRUE))
2928 if (begin_found[dimm_num] == FALSE) {
2929 begin_found[dimm_num] = TRUE;
2930 search_end[dimm_num] = TRUE;
2934 begin_found[dimm_num] = TRUE;
2935 end_found[dimm_num] = TRUE;
2939 if ((begin_found[0] == TRUE) && (begin_found[1] == TRUE))
2940 window_found = TRUE;
2942 /*------------------------------------------------------------------
2943 * Make sure we found the valid read passing window. Halt if not
2944 *-----------------------------------------------------------------*/
2945 if (window_found == FALSE) {
2946 printf("ERROR: Cannot determine a common read delay for the "
2947 "DIMM(s) installed.\n");
2948 spd_ddr_init_hang ();
2951 /*------------------------------------------------------------------
2952 * Restore the ECC variable to what it originally was
2953 *-----------------------------------------------------------------*/
2954 mtsdram(SDRAM_MCOPT1,
2955 (ppcMfdcr_sdram(SDRAM_MCOPT1) & ~SDRAM_MCOPT1_MCHK_MASK)
2958 #endif /* !HARD_CODED_DQS */
2959 #endif /* !defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION) */
2961 #else /* CONFIG_SPD_EEPROM */
2963 /*-----------------------------------------------------------------------------
2964 * Function: initdram
2965 * Description: Configures the PPC4xx IBM DDR1/DDR2 SDRAM memory controller.
2966 * The configuration is performed using static, compile-
2968 * Configures the PPC405EX(r) and PPC460EX/GT
2969 *---------------------------------------------------------------------------*/
2970 phys_size_t initdram(int board_type)
2973 * Only run this SDRAM init code once. For NAND booting
2974 * targets like Kilauea, we call initdram() early from the
2975 * 4k NAND booting image (CONFIG_NAND_SPL) from nand_boot().
2976 * Later on the NAND U-Boot image runs (CONFIG_NAND_U_BOOT)
2977 * which calls initdram() again. This time the controller
2978 * mustn't be reconfigured again since we're already running
2981 #if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
2984 #if defined(CONFIG_440)
2985 mtdcr(SDRAM_R0BAS, CONFIG_SYS_SDRAM_R0BAS);
2986 mtdcr(SDRAM_R1BAS, CONFIG_SYS_SDRAM_R1BAS);
2987 mtdcr(SDRAM_R2BAS, CONFIG_SYS_SDRAM_R2BAS);
2988 mtdcr(SDRAM_R3BAS, CONFIG_SYS_SDRAM_R3BAS);
2989 mtdcr(SDRAM_PLBADDULL, CONFIG_SYS_SDRAM_PLBADDULL); /* MQ0_BAUL */
2990 mtdcr(SDRAM_PLBADDUHB, CONFIG_SYS_SDRAM_PLBADDUHB); /* MQ0_BAUH */
2991 mtdcr(SDRAM_CONF1LL, CONFIG_SYS_SDRAM_CONF1LL);
2992 mtdcr(SDRAM_CONF1HB, CONFIG_SYS_SDRAM_CONF1HB);
2993 mtdcr(SDRAM_CONFPATHB, CONFIG_SYS_SDRAM_CONFPATHB);
2996 /* Set Memory Bank Configuration Registers */
2998 mtsdram(SDRAM_MB0CF, CONFIG_SYS_SDRAM0_MB0CF);
2999 mtsdram(SDRAM_MB1CF, CONFIG_SYS_SDRAM0_MB1CF);
3000 mtsdram(SDRAM_MB2CF, CONFIG_SYS_SDRAM0_MB2CF);
3001 mtsdram(SDRAM_MB3CF, CONFIG_SYS_SDRAM0_MB3CF);
3003 /* Set Memory Clock Timing Register */
3005 mtsdram(SDRAM_CLKTR, CONFIG_SYS_SDRAM0_CLKTR);
3007 /* Set Refresh Time Register */
3009 mtsdram(SDRAM_RTR, CONFIG_SYS_SDRAM0_RTR);
3011 /* Set SDRAM Timing Registers */
3013 mtsdram(SDRAM_SDTR1, CONFIG_SYS_SDRAM0_SDTR1);
3014 mtsdram(SDRAM_SDTR2, CONFIG_SYS_SDRAM0_SDTR2);
3015 mtsdram(SDRAM_SDTR3, CONFIG_SYS_SDRAM0_SDTR3);
3017 /* Set Mode and Extended Mode Registers */
3019 mtsdram(SDRAM_MMODE, CONFIG_SYS_SDRAM0_MMODE);
3020 mtsdram(SDRAM_MEMODE, CONFIG_SYS_SDRAM0_MEMODE);
3022 /* Set Memory Controller Options 1 Register */
3024 mtsdram(SDRAM_MCOPT1, CONFIG_SYS_SDRAM0_MCOPT1);
3026 /* Set Manual Initialization Control Registers */
3028 mtsdram(SDRAM_INITPLR0, CONFIG_SYS_SDRAM0_INITPLR0);
3029 mtsdram(SDRAM_INITPLR1, CONFIG_SYS_SDRAM0_INITPLR1);
3030 mtsdram(SDRAM_INITPLR2, CONFIG_SYS_SDRAM0_INITPLR2);
3031 mtsdram(SDRAM_INITPLR3, CONFIG_SYS_SDRAM0_INITPLR3);
3032 mtsdram(SDRAM_INITPLR4, CONFIG_SYS_SDRAM0_INITPLR4);
3033 mtsdram(SDRAM_INITPLR5, CONFIG_SYS_SDRAM0_INITPLR5);
3034 mtsdram(SDRAM_INITPLR6, CONFIG_SYS_SDRAM0_INITPLR6);
3035 mtsdram(SDRAM_INITPLR7, CONFIG_SYS_SDRAM0_INITPLR7);
3036 mtsdram(SDRAM_INITPLR8, CONFIG_SYS_SDRAM0_INITPLR8);
3037 mtsdram(SDRAM_INITPLR9, CONFIG_SYS_SDRAM0_INITPLR9);
3038 mtsdram(SDRAM_INITPLR10, CONFIG_SYS_SDRAM0_INITPLR10);
3039 mtsdram(SDRAM_INITPLR11, CONFIG_SYS_SDRAM0_INITPLR11);
3040 mtsdram(SDRAM_INITPLR12, CONFIG_SYS_SDRAM0_INITPLR12);
3041 mtsdram(SDRAM_INITPLR13, CONFIG_SYS_SDRAM0_INITPLR13);
3042 mtsdram(SDRAM_INITPLR14, CONFIG_SYS_SDRAM0_INITPLR14);
3043 mtsdram(SDRAM_INITPLR15, CONFIG_SYS_SDRAM0_INITPLR15);
3045 /* Set On-Die Termination Registers */
3047 mtsdram(SDRAM_CODT, CONFIG_SYS_SDRAM0_CODT);
3048 mtsdram(SDRAM_MODT0, CONFIG_SYS_SDRAM0_MODT0);
3049 mtsdram(SDRAM_MODT1, CONFIG_SYS_SDRAM0_MODT1);
3051 /* Set Write Timing Register */
3053 mtsdram(SDRAM_WRDTR, CONFIG_SYS_SDRAM0_WRDTR);
3056 * Start Initialization by SDRAM0_MCOPT2[SREN] = 0 and
3057 * SDRAM0_MCOPT2[IPTR] = 1
3060 mtsdram(SDRAM_MCOPT2, (SDRAM_MCOPT2_SREN_EXIT |
3061 SDRAM_MCOPT2_IPTR_EXECUTE));
3064 * Poll SDRAM0_MCSTAT[MIC] for assertion to indicate the
3065 * completion of initialization.
3069 mfsdram(SDRAM_MCSTAT, val);
3070 } while ((val & SDRAM_MCSTAT_MIC_MASK) != SDRAM_MCSTAT_MIC_COMP);
3072 /* Set Delay Control Registers */
3074 mtsdram(SDRAM_DLCR, CONFIG_SYS_SDRAM0_DLCR);
3076 #if !defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION)
3077 mtsdram(SDRAM_RDCC, CONFIG_SYS_SDRAM0_RDCC);
3078 mtsdram(SDRAM_RQDC, CONFIG_SYS_SDRAM0_RQDC);
3079 mtsdram(SDRAM_RFDC, CONFIG_SYS_SDRAM0_RFDC);
3080 #endif /* !CONFIG_PPC4xx_DDR_AUTOCALIBRATION */
3083 * Enable Controller by SDRAM0_MCOPT2[DCEN] = 1:
3086 mfsdram(SDRAM_MCOPT2, val);
3087 mtsdram(SDRAM_MCOPT2, val | SDRAM_MCOPT2_DCEN_ENABLE);
3089 #if defined(CONFIG_440)
3091 * Program TLB entries with caches enabled, for best performace
3092 * while auto-calibrating and ECC generation
3094 program_tlb(0, 0, (CONFIG_SYS_MBYTES_SDRAM << 20), 0);
3097 #if defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION)
3098 #if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
3099 /*------------------------------------------------------------------
3101 +-----------------------------------------------------------------*/
3102 DQS_autocalibration();
3103 #endif /* !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) */
3104 #endif /* CONFIG_PPC4xx_DDR_AUTOCALIBRATION */
3106 #if defined(CONFIG_DDR_ECC)
3107 ecc_init(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MBYTES_SDRAM << 20);
3108 #endif /* defined(CONFIG_DDR_ECC) */
3110 #if defined(CONFIG_440)
3112 * Now after initialization (auto-calibration and ECC generation)
3113 * remove the TLB entries with caches enabled and program again with
3114 * desired cache functionality
3116 remove_tlb(0, (CONFIG_SYS_MBYTES_SDRAM << 20));
3117 program_tlb(0, 0, (CONFIG_SYS_MBYTES_SDRAM << 20), MY_TLB_WORD2_I_ENABLE);
3120 ppc4xx_ibm_ddr2_register_dump();
3122 #if defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION)
3124 * Clear potential errors resulting from auto-calibration.
3125 * If not done, then we could get an interrupt later on when
3126 * exceptions are enabled.
3128 set_mcsr(get_mcsr());
3129 #endif /* CONFIG_PPC4xx_DDR_AUTOCALIBRATION */
3131 #endif /* !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) */
3133 return (CONFIG_SYS_MBYTES_SDRAM << 20);
3135 #endif /* CONFIG_SPD_EEPROM */
3137 #if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
3138 #if defined(CONFIG_440)
3139 u32 mfdcr_any(u32 dcr)
3144 case SDRAM_R0BAS + 0:
3145 val = mfdcr(SDRAM_R0BAS + 0);
3147 case SDRAM_R0BAS + 1:
3148 val = mfdcr(SDRAM_R0BAS + 1);
3150 case SDRAM_R0BAS + 2:
3151 val = mfdcr(SDRAM_R0BAS + 2);
3153 case SDRAM_R0BAS + 3:
3154 val = mfdcr(SDRAM_R0BAS + 3);
3157 printf("DCR %d not defined in case statement!!!\n", dcr);
3158 val = 0; /* just to satisfy the compiler */
3164 void mtdcr_any(u32 dcr, u32 val)
3167 case SDRAM_R0BAS + 0:
3168 mtdcr(SDRAM_R0BAS + 0, val);
3170 case SDRAM_R0BAS + 1:
3171 mtdcr(SDRAM_R0BAS + 1, val);
3173 case SDRAM_R0BAS + 2:
3174 mtdcr(SDRAM_R0BAS + 2, val);
3176 case SDRAM_R0BAS + 3:
3177 mtdcr(SDRAM_R0BAS + 3, val);
3180 printf("DCR %d not defined in case statement!!!\n", dcr);
3183 #endif /* defined(CONFIG_440) */
3185 void blank_string(int size)
3189 for (i = 0; i < size; i++)
3191 for (i = 0; i < size; i++)
3193 for (i = 0; i < size; i++)
3196 #endif /* !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) */
3198 inline void ppc4xx_ibm_ddr2_register_dump(void)
3201 printf("\nPPC4xx IBM DDR2 Register Dump:\n");
3203 #if (defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
3204 defined(CONFIG_460EX) || defined(CONFIG_460GT))
3205 PPC4xx_IBM_DDR2_DUMP_REGISTER(R0BAS);
3206 PPC4xx_IBM_DDR2_DUMP_REGISTER(R1BAS);
3207 PPC4xx_IBM_DDR2_DUMP_REGISTER(R2BAS);
3208 PPC4xx_IBM_DDR2_DUMP_REGISTER(R3BAS);
3209 #endif /* (defined(CONFIG_440SP) || ... */
3210 #if defined(CONFIG_405EX)
3211 PPC4xx_IBM_DDR2_DUMP_REGISTER(BESR);
3212 PPC4xx_IBM_DDR2_DUMP_REGISTER(BEARL);
3213 PPC4xx_IBM_DDR2_DUMP_REGISTER(BEARH);
3214 PPC4xx_IBM_DDR2_DUMP_REGISTER(WMIRQ);
3215 PPC4xx_IBM_DDR2_DUMP_REGISTER(PLBOPT);
3216 PPC4xx_IBM_DDR2_DUMP_REGISTER(PUABA);
3217 #endif /* defined(CONFIG_405EX) */
3218 PPC4xx_IBM_DDR2_DUMP_REGISTER(MB0CF);
3219 PPC4xx_IBM_DDR2_DUMP_REGISTER(MB1CF);
3220 PPC4xx_IBM_DDR2_DUMP_REGISTER(MB2CF);
3221 PPC4xx_IBM_DDR2_DUMP_REGISTER(MB3CF);
3222 PPC4xx_IBM_DDR2_DUMP_REGISTER(MCSTAT);
3223 PPC4xx_IBM_DDR2_DUMP_REGISTER(MCOPT1);
3224 PPC4xx_IBM_DDR2_DUMP_REGISTER(MCOPT2);
3225 PPC4xx_IBM_DDR2_DUMP_REGISTER(MODT0);
3226 PPC4xx_IBM_DDR2_DUMP_REGISTER(MODT1);
3227 PPC4xx_IBM_DDR2_DUMP_REGISTER(MODT2);
3228 PPC4xx_IBM_DDR2_DUMP_REGISTER(MODT3);
3229 PPC4xx_IBM_DDR2_DUMP_REGISTER(CODT);
3230 #if (defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
3231 defined(CONFIG_460EX) || defined(CONFIG_460GT))
3232 PPC4xx_IBM_DDR2_DUMP_REGISTER(VVPR);
3233 PPC4xx_IBM_DDR2_DUMP_REGISTER(OPARS);
3235 * OPART is only used as a trigger register.
3237 * No data is contained in this register, and reading or writing
3238 * to is can cause bad things to happen (hangs). Just skip it and
3241 printf("%20s = N/A\n", "SDRAM_OPART");
3242 #endif /* defined(CONFIG_440SP) || ... */
3243 PPC4xx_IBM_DDR2_DUMP_REGISTER(RTR);
3244 PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR0);
3245 PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR1);
3246 PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR2);
3247 PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR3);
3248 PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR4);
3249 PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR5);
3250 PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR6);
3251 PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR7);
3252 PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR8);
3253 PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR9);
3254 PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR10);
3255 PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR11);
3256 PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR12);
3257 PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR13);
3258 PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR14);
3259 PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR15);
3260 PPC4xx_IBM_DDR2_DUMP_REGISTER(RQDC);
3261 PPC4xx_IBM_DDR2_DUMP_REGISTER(RFDC);
3262 PPC4xx_IBM_DDR2_DUMP_REGISTER(RDCC);
3263 PPC4xx_IBM_DDR2_DUMP_REGISTER(DLCR);
3264 PPC4xx_IBM_DDR2_DUMP_REGISTER(CLKTR);
3265 PPC4xx_IBM_DDR2_DUMP_REGISTER(WRDTR);
3266 PPC4xx_IBM_DDR2_DUMP_REGISTER(SDTR1);
3267 PPC4xx_IBM_DDR2_DUMP_REGISTER(SDTR2);
3268 PPC4xx_IBM_DDR2_DUMP_REGISTER(SDTR3);
3269 PPC4xx_IBM_DDR2_DUMP_REGISTER(MMODE);
3270 PPC4xx_IBM_DDR2_DUMP_REGISTER(MEMODE);
3271 PPC4xx_IBM_DDR2_DUMP_REGISTER(ECCCR);
3272 #if (defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
3273 defined(CONFIG_460EX) || defined(CONFIG_460GT))
3274 PPC4xx_IBM_DDR2_DUMP_REGISTER(CID);
3275 #endif /* defined(CONFIG_440SP) || ... */
3276 PPC4xx_IBM_DDR2_DUMP_REGISTER(RID);
3277 PPC4xx_IBM_DDR2_DUMP_REGISTER(FCSR);
3278 PPC4xx_IBM_DDR2_DUMP_REGISTER(RTSR);
3279 #endif /* defined(DEBUG) */
3282 #endif /* CONFIG_SDRAM_PPC4xx_IBM_DDR2 */