2 * cpu/ppc4xx/44x_spd_ddr2.c
3 * This SPD SDRAM detection code supports AMCC PPC44x cpu's with a
4 * DDR2 controller (non Denali Core). Those currently are:
7 * 440/460: 440SP/440SPe/460EX/460GT
9 * Copyright (c) 2008 Nuovation System Designs, LLC
10 * Grant Erickson <gerickson@nuovations.com>
12 * (C) Copyright 2007-2008
13 * Stefan Roese, DENX Software Engineering, sr@denx.de.
15 * COPYRIGHT AMCC CORPORATION 2004
17 * See file CREDITS for list of people who contributed to this
20 * This program is free software; you can redistribute it and/or
21 * modify it under the terms of the GNU General Public License as
22 * published by the Free Software Foundation; either version 2 of
23 * the License, or (at your option) any later version.
25 * This program is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU General Public License for more details.
30 * You should have received a copy of the GNU General Public License
31 * along with this program; if not, write to the Free Software
32 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
37 /* define DEBUG for debugging output (obviously ;-)) */
47 #include <asm/processor.h>
49 #include <asm/cache.h>
53 static void ppc4xx_ibm_ddr2_register_dump(void);
55 #if defined(CONFIG_SPD_EEPROM) && \
56 (defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
57 defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
58 defined(CONFIG_460SX))
60 /*-----------------------------------------------------------------------------+
62 *-----------------------------------------------------------------------------*/
77 #define MAX_SPD_BYTES 256 /* Max number of bytes on the DIMM's SPD EEPROM */
79 #define ONE_BILLION 1000000000
81 #define MULDIV64(m1, m2, d) (u32)(((u64)(m1) * (u64)(m2)) / (u64)(d))
83 #define CMD_NOP (7 << 19)
84 #define CMD_PRECHARGE (2 << 19)
85 #define CMD_REFRESH (1 << 19)
86 #define CMD_EMR (0 << 19)
87 #define CMD_READ (5 << 19)
88 #define CMD_WRITE (4 << 19)
90 #define SELECT_MR (0 << 16)
91 #define SELECT_EMR (1 << 16)
92 #define SELECT_EMR2 (2 << 16)
93 #define SELECT_EMR3 (3 << 16)
96 #define DLL_RESET 0x00000100
98 #define WRITE_RECOV_2 (1 << 9)
99 #define WRITE_RECOV_3 (2 << 9)
100 #define WRITE_RECOV_4 (3 << 9)
101 #define WRITE_RECOV_5 (4 << 9)
102 #define WRITE_RECOV_6 (5 << 9)
104 #define BURST_LEN_4 0x00000002
107 #define ODT_0_OHM 0x00000000
108 #define ODT_50_OHM 0x00000044
109 #define ODT_75_OHM 0x00000004
110 #define ODT_150_OHM 0x00000040
112 #define ODS_FULL 0x00000000
113 #define ODS_REDUCED 0x00000002
115 /* defines for ODT (On Die Termination) of the 440SP(e) DDR2 controller */
116 #define ODT_EB0R (0x80000000 >> 8)
117 #define ODT_EB0W (0x80000000 >> 7)
118 #define CALC_ODT_R(n) (ODT_EB0R << (n << 1))
119 #define CALC_ODT_W(n) (ODT_EB0W << (n << 1))
120 #define CALC_ODT_RW(n) (CALC_ODT_R(n) | CALC_ODT_W(n))
122 /* Defines for the Read Cycle Delay test */
123 #define NUMMEMTESTS 8
124 #define NUMMEMWORDS 8
125 #define NUMLOOPS 64 /* memory test loops */
128 * This DDR2 setup code can dynamically setup the TLB entries for the DDR2 memory
129 * region. Right now the cache should still be disabled in U-Boot because of the
130 * EMAC driver, that need it's buffer descriptor to be located in non cached
133 * If at some time this restriction doesn't apply anymore, just define
134 * CONFIG_4xx_DCACHE in the board config file and this code should setup
135 * everything correctly.
137 #ifdef CONFIG_4xx_DCACHE
138 #define MY_TLB_WORD2_I_ENABLE 0 /* enable caching on SDRAM */
140 #define MY_TLB_WORD2_I_ENABLE TLB_WORD2_I_ENABLE /* disable caching on SDRAM */
144 * Newer PPC's like 440SPe, 460EX/GT can be equipped with more than 2GB of SDRAM.
145 * To support such configurations, we "only" map the first 2GB via the TLB's. We
146 * need some free virtual address space for the remaining peripherals like, SoC
147 * devices, FLASH etc.
149 * Note that ECC is currently not supported on configurations with more than 2GB
150 * SDRAM. This is because we only map the first 2GB on such systems, and therefore
151 * the ECC parity byte of the remaining area can't be written.
153 #ifndef CONFIG_MAX_MEM_MAPPED
154 #define CONFIG_MAX_MEM_MAPPED ((phys_size_t)2 << 30)
158 * Board-specific Platform code can reimplement spd_ddr_init_hang () if needed
160 void __spd_ddr_init_hang (void)
164 void spd_ddr_init_hang (void) __attribute__((weak, alias("__spd_ddr_init_hang")));
167 * To provide an interface for board specific config values in this common
168 * DDR setup code, we implement he "weak" default functions here. They return
169 * the default value back to the caller.
171 * Please see include/configs/yucca.h for an example fora board specific
174 u32 __ddr_wrdtr(u32 default_val)
178 u32 ddr_wrdtr(u32) __attribute__((weak, alias("__ddr_wrdtr")));
180 u32 __ddr_clktr(u32 default_val)
184 u32 ddr_clktr(u32) __attribute__((weak, alias("__ddr_clktr")));
187 /* Private Structure Definitions */
189 /* enum only to ease code for cas latency setting */
190 typedef enum ddr_cas_id {
198 /*-----------------------------------------------------------------------------+
200 *-----------------------------------------------------------------------------*/
201 static phys_size_t sdram_memsize(void);
202 static void get_spd_info(unsigned long *dimm_populated,
203 unsigned char *iic0_dimm_addr,
204 unsigned long num_dimm_banks);
205 static void check_mem_type(unsigned long *dimm_populated,
206 unsigned char *iic0_dimm_addr,
207 unsigned long num_dimm_banks);
208 static void check_frequency(unsigned long *dimm_populated,
209 unsigned char *iic0_dimm_addr,
210 unsigned long num_dimm_banks);
211 static void check_rank_number(unsigned long *dimm_populated,
212 unsigned char *iic0_dimm_addr,
213 unsigned long num_dimm_banks);
214 static void check_voltage_type(unsigned long *dimm_populated,
215 unsigned char *iic0_dimm_addr,
216 unsigned long num_dimm_banks);
217 static void program_memory_queue(unsigned long *dimm_populated,
218 unsigned char *iic0_dimm_addr,
219 unsigned long num_dimm_banks);
220 static void program_codt(unsigned long *dimm_populated,
221 unsigned char *iic0_dimm_addr,
222 unsigned long num_dimm_banks);
223 static void program_mode(unsigned long *dimm_populated,
224 unsigned char *iic0_dimm_addr,
225 unsigned long num_dimm_banks,
226 ddr_cas_id_t *selected_cas,
227 int *write_recovery);
228 static void program_tr(unsigned long *dimm_populated,
229 unsigned char *iic0_dimm_addr,
230 unsigned long num_dimm_banks);
231 static void program_rtr(unsigned long *dimm_populated,
232 unsigned char *iic0_dimm_addr,
233 unsigned long num_dimm_banks);
234 static void program_bxcf(unsigned long *dimm_populated,
235 unsigned char *iic0_dimm_addr,
236 unsigned long num_dimm_banks);
237 static void program_copt1(unsigned long *dimm_populated,
238 unsigned char *iic0_dimm_addr,
239 unsigned long num_dimm_banks);
240 static void program_initplr(unsigned long *dimm_populated,
241 unsigned char *iic0_dimm_addr,
242 unsigned long num_dimm_banks,
243 ddr_cas_id_t selected_cas,
245 static unsigned long is_ecc_enabled(void);
246 #ifdef CONFIG_DDR_ECC
247 static void program_ecc(unsigned long *dimm_populated,
248 unsigned char *iic0_dimm_addr,
249 unsigned long num_dimm_banks,
250 unsigned long tlb_word2_i_value);
251 static void program_ecc_addr(unsigned long start_address,
252 unsigned long num_bytes,
253 unsigned long tlb_word2_i_value);
255 static void program_DQS_calibration(unsigned long *dimm_populated,
256 unsigned char *iic0_dimm_addr,
257 unsigned long num_dimm_banks);
258 #ifdef HARD_CODED_DQS /* calibration test with hardvalues */
259 static void test(void);
261 static void DQS_calibration_process(void);
263 int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
264 void dcbz_area(u32 start_address, u32 num_bytes);
266 static u32 mfdcr_any(u32 dcr)
271 case SDRAM_R0BAS + 0:
272 val = mfdcr(SDRAM_R0BAS + 0);
274 case SDRAM_R0BAS + 1:
275 val = mfdcr(SDRAM_R0BAS + 1);
277 case SDRAM_R0BAS + 2:
278 val = mfdcr(SDRAM_R0BAS + 2);
280 case SDRAM_R0BAS + 3:
281 val = mfdcr(SDRAM_R0BAS + 3);
284 printf("DCR %d not defined in case statement!!!\n", dcr);
285 val = 0; /* just to satisfy the compiler */
291 static void mtdcr_any(u32 dcr, u32 val)
294 case SDRAM_R0BAS + 0:
295 mtdcr(SDRAM_R0BAS + 0, val);
297 case SDRAM_R0BAS + 1:
298 mtdcr(SDRAM_R0BAS + 1, val);
300 case SDRAM_R0BAS + 2:
301 mtdcr(SDRAM_R0BAS + 2, val);
303 case SDRAM_R0BAS + 3:
304 mtdcr(SDRAM_R0BAS + 3, val);
307 printf("DCR %d not defined in case statement!!!\n", dcr);
311 static unsigned char spd_read(uchar chip, uint addr)
313 unsigned char data[2];
315 if (i2c_probe(chip) == 0)
316 if (i2c_read(chip, addr, 1, data, 1) == 0)
322 /*-----------------------------------------------------------------------------+
324 *-----------------------------------------------------------------------------*/
325 static phys_size_t sdram_memsize(void)
327 phys_size_t mem_size;
328 unsigned long mcopt2;
329 unsigned long mcstat;
336 mfsdram(SDRAM_MCOPT2, mcopt2);
337 mfsdram(SDRAM_MCSTAT, mcstat);
339 /* DDR controller must be enabled and not in self-refresh. */
340 /* Otherwise memsize is zero. */
341 if (((mcopt2 & SDRAM_MCOPT2_DCEN_MASK) == SDRAM_MCOPT2_DCEN_ENABLE)
342 && ((mcopt2 & SDRAM_MCOPT2_SREN_MASK) == SDRAM_MCOPT2_SREN_EXIT)
343 && ((mcstat & (SDRAM_MCSTAT_MIC_MASK | SDRAM_MCSTAT_SRMS_MASK))
344 == (SDRAM_MCSTAT_MIC_COMP | SDRAM_MCSTAT_SRMS_NOT_SF))) {
345 for (i = 0; i < MAXBXCF; i++) {
346 mfsdram(SDRAM_MB0CF + (i << 2), mb0cf);
348 if ((mb0cf & SDRAM_BXCF_M_BE_MASK) == SDRAM_BXCF_M_BE_ENABLE) {
349 sdsz = mfdcr_any(SDRAM_R0BAS + i) & SDRAM_RXBAS_SDSZ_MASK;
352 case SDRAM_RXBAS_SDSZ_8:
355 case SDRAM_RXBAS_SDSZ_16:
358 case SDRAM_RXBAS_SDSZ_32:
361 case SDRAM_RXBAS_SDSZ_64:
364 case SDRAM_RXBAS_SDSZ_128:
367 case SDRAM_RXBAS_SDSZ_256:
370 case SDRAM_RXBAS_SDSZ_512:
373 case SDRAM_RXBAS_SDSZ_1024:
376 case SDRAM_RXBAS_SDSZ_2048:
379 case SDRAM_RXBAS_SDSZ_4096:
383 printf("WARNING: Unsupported bank size (SDSZ=0x%lx)!\n"
392 return mem_size << 20;
395 /*-----------------------------------------------------------------------------+
396 * initdram. Initializes the 440SP Memory Queue and DDR SDRAM controller.
397 * Note: This routine runs from flash with a stack set up in the chip's
398 * sram space. It is important that the routine does not require .sbss, .bss or
399 * .data sections. It also cannot call routines that require these sections.
400 *-----------------------------------------------------------------------------*/
401 /*-----------------------------------------------------------------------------
403 * Description: Configures SDRAM memory banks for DDR operation.
404 * Auto Memory Configuration option reads the DDR SDRAM EEPROMs
405 * via the IIC bus and then configures the DDR SDRAM memory
406 * banks appropriately. If Auto Memory Configuration is
407 * not used, it is assumed that no DIMM is plugged
408 *-----------------------------------------------------------------------------*/
409 phys_size_t initdram(int board_type)
411 unsigned char iic0_dimm_addr[] = SPD_EEPROM_ADDRESS;
412 unsigned char spd0[MAX_SPD_BYTES];
413 unsigned char spd1[MAX_SPD_BYTES];
414 unsigned char *dimm_spd[MAXDIMMS];
415 unsigned long dimm_populated[MAXDIMMS];
416 unsigned long num_dimm_banks; /* on board dimm banks */
418 ddr_cas_id_t selected_cas = DDR_CAS_5; /* preset to silence compiler */
420 phys_size_t dram_size = 0;
422 num_dimm_banks = sizeof(iic0_dimm_addr);
424 /*------------------------------------------------------------------
425 * Set up an array of SPD matrixes.
426 *-----------------------------------------------------------------*/
430 /*------------------------------------------------------------------
431 * Reset the DDR-SDRAM controller.
432 *-----------------------------------------------------------------*/
433 mtsdr(SDR0_SRST, (0x80000000 >> 10));
434 mtsdr(SDR0_SRST, 0x00000000);
437 * Make sure I2C controller is initialized
441 /* switch to correct I2C bus */
442 I2C_SET_BUS(CFG_SPD_BUS_NUM);
443 i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE);
445 /*------------------------------------------------------------------
446 * Clear out the serial presence detect buffers.
447 * Perform IIC reads from the dimm. Fill in the spds.
448 * Check to see if the dimm slots are populated
449 *-----------------------------------------------------------------*/
450 get_spd_info(dimm_populated, iic0_dimm_addr, num_dimm_banks);
452 /*------------------------------------------------------------------
453 * Check the memory type for the dimms plugged.
454 *-----------------------------------------------------------------*/
455 check_mem_type(dimm_populated, iic0_dimm_addr, num_dimm_banks);
457 /*------------------------------------------------------------------
458 * Check the frequency supported for the dimms plugged.
459 *-----------------------------------------------------------------*/
460 check_frequency(dimm_populated, iic0_dimm_addr, num_dimm_banks);
462 /*------------------------------------------------------------------
463 * Check the total rank number.
464 *-----------------------------------------------------------------*/
465 check_rank_number(dimm_populated, iic0_dimm_addr, num_dimm_banks);
467 /*------------------------------------------------------------------
468 * Check the voltage type for the dimms plugged.
469 *-----------------------------------------------------------------*/
470 check_voltage_type(dimm_populated, iic0_dimm_addr, num_dimm_banks);
472 /*------------------------------------------------------------------
473 * Program SDRAM controller options 2 register
474 * Except Enabling of the memory controller.
475 *-----------------------------------------------------------------*/
476 mfsdram(SDRAM_MCOPT2, val);
477 mtsdram(SDRAM_MCOPT2,
479 ~(SDRAM_MCOPT2_SREN_MASK | SDRAM_MCOPT2_PMEN_MASK |
480 SDRAM_MCOPT2_IPTR_MASK | SDRAM_MCOPT2_XSRP_MASK |
481 SDRAM_MCOPT2_ISIE_MASK))
482 | (SDRAM_MCOPT2_SREN_ENTER | SDRAM_MCOPT2_PMEN_DISABLE |
483 SDRAM_MCOPT2_IPTR_IDLE | SDRAM_MCOPT2_XSRP_ALLOW |
484 SDRAM_MCOPT2_ISIE_ENABLE));
486 /*------------------------------------------------------------------
487 * Program SDRAM controller options 1 register
488 * Note: Does not enable the memory controller.
489 *-----------------------------------------------------------------*/
490 program_copt1(dimm_populated, iic0_dimm_addr, num_dimm_banks);
492 /*------------------------------------------------------------------
493 * Set the SDRAM Controller On Die Termination Register
494 *-----------------------------------------------------------------*/
495 program_codt(dimm_populated, iic0_dimm_addr, num_dimm_banks);
497 /*------------------------------------------------------------------
498 * Program SDRAM refresh register.
499 *-----------------------------------------------------------------*/
500 program_rtr(dimm_populated, iic0_dimm_addr, num_dimm_banks);
502 /*------------------------------------------------------------------
503 * Program SDRAM mode register.
504 *-----------------------------------------------------------------*/
505 program_mode(dimm_populated, iic0_dimm_addr, num_dimm_banks,
506 &selected_cas, &write_recovery);
508 /*------------------------------------------------------------------
509 * Set the SDRAM Write Data/DM/DQS Clock Timing Reg
510 *-----------------------------------------------------------------*/
511 mfsdram(SDRAM_WRDTR, val);
512 mtsdram(SDRAM_WRDTR, (val & ~(SDRAM_WRDTR_LLWP_MASK | SDRAM_WRDTR_WTR_MASK)) |
513 ddr_wrdtr(SDRAM_WRDTR_LLWP_1_CYC | SDRAM_WRDTR_WTR_90_DEG_ADV));
515 /*------------------------------------------------------------------
516 * Set the SDRAM Clock Timing Register
517 *-----------------------------------------------------------------*/
518 mfsdram(SDRAM_CLKTR, val);
519 mtsdram(SDRAM_CLKTR, (val & ~SDRAM_CLKTR_CLKP_MASK) |
520 ddr_clktr(SDRAM_CLKTR_CLKP_0_DEG));
522 /*------------------------------------------------------------------
523 * Program the BxCF registers.
524 *-----------------------------------------------------------------*/
525 program_bxcf(dimm_populated, iic0_dimm_addr, num_dimm_banks);
527 /*------------------------------------------------------------------
528 * Program SDRAM timing registers.
529 *-----------------------------------------------------------------*/
530 program_tr(dimm_populated, iic0_dimm_addr, num_dimm_banks);
532 /*------------------------------------------------------------------
533 * Set the Extended Mode register
534 *-----------------------------------------------------------------*/
535 mfsdram(SDRAM_MEMODE, val);
536 mtsdram(SDRAM_MEMODE,
537 (val & ~(SDRAM_MEMODE_DIC_MASK | SDRAM_MEMODE_DLL_MASK |
538 SDRAM_MEMODE_RTT_MASK | SDRAM_MEMODE_DQS_MASK)) |
539 (SDRAM_MEMODE_DIC_NORMAL | SDRAM_MEMODE_DLL_ENABLE
540 | SDRAM_MEMODE_RTT_150OHM | SDRAM_MEMODE_DQS_ENABLE));
542 /*------------------------------------------------------------------
543 * Program Initialization preload registers.
544 *-----------------------------------------------------------------*/
545 program_initplr(dimm_populated, iic0_dimm_addr, num_dimm_banks,
546 selected_cas, write_recovery);
548 /*------------------------------------------------------------------
549 * Delay to ensure 200usec have elapsed since reset.
550 *-----------------------------------------------------------------*/
553 /*------------------------------------------------------------------
554 * Set the memory queue core base addr.
555 *-----------------------------------------------------------------*/
556 program_memory_queue(dimm_populated, iic0_dimm_addr, num_dimm_banks);
558 /*------------------------------------------------------------------
559 * Program SDRAM controller options 2 register
560 * Enable the memory controller.
561 *-----------------------------------------------------------------*/
562 mfsdram(SDRAM_MCOPT2, val);
563 mtsdram(SDRAM_MCOPT2,
564 (val & ~(SDRAM_MCOPT2_SREN_MASK | SDRAM_MCOPT2_DCEN_MASK |
565 SDRAM_MCOPT2_IPTR_MASK | SDRAM_MCOPT2_ISIE_MASK)) |
566 (SDRAM_MCOPT2_DCEN_ENABLE | SDRAM_MCOPT2_IPTR_EXECUTE));
568 /*------------------------------------------------------------------
569 * Wait for SDRAM_CFG0_DC_EN to complete.
570 *-----------------------------------------------------------------*/
572 mfsdram(SDRAM_MCSTAT, val);
573 } while ((val & SDRAM_MCSTAT_MIC_MASK) == SDRAM_MCSTAT_MIC_NOTCOMP);
575 /* get installed memory size */
576 dram_size = sdram_memsize();
581 if (dram_size > CONFIG_MAX_MEM_MAPPED)
582 dram_size = CONFIG_MAX_MEM_MAPPED;
584 /* and program tlb entries for this size (dynamic) */
587 * Program TLB entries with caches enabled, for best performace
588 * while auto-calibrating and ECC generation
590 program_tlb(0, 0, dram_size, 0);
592 /*------------------------------------------------------------------
594 *-----------------------------------------------------------------*/
595 program_DQS_calibration(dimm_populated, iic0_dimm_addr, num_dimm_banks);
597 #ifdef CONFIG_DDR_ECC
598 /*------------------------------------------------------------------
599 * If ecc is enabled, initialize the parity bits.
600 *-----------------------------------------------------------------*/
601 program_ecc(dimm_populated, iic0_dimm_addr, num_dimm_banks, 0);
605 * Now after initialization (auto-calibration and ECC generation)
606 * remove the TLB entries with caches enabled and program again with
607 * desired cache functionality
609 remove_tlb(0, dram_size);
610 program_tlb(0, 0, dram_size, MY_TLB_WORD2_I_ENABLE);
612 ppc4xx_ibm_ddr2_register_dump();
615 * Clear potential errors resulting from auto-calibration.
616 * If not done, then we could get an interrupt later on when
617 * exceptions are enabled.
619 set_mcsr(get_mcsr());
621 return sdram_memsize();
624 static void get_spd_info(unsigned long *dimm_populated,
625 unsigned char *iic0_dimm_addr,
626 unsigned long num_dimm_banks)
628 unsigned long dimm_num;
629 unsigned long dimm_found;
630 unsigned char num_of_bytes;
631 unsigned char total_size;
634 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
638 num_of_bytes = spd_read(iic0_dimm_addr[dimm_num], 0);
639 debug("\nspd_read(0x%x) returned %d\n",
640 iic0_dimm_addr[dimm_num], num_of_bytes);
641 total_size = spd_read(iic0_dimm_addr[dimm_num], 1);
642 debug("spd_read(0x%x) returned %d\n",
643 iic0_dimm_addr[dimm_num], total_size);
645 if ((num_of_bytes != 0) && (total_size != 0)) {
646 dimm_populated[dimm_num] = TRUE;
648 debug("DIMM slot %lu: populated\n", dimm_num);
650 dimm_populated[dimm_num] = FALSE;
651 debug("DIMM slot %lu: Not populated\n", dimm_num);
655 if (dimm_found == FALSE) {
656 printf("ERROR - No memory installed. Install a DDR-SDRAM DIMM.\n\n");
657 spd_ddr_init_hang ();
661 void board_add_ram_info(int use_default)
663 PPC4xx_SYS_INFO board_cfg;
666 if (is_ecc_enabled())
671 get_sys_info(&board_cfg);
673 mfsdr(SDR0_DDR0, val);
674 val = MULDIV64((board_cfg.freqPLB), SDR0_DDR0_DDRM_DECODE(val), 1);
675 printf(" enabled, %d MHz", (val * 2) / 1000000);
677 mfsdram(SDRAM_MMODE, val);
678 val = (val & SDRAM_MMODE_DCL_MASK) >> 4;
679 printf(", CL%d)", val);
682 /*------------------------------------------------------------------
683 * For the memory DIMMs installed, this routine verifies that they
684 * really are DDR specific DIMMs.
685 *-----------------------------------------------------------------*/
686 static void check_mem_type(unsigned long *dimm_populated,
687 unsigned char *iic0_dimm_addr,
688 unsigned long num_dimm_banks)
690 unsigned long dimm_num;
691 unsigned long dimm_type;
693 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
694 if (dimm_populated[dimm_num] == TRUE) {
695 dimm_type = spd_read(iic0_dimm_addr[dimm_num], 2);
698 printf("ERROR: Standard Fast Page Mode DRAM DIMM detected in "
699 "slot %d.\n", (unsigned int)dimm_num);
700 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
701 printf("Replace the DIMM module with a supported DIMM.\n\n");
702 spd_ddr_init_hang ();
705 printf("ERROR: EDO DIMM detected in slot %d.\n",
706 (unsigned int)dimm_num);
707 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
708 printf("Replace the DIMM module with a supported DIMM.\n\n");
709 spd_ddr_init_hang ();
712 printf("ERROR: Pipelined Nibble DIMM detected in slot %d.\n",
713 (unsigned int)dimm_num);
714 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
715 printf("Replace the DIMM module with a supported DIMM.\n\n");
716 spd_ddr_init_hang ();
719 printf("ERROR: SDRAM DIMM detected in slot %d.\n",
720 (unsigned int)dimm_num);
721 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
722 printf("Replace the DIMM module with a supported DIMM.\n\n");
723 spd_ddr_init_hang ();
726 printf("ERROR: Multiplexed ROM DIMM detected in slot %d.\n",
727 (unsigned int)dimm_num);
728 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
729 printf("Replace the DIMM module with a supported DIMM.\n\n");
730 spd_ddr_init_hang ();
733 printf("ERROR: SGRAM DIMM detected in slot %d.\n",
734 (unsigned int)dimm_num);
735 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
736 printf("Replace the DIMM module with a supported DIMM.\n\n");
737 spd_ddr_init_hang ();
740 debug("DIMM slot %d: DDR1 SDRAM detected\n", dimm_num);
741 dimm_populated[dimm_num] = SDRAM_DDR1;
744 debug("DIMM slot %d: DDR2 SDRAM detected\n", dimm_num);
745 dimm_populated[dimm_num] = SDRAM_DDR2;
748 printf("ERROR: Unknown DIMM detected in slot %d.\n",
749 (unsigned int)dimm_num);
750 printf("Only DDR1 and DDR2 SDRAM DIMMs are supported.\n");
751 printf("Replace the DIMM module with a supported DIMM.\n\n");
752 spd_ddr_init_hang ();
757 for (dimm_num = 1; dimm_num < num_dimm_banks; dimm_num++) {
758 if ((dimm_populated[dimm_num-1] != SDRAM_NONE)
759 && (dimm_populated[dimm_num] != SDRAM_NONE)
760 && (dimm_populated[dimm_num-1] != dimm_populated[dimm_num])) {
761 printf("ERROR: DIMM's DDR1 and DDR2 type can not be mixed.\n");
762 spd_ddr_init_hang ();
767 /*------------------------------------------------------------------
768 * For the memory DIMMs installed, this routine verifies that
769 * frequency previously calculated is supported.
770 *-----------------------------------------------------------------*/
771 static void check_frequency(unsigned long *dimm_populated,
772 unsigned char *iic0_dimm_addr,
773 unsigned long num_dimm_banks)
775 unsigned long dimm_num;
776 unsigned long tcyc_reg;
777 unsigned long cycle_time;
778 unsigned long calc_cycle_time;
779 unsigned long sdram_freq;
780 unsigned long sdr_ddrpll;
781 PPC4xx_SYS_INFO board_cfg;
783 /*------------------------------------------------------------------
784 * Get the board configuration info.
785 *-----------------------------------------------------------------*/
786 get_sys_info(&board_cfg);
788 mfsdr(SDR0_DDR0, sdr_ddrpll);
789 sdram_freq = ((board_cfg.freqPLB) * SDR0_DDR0_DDRM_DECODE(sdr_ddrpll));
792 * calc_cycle_time is calculated from DDR frequency set by board/chip
793 * and is expressed in multiple of 10 picoseconds
794 * to match the way DIMM cycle time is calculated below.
796 calc_cycle_time = MULDIV64(ONE_BILLION, 100, sdram_freq);
798 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
799 if (dimm_populated[dimm_num] != SDRAM_NONE) {
800 tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 9);
802 * Byte 9, Cycle time for CAS Latency=X, is split into two nibbles:
803 * the higher order nibble (bits 4-7) designates the cycle time
804 * to a granularity of 1ns;
805 * the value presented by the lower order nibble (bits 0-3)
806 * has a granularity of .1ns and is added to the value designated
807 * by the higher nibble. In addition, four lines of the lower order
808 * nibble are assigned to support +.25,+.33, +.66 and +.75.
810 /* Convert from hex to decimal */
811 if ((tcyc_reg & 0x0F) == 0x0D)
812 cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) + 75;
813 else if ((tcyc_reg & 0x0F) == 0x0C)
814 cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) + 66;
815 else if ((tcyc_reg & 0x0F) == 0x0B)
816 cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) + 33;
817 else if ((tcyc_reg & 0x0F) == 0x0A)
818 cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) + 25;
820 cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) +
821 ((tcyc_reg & 0x0F)*10);
822 debug("cycle_time=%d [10 picoseconds]\n", cycle_time);
824 if (cycle_time > (calc_cycle_time + 10)) {
826 * the provided sdram cycle_time is too small
827 * for the available DIMM cycle_time.
828 * The additionnal 100ps is here to accept a small incertainty.
830 printf("ERROR: DRAM DIMM detected with cycle_time %d ps in "
831 "slot %d \n while calculated cycle time is %d ps.\n",
832 (unsigned int)(cycle_time*10),
833 (unsigned int)dimm_num,
834 (unsigned int)(calc_cycle_time*10));
835 printf("Replace the DIMM, or change DDR frequency via "
836 "strapping bits.\n\n");
837 spd_ddr_init_hang ();
843 /*------------------------------------------------------------------
844 * For the memory DIMMs installed, this routine verifies two
845 * ranks/banks maximum are availables.
846 *-----------------------------------------------------------------*/
847 static void check_rank_number(unsigned long *dimm_populated,
848 unsigned char *iic0_dimm_addr,
849 unsigned long num_dimm_banks)
851 unsigned long dimm_num;
852 unsigned long dimm_rank;
853 unsigned long total_rank = 0;
855 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
856 if (dimm_populated[dimm_num] != SDRAM_NONE) {
857 dimm_rank = spd_read(iic0_dimm_addr[dimm_num], 5);
858 if (((unsigned long)spd_read(iic0_dimm_addr[dimm_num], 2)) == 0x08)
859 dimm_rank = (dimm_rank & 0x0F) +1;
861 dimm_rank = dimm_rank & 0x0F;
864 if (dimm_rank > MAXRANKS) {
865 printf("ERROR: DRAM DIMM detected with %lu ranks in "
866 "slot %lu is not supported.\n", dimm_rank, dimm_num);
867 printf("Only %d ranks are supported for all DIMM.\n", MAXRANKS);
868 printf("Replace the DIMM module with a supported DIMM.\n\n");
869 spd_ddr_init_hang ();
871 total_rank += dimm_rank;
873 if (total_rank > MAXRANKS) {
874 printf("ERROR: DRAM DIMM detected with a total of %d ranks "
875 "for all slots.\n", (unsigned int)total_rank);
876 printf("Only %d ranks are supported for all DIMM.\n", MAXRANKS);
877 printf("Remove one of the DIMM modules.\n\n");
878 spd_ddr_init_hang ();
883 /*------------------------------------------------------------------
884 * only support 2.5V modules.
885 * This routine verifies this.
886 *-----------------------------------------------------------------*/
887 static void check_voltage_type(unsigned long *dimm_populated,
888 unsigned char *iic0_dimm_addr,
889 unsigned long num_dimm_banks)
891 unsigned long dimm_num;
892 unsigned long voltage_type;
894 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
895 if (dimm_populated[dimm_num] != SDRAM_NONE) {
896 voltage_type = spd_read(iic0_dimm_addr[dimm_num], 8);
897 switch (voltage_type) {
899 printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
900 printf("This DIMM is 5.0 Volt/TTL.\n");
901 printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
902 (unsigned int)dimm_num);
903 spd_ddr_init_hang ();
906 printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
907 printf("This DIMM is LVTTL.\n");
908 printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
909 (unsigned int)dimm_num);
910 spd_ddr_init_hang ();
913 printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
914 printf("This DIMM is 1.5 Volt.\n");
915 printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
916 (unsigned int)dimm_num);
917 spd_ddr_init_hang ();
920 printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
921 printf("This DIMM is 3.3 Volt/TTL.\n");
922 printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
923 (unsigned int)dimm_num);
924 spd_ddr_init_hang ();
927 /* 2.5 Voltage only for DDR1 */
930 /* 1.8 Voltage only for DDR2 */
933 printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
934 printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
935 (unsigned int)dimm_num);
936 spd_ddr_init_hang ();
943 /*-----------------------------------------------------------------------------+
945 *-----------------------------------------------------------------------------*/
946 static void program_copt1(unsigned long *dimm_populated,
947 unsigned char *iic0_dimm_addr,
948 unsigned long num_dimm_banks)
950 unsigned long dimm_num;
951 unsigned long mcopt1;
952 unsigned long ecc_enabled;
953 unsigned long ecc = 0;
954 unsigned long data_width = 0;
955 unsigned long dimm_32bit;
956 unsigned long dimm_64bit;
957 unsigned long registered = 0;
958 unsigned long attribute = 0;
959 unsigned long buf0, buf1; /* TODO: code to be changed for IOP1.6 to support 4 DIMMs */
960 unsigned long bankcount;
961 unsigned long ddrtype;
964 #ifdef CONFIG_DDR_ECC
974 /*------------------------------------------------------------------
975 * Set memory controller options reg 1, SDRAM_MCOPT1.
976 *-----------------------------------------------------------------*/
977 mfsdram(SDRAM_MCOPT1, val);
978 mcopt1 = val & ~(SDRAM_MCOPT1_MCHK_MASK | SDRAM_MCOPT1_RDEN_MASK |
979 SDRAM_MCOPT1_PMU_MASK | SDRAM_MCOPT1_DMWD_MASK |
980 SDRAM_MCOPT1_UIOS_MASK | SDRAM_MCOPT1_BCNT_MASK |
981 SDRAM_MCOPT1_DDR_TYPE_MASK | SDRAM_MCOPT1_RWOO_MASK |
982 SDRAM_MCOPT1_WOOO_MASK | SDRAM_MCOPT1_DCOO_MASK |
983 SDRAM_MCOPT1_DREF_MASK);
985 mcopt1 |= SDRAM_MCOPT1_QDEP;
986 mcopt1 |= SDRAM_MCOPT1_PMU_OPEN;
987 mcopt1 |= SDRAM_MCOPT1_RWOO_DISABLED;
988 mcopt1 |= SDRAM_MCOPT1_WOOO_DISABLED;
989 mcopt1 |= SDRAM_MCOPT1_DCOO_DISABLED;
990 mcopt1 |= SDRAM_MCOPT1_DREF_NORMAL;
992 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
993 if (dimm_populated[dimm_num] != SDRAM_NONE) {
994 /* test ecc support */
995 ecc = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 11);
996 if (ecc != 0x02) /* ecc not supported */
999 /* test bank count */
1000 bankcount = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 17);
1001 if (bankcount == 0x04) /* bank count = 4 */
1002 mcopt1 |= SDRAM_MCOPT1_4_BANKS;
1003 else /* bank count = 8 */
1004 mcopt1 |= SDRAM_MCOPT1_8_BANKS;
1007 ddrtype = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 2);
1008 /* test for buffered/unbuffered, registered, differential clocks */
1009 registered = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 20);
1010 attribute = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 21);
1012 /* TODO: code to be changed for IOP1.6 to support 4 DIMMs */
1013 if (dimm_num == 0) {
1014 if (dimm_populated[dimm_num] == SDRAM_DDR1) /* DDR1 type */
1015 mcopt1 |= SDRAM_MCOPT1_DDR1_TYPE;
1016 if (dimm_populated[dimm_num] == SDRAM_DDR2) /* DDR2 type */
1017 mcopt1 |= SDRAM_MCOPT1_DDR2_TYPE;
1018 if (registered == 1) { /* DDR2 always buffered */
1019 /* TODO: what about above comments ? */
1020 mcopt1 |= SDRAM_MCOPT1_RDEN;
1023 /* TODO: the mask 0x02 doesn't match Samsung def for byte 21. */
1024 if ((attribute & 0x02) == 0x00) {
1025 /* buffered not supported */
1028 mcopt1 |= SDRAM_MCOPT1_RDEN;
1033 else if (dimm_num == 1) {
1034 if (dimm_populated[dimm_num] == SDRAM_DDR1) /* DDR1 type */
1035 mcopt1 |= SDRAM_MCOPT1_DDR1_TYPE;
1036 if (dimm_populated[dimm_num] == SDRAM_DDR2) /* DDR2 type */
1037 mcopt1 |= SDRAM_MCOPT1_DDR2_TYPE;
1038 if (registered == 1) {
1039 /* DDR2 always buffered */
1040 mcopt1 |= SDRAM_MCOPT1_RDEN;
1043 if ((attribute & 0x02) == 0x00) {
1044 /* buffered not supported */
1047 mcopt1 |= SDRAM_MCOPT1_RDEN;
1053 /* Note that for DDR2 the byte 7 is reserved, but OK to keep code as is. */
1054 data_width = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 6) +
1055 (((unsigned long)spd_read(iic0_dimm_addr[dimm_num], 7)) << 8);
1057 switch (data_width) {
1067 printf("WARNING: Detected a DIMM with a data width of %lu bits.\n",
1069 printf("Only DIMMs with 32 or 64 bit DDR-SDRAM widths are supported.\n");
1075 /* verify matching properties */
1076 if ((dimm_populated[0] != SDRAM_NONE) && (dimm_populated[1] != SDRAM_NONE)) {
1078 printf("ERROR: DIMM's buffered/unbuffered, registered, clocking don't match.\n");
1079 spd_ddr_init_hang ();
1083 if ((dimm_64bit == TRUE) && (dimm_32bit == TRUE)) {
1084 printf("ERROR: Cannot mix 32 bit and 64 bit DDR-SDRAM DIMMs together.\n");
1085 spd_ddr_init_hang ();
1087 else if ((dimm_64bit == TRUE) && (dimm_32bit == FALSE)) {
1088 mcopt1 |= SDRAM_MCOPT1_DMWD_64;
1089 } else if ((dimm_64bit == FALSE) && (dimm_32bit == TRUE)) {
1090 mcopt1 |= SDRAM_MCOPT1_DMWD_32;
1092 printf("ERROR: Please install only 32 or 64 bit DDR-SDRAM DIMMs.\n\n");
1093 spd_ddr_init_hang ();
1096 if (ecc_enabled == TRUE)
1097 mcopt1 |= SDRAM_MCOPT1_MCHK_GEN;
1099 mcopt1 |= SDRAM_MCOPT1_MCHK_NON;
1101 mtsdram(SDRAM_MCOPT1, mcopt1);
1104 /*-----------------------------------------------------------------------------+
1106 *-----------------------------------------------------------------------------*/
1107 static void program_codt(unsigned long *dimm_populated,
1108 unsigned char *iic0_dimm_addr,
1109 unsigned long num_dimm_banks)
1112 unsigned long modt0 = 0;
1113 unsigned long modt1 = 0;
1114 unsigned long modt2 = 0;
1115 unsigned long modt3 = 0;
1116 unsigned char dimm_num;
1117 unsigned char dimm_rank;
1118 unsigned char total_rank = 0;
1119 unsigned char total_dimm = 0;
1120 unsigned char dimm_type = 0;
1121 unsigned char firstSlot = 0;
1123 /*------------------------------------------------------------------
1124 * Set the SDRAM Controller On Die Termination Register
1125 *-----------------------------------------------------------------*/
1126 mfsdram(SDRAM_CODT, codt);
1127 codt |= (SDRAM_CODT_IO_NMODE
1128 & (~SDRAM_CODT_DQS_SINGLE_END
1129 & ~SDRAM_CODT_CKSE_SINGLE_END
1130 & ~SDRAM_CODT_FEEBBACK_RCV_SINGLE_END
1131 & ~SDRAM_CODT_FEEBBACK_DRV_SINGLE_END));
1133 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1134 if (dimm_populated[dimm_num] != SDRAM_NONE) {
1135 dimm_rank = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 5);
1136 if (((unsigned long)spd_read(iic0_dimm_addr[dimm_num], 2)) == 0x08) {
1137 dimm_rank = (dimm_rank & 0x0F) + 1;
1138 dimm_type = SDRAM_DDR2;
1140 dimm_rank = dimm_rank & 0x0F;
1141 dimm_type = SDRAM_DDR1;
1144 total_rank += dimm_rank;
1146 if ((dimm_num == 0) && (total_dimm == 1))
1152 if (dimm_type == SDRAM_DDR2) {
1153 codt |= SDRAM_CODT_DQS_1_8_V_DDR2;
1154 if ((total_dimm == 1) && (firstSlot == TRUE)) {
1155 if (total_rank == 1) {
1156 codt |= CALC_ODT_R(0);
1157 modt0 = CALC_ODT_W(0);
1162 if (total_rank == 2) {
1163 codt |= CALC_ODT_R(0) | CALC_ODT_R(1);
1164 modt0 = CALC_ODT_W(0);
1165 modt1 = CALC_ODT_W(0);
1169 } else if ((total_dimm == 1) && (firstSlot != TRUE)) {
1170 if (total_rank == 1) {
1171 codt |= CALC_ODT_R(2);
1174 modt2 = CALC_ODT_W(2);
1177 if (total_rank == 2) {
1178 codt |= CALC_ODT_R(2) | CALC_ODT_R(3);
1181 modt2 = CALC_ODT_W(2);
1182 modt3 = CALC_ODT_W(2);
1185 if (total_dimm == 2) {
1186 if (total_rank == 2) {
1187 codt |= CALC_ODT_R(0) | CALC_ODT_R(2);
1188 modt0 = CALC_ODT_RW(2);
1190 modt2 = CALC_ODT_RW(0);
1193 if (total_rank == 4) {
1194 codt |= CALC_ODT_R(0) | CALC_ODT_R(1) |
1195 CALC_ODT_R(2) | CALC_ODT_R(3);
1196 modt0 = CALC_ODT_RW(2);
1198 modt2 = CALC_ODT_RW(0);
1203 codt |= SDRAM_CODT_DQS_2_5_V_DDR1;
1209 if (total_dimm == 1) {
1210 if (total_rank == 1)
1212 if (total_rank == 2)
1215 if (total_dimm == 2) {
1216 if (total_rank == 2)
1218 if (total_rank == 4)
1223 debug("nb of dimm %d\n", total_dimm);
1224 debug("nb of rank %d\n", total_rank);
1225 if (total_dimm == 1)
1226 debug("dimm in slot %d\n", firstSlot);
1228 mtsdram(SDRAM_CODT, codt);
1229 mtsdram(SDRAM_MODT0, modt0);
1230 mtsdram(SDRAM_MODT1, modt1);
1231 mtsdram(SDRAM_MODT2, modt2);
1232 mtsdram(SDRAM_MODT3, modt3);
1235 /*-----------------------------------------------------------------------------+
1237 *-----------------------------------------------------------------------------*/
1238 static void program_initplr(unsigned long *dimm_populated,
1239 unsigned char *iic0_dimm_addr,
1240 unsigned long num_dimm_banks,
1241 ddr_cas_id_t selected_cas,
1255 /******************************************************
1256 ** Assumption: if more than one DIMM, all DIMMs are the same
1257 ** as already checked in check_memory_type
1258 ******************************************************/
1260 if ((dimm_populated[0] == SDRAM_DDR1) || (dimm_populated[1] == SDRAM_DDR1)) {
1261 mtsdram(SDRAM_INITPLR0, 0x81B80000);
1262 mtsdram(SDRAM_INITPLR1, 0x81900400);
1263 mtsdram(SDRAM_INITPLR2, 0x81810000);
1264 mtsdram(SDRAM_INITPLR3, 0xff800162);
1265 mtsdram(SDRAM_INITPLR4, 0x81900400);
1266 mtsdram(SDRAM_INITPLR5, 0x86080000);
1267 mtsdram(SDRAM_INITPLR6, 0x86080000);
1268 mtsdram(SDRAM_INITPLR7, 0x81000062);
1269 } else if ((dimm_populated[0] == SDRAM_DDR2) || (dimm_populated[1] == SDRAM_DDR2)) {
1270 switch (selected_cas) {
1281 printf("ERROR: ucode error on selected_cas value %d", selected_cas);
1282 spd_ddr_init_hang ();
1288 * ToDo - Still a problem with the write recovery:
1289 * On the Corsair CM2X512-5400C4 module, setting write recovery
1290 * in the INITPLR reg to the value calculated in program_mode()
1291 * results in not correctly working DDR2 memory (crash after
1294 * So for now, set the write recovery to 3. This seems to work
1295 * on the Corair module too.
1299 switch (write_recovery) {
1313 printf("ERROR: write recovery not support (%d)", write_recovery);
1314 spd_ddr_init_hang ();
1318 wr = WRITE_RECOV_3; /* test-only, see description above */
1321 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++)
1322 if (dimm_populated[dimm_num] != SDRAM_NONE)
1324 if (total_dimm == 1) {
1327 } else if (total_dimm == 2) {
1331 printf("ERROR: Unsupported number of DIMM's (%d)", total_dimm);
1332 spd_ddr_init_hang ();
1335 mr = CMD_EMR | SELECT_MR | BURST_LEN_4 | wr | cas;
1336 emr = CMD_EMR | SELECT_EMR | odt | ods;
1337 emr2 = CMD_EMR | SELECT_EMR2;
1338 emr3 = CMD_EMR | SELECT_EMR3;
1339 mtsdram(SDRAM_INITPLR0, 0xB5000000 | CMD_NOP); /* NOP */
1341 mtsdram(SDRAM_INITPLR1, 0x82000400 | CMD_PRECHARGE); /* precharge 8 DDR clock cycle */
1342 mtsdram(SDRAM_INITPLR2, 0x80800000 | emr2); /* EMR2 */
1343 mtsdram(SDRAM_INITPLR3, 0x80800000 | emr3); /* EMR3 */
1344 mtsdram(SDRAM_INITPLR4, 0x80800000 | emr); /* EMR DLL ENABLE */
1345 mtsdram(SDRAM_INITPLR5, 0x80800000 | mr | DLL_RESET); /* MR w/ DLL reset */
1347 mtsdram(SDRAM_INITPLR6, 0x82000400 | CMD_PRECHARGE); /* precharge 8 DDR clock cycle */
1348 mtsdram(SDRAM_INITPLR7, 0x8a000000 | CMD_REFRESH); /* Refresh 50 DDR clock cycle */
1349 mtsdram(SDRAM_INITPLR8, 0x8a000000 | CMD_REFRESH); /* Refresh 50 DDR clock cycle */
1350 mtsdram(SDRAM_INITPLR9, 0x8a000000 | CMD_REFRESH); /* Refresh 50 DDR clock cycle */
1351 mtsdram(SDRAM_INITPLR10, 0x8a000000 | CMD_REFRESH); /* Refresh 50 DDR clock cycle */
1352 mtsdram(SDRAM_INITPLR11, 0x80000000 | mr); /* MR w/o DLL reset */
1353 mtsdram(SDRAM_INITPLR12, 0x80800380 | emr); /* EMR OCD Default */
1354 mtsdram(SDRAM_INITPLR13, 0x80800000 | emr); /* EMR OCD Exit */
1356 printf("ERROR: ucode error as unknown DDR type in program_initplr");
1357 spd_ddr_init_hang ();
1361 /*------------------------------------------------------------------
1362 * This routine programs the SDRAM_MMODE register.
1363 * the selected_cas is an output parameter, that will be passed
1364 * by caller to call the above program_initplr( )
1365 *-----------------------------------------------------------------*/
1366 static void program_mode(unsigned long *dimm_populated,
1367 unsigned char *iic0_dimm_addr,
1368 unsigned long num_dimm_banks,
1369 ddr_cas_id_t *selected_cas,
1370 int *write_recovery)
1372 unsigned long dimm_num;
1373 unsigned long sdram_ddr1;
1374 unsigned long t_wr_ns;
1375 unsigned long t_wr_clk;
1376 unsigned long cas_bit;
1377 unsigned long cas_index;
1378 unsigned long sdram_freq;
1379 unsigned long ddr_check;
1380 unsigned long mmode;
1381 unsigned long tcyc_reg;
1382 unsigned long cycle_2_0_clk;
1383 unsigned long cycle_2_5_clk;
1384 unsigned long cycle_3_0_clk;
1385 unsigned long cycle_4_0_clk;
1386 unsigned long cycle_5_0_clk;
1387 unsigned long max_2_0_tcyc_ns_x_100;
1388 unsigned long max_2_5_tcyc_ns_x_100;
1389 unsigned long max_3_0_tcyc_ns_x_100;
1390 unsigned long max_4_0_tcyc_ns_x_100;
1391 unsigned long max_5_0_tcyc_ns_x_100;
1392 unsigned long cycle_time_ns_x_100[3];
1393 PPC4xx_SYS_INFO board_cfg;
1394 unsigned char cas_2_0_available;
1395 unsigned char cas_2_5_available;
1396 unsigned char cas_3_0_available;
1397 unsigned char cas_4_0_available;
1398 unsigned char cas_5_0_available;
1399 unsigned long sdr_ddrpll;
1401 /*------------------------------------------------------------------
1402 * Get the board configuration info.
1403 *-----------------------------------------------------------------*/
1404 get_sys_info(&board_cfg);
1406 mfsdr(SDR0_DDR0, sdr_ddrpll);
1407 sdram_freq = MULDIV64((board_cfg.freqPLB), SDR0_DDR0_DDRM_DECODE(sdr_ddrpll), 1);
1408 debug("sdram_freq=%d\n", sdram_freq);
1410 /*------------------------------------------------------------------
1411 * Handle the timing. We need to find the worst case timing of all
1412 * the dimm modules installed.
1413 *-----------------------------------------------------------------*/
1415 cas_2_0_available = TRUE;
1416 cas_2_5_available = TRUE;
1417 cas_3_0_available = TRUE;
1418 cas_4_0_available = TRUE;
1419 cas_5_0_available = TRUE;
1420 max_2_0_tcyc_ns_x_100 = 10;
1421 max_2_5_tcyc_ns_x_100 = 10;
1422 max_3_0_tcyc_ns_x_100 = 10;
1423 max_4_0_tcyc_ns_x_100 = 10;
1424 max_5_0_tcyc_ns_x_100 = 10;
1427 /* loop through all the DIMM slots on the board */
1428 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1429 /* If a dimm is installed in a particular slot ... */
1430 if (dimm_populated[dimm_num] != SDRAM_NONE) {
1431 if (dimm_populated[dimm_num] == SDRAM_DDR1)
1436 /* t_wr_ns = max(t_wr_ns, (unsigned long)dimm_spd[dimm_num][36] >> 2); */ /* not used in this loop. */
1437 cas_bit = spd_read(iic0_dimm_addr[dimm_num], 18);
1438 debug("cas_bit[SPD byte 18]=%02x\n", cas_bit);
1440 /* For a particular DIMM, grab the three CAS values it supports */
1441 for (cas_index = 0; cas_index < 3; cas_index++) {
1442 switch (cas_index) {
1444 tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 9);
1447 tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 23);
1450 tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 25);
1454 if ((tcyc_reg & 0x0F) >= 10) {
1455 if ((tcyc_reg & 0x0F) == 0x0D) {
1456 /* Convert from hex to decimal */
1457 cycle_time_ns_x_100[cas_index] =
1458 (((tcyc_reg & 0xF0) >> 4) * 100) + 75;
1460 printf("ERROR: SPD reported Tcyc is incorrect for DIMM "
1461 "in slot %d\n", (unsigned int)dimm_num);
1462 spd_ddr_init_hang ();
1465 /* Convert from hex to decimal */
1466 cycle_time_ns_x_100[cas_index] =
1467 (((tcyc_reg & 0xF0) >> 4) * 100) +
1468 ((tcyc_reg & 0x0F)*10);
1470 debug("cas_index=%d: cycle_time_ns_x_100=%d\n", cas_index,
1471 cycle_time_ns_x_100[cas_index]);
1474 /* The rest of this routine determines if CAS 2.0, 2.5, 3.0, 4.0 and 5.0 are */
1475 /* supported for a particular DIMM. */
1480 * DDR devices use the following bitmask for CAS latency:
1481 * Bit 7 6 5 4 3 2 1 0
1482 * TBD 4.0 3.5 3.0 2.5 2.0 1.5 1.0
1484 if (((cas_bit & 0x40) == 0x40) && (cas_index < 3) &&
1485 (cycle_time_ns_x_100[cas_index] != 0)) {
1486 max_4_0_tcyc_ns_x_100 = max(max_4_0_tcyc_ns_x_100,
1487 cycle_time_ns_x_100[cas_index]);
1492 cas_4_0_available = FALSE;
1495 if (((cas_bit & 0x10) == 0x10) && (cas_index < 3) &&
1496 (cycle_time_ns_x_100[cas_index] != 0)) {
1497 max_3_0_tcyc_ns_x_100 = max(max_3_0_tcyc_ns_x_100,
1498 cycle_time_ns_x_100[cas_index]);
1503 cas_3_0_available = FALSE;
1506 if (((cas_bit & 0x08) == 0x08) && (cas_index < 3) &&
1507 (cycle_time_ns_x_100[cas_index] != 0)) {
1508 max_2_5_tcyc_ns_x_100 = max(max_2_5_tcyc_ns_x_100,
1509 cycle_time_ns_x_100[cas_index]);
1514 cas_2_5_available = FALSE;
1517 if (((cas_bit & 0x04) == 0x04) && (cas_index < 3) &&
1518 (cycle_time_ns_x_100[cas_index] != 0)) {
1519 max_2_0_tcyc_ns_x_100 = max(max_2_0_tcyc_ns_x_100,
1520 cycle_time_ns_x_100[cas_index]);
1525 cas_2_0_available = FALSE;
1529 * DDR2 devices use the following bitmask for CAS latency:
1530 * Bit 7 6 5 4 3 2 1 0
1531 * TBD 6.0 5.0 4.0 3.0 2.0 TBD TBD
1533 if (((cas_bit & 0x20) == 0x20) && (cas_index < 3) &&
1534 (cycle_time_ns_x_100[cas_index] != 0)) {
1535 max_5_0_tcyc_ns_x_100 = max(max_5_0_tcyc_ns_x_100,
1536 cycle_time_ns_x_100[cas_index]);
1541 cas_5_0_available = FALSE;
1544 if (((cas_bit & 0x10) == 0x10) && (cas_index < 3) &&
1545 (cycle_time_ns_x_100[cas_index] != 0)) {
1546 max_4_0_tcyc_ns_x_100 = max(max_4_0_tcyc_ns_x_100,
1547 cycle_time_ns_x_100[cas_index]);
1552 cas_4_0_available = FALSE;
1555 if (((cas_bit & 0x08) == 0x08) && (cas_index < 3) &&
1556 (cycle_time_ns_x_100[cas_index] != 0)) {
1557 max_3_0_tcyc_ns_x_100 = max(max_3_0_tcyc_ns_x_100,
1558 cycle_time_ns_x_100[cas_index]);
1563 cas_3_0_available = FALSE;
1569 /*------------------------------------------------------------------
1570 * Set the SDRAM mode, SDRAM_MMODE
1571 *-----------------------------------------------------------------*/
1572 mfsdram(SDRAM_MMODE, mmode);
1573 mmode = mmode & ~(SDRAM_MMODE_WR_MASK | SDRAM_MMODE_DCL_MASK);
1575 /* add 10 here because of rounding problems */
1576 cycle_2_0_clk = MULDIV64(ONE_BILLION, 100, max_2_0_tcyc_ns_x_100) + 10;
1577 cycle_2_5_clk = MULDIV64(ONE_BILLION, 100, max_2_5_tcyc_ns_x_100) + 10;
1578 cycle_3_0_clk = MULDIV64(ONE_BILLION, 100, max_3_0_tcyc_ns_x_100) + 10;
1579 cycle_4_0_clk = MULDIV64(ONE_BILLION, 100, max_4_0_tcyc_ns_x_100) + 10;
1580 cycle_5_0_clk = MULDIV64(ONE_BILLION, 100, max_5_0_tcyc_ns_x_100) + 10;
1581 debug("cycle_3_0_clk=%d\n", cycle_3_0_clk);
1582 debug("cycle_4_0_clk=%d\n", cycle_4_0_clk);
1583 debug("cycle_5_0_clk=%d\n", cycle_5_0_clk);
1585 if (sdram_ddr1 == TRUE) { /* DDR1 */
1586 if ((cas_2_0_available == TRUE) && (sdram_freq <= cycle_2_0_clk)) {
1587 mmode |= SDRAM_MMODE_DCL_DDR1_2_0_CLK;
1588 *selected_cas = DDR_CAS_2;
1589 } else if ((cas_2_5_available == TRUE) && (sdram_freq <= cycle_2_5_clk)) {
1590 mmode |= SDRAM_MMODE_DCL_DDR1_2_5_CLK;
1591 *selected_cas = DDR_CAS_2_5;
1592 } else if ((cas_3_0_available == TRUE) && (sdram_freq <= cycle_3_0_clk)) {
1593 mmode |= SDRAM_MMODE_DCL_DDR1_3_0_CLK;
1594 *selected_cas = DDR_CAS_3;
1596 printf("ERROR: Cannot find a supported CAS latency with the installed DIMMs.\n");
1597 printf("Only DIMMs DDR1 with CAS latencies of 2.0, 2.5, and 3.0 are supported.\n");
1598 printf("Make sure the PLB speed is within the supported range of the DIMMs.\n\n");
1599 spd_ddr_init_hang ();
1602 debug("cas_3_0_available=%d\n", cas_3_0_available);
1603 debug("cas_4_0_available=%d\n", cas_4_0_available);
1604 debug("cas_5_0_available=%d\n", cas_5_0_available);
1605 if ((cas_3_0_available == TRUE) && (sdram_freq <= cycle_3_0_clk)) {
1606 mmode |= SDRAM_MMODE_DCL_DDR2_3_0_CLK;
1607 *selected_cas = DDR_CAS_3;
1608 } else if ((cas_4_0_available == TRUE) && (sdram_freq <= cycle_4_0_clk)) {
1609 mmode |= SDRAM_MMODE_DCL_DDR2_4_0_CLK;
1610 *selected_cas = DDR_CAS_4;
1611 } else if ((cas_5_0_available == TRUE) && (sdram_freq <= cycle_5_0_clk)) {
1612 mmode |= SDRAM_MMODE_DCL_DDR2_5_0_CLK;
1613 *selected_cas = DDR_CAS_5;
1615 printf("ERROR: Cannot find a supported CAS latency with the installed DIMMs.\n");
1616 printf("Only DIMMs DDR2 with CAS latencies of 3.0, 4.0, and 5.0 are supported.\n");
1617 printf("Make sure the PLB speed is within the supported range of the DIMMs.\n");
1618 printf("cas3=%d cas4=%d cas5=%d\n",
1619 cas_3_0_available, cas_4_0_available, cas_5_0_available);
1620 printf("sdram_freq=%lu cycle3=%lu cycle4=%lu cycle5=%lu\n\n",
1621 sdram_freq, cycle_3_0_clk, cycle_4_0_clk, cycle_5_0_clk);
1622 spd_ddr_init_hang ();
1626 if (sdram_ddr1 == TRUE)
1627 mmode |= SDRAM_MMODE_WR_DDR1;
1630 /* loop through all the DIMM slots on the board */
1631 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1632 /* If a dimm is installed in a particular slot ... */
1633 if (dimm_populated[dimm_num] != SDRAM_NONE)
1634 t_wr_ns = max(t_wr_ns,
1635 spd_read(iic0_dimm_addr[dimm_num], 36) >> 2);
1639 * convert from nanoseconds to ddr clocks
1640 * round up if necessary
1642 t_wr_clk = MULDIV64(sdram_freq, t_wr_ns, ONE_BILLION);
1643 ddr_check = MULDIV64(ONE_BILLION, t_wr_clk, t_wr_ns);
1644 if (sdram_freq != ddr_check)
1652 mmode |= SDRAM_MMODE_WR_DDR2_3_CYC;
1655 mmode |= SDRAM_MMODE_WR_DDR2_4_CYC;
1658 mmode |= SDRAM_MMODE_WR_DDR2_5_CYC;
1661 mmode |= SDRAM_MMODE_WR_DDR2_6_CYC;
1664 *write_recovery = t_wr_clk;
1667 debug("CAS latency = %d\n", *selected_cas);
1668 debug("Write recovery = %d\n", *write_recovery);
1670 mtsdram(SDRAM_MMODE, mmode);
1673 /*-----------------------------------------------------------------------------+
1675 *-----------------------------------------------------------------------------*/
1676 static void program_rtr(unsigned long *dimm_populated,
1677 unsigned char *iic0_dimm_addr,
1678 unsigned long num_dimm_banks)
1680 PPC4xx_SYS_INFO board_cfg;
1681 unsigned long max_refresh_rate;
1682 unsigned long dimm_num;
1683 unsigned long refresh_rate_type;
1684 unsigned long refresh_rate;
1686 unsigned long sdram_freq;
1687 unsigned long sdr_ddrpll;
1690 /*------------------------------------------------------------------
1691 * Get the board configuration info.
1692 *-----------------------------------------------------------------*/
1693 get_sys_info(&board_cfg);
1695 /*------------------------------------------------------------------
1696 * Set the SDRAM Refresh Timing Register, SDRAM_RTR
1697 *-----------------------------------------------------------------*/
1698 mfsdr(SDR0_DDR0, sdr_ddrpll);
1699 sdram_freq = ((board_cfg.freqPLB) * SDR0_DDR0_DDRM_DECODE(sdr_ddrpll));
1701 max_refresh_rate = 0;
1702 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1703 if (dimm_populated[dimm_num] != SDRAM_NONE) {
1705 refresh_rate_type = spd_read(iic0_dimm_addr[dimm_num], 12);
1706 refresh_rate_type &= 0x7F;
1707 switch (refresh_rate_type) {
1709 refresh_rate = 15625;
1712 refresh_rate = 3906;
1715 refresh_rate = 7812;
1718 refresh_rate = 31250;
1721 refresh_rate = 62500;
1724 refresh_rate = 125000;
1728 printf("ERROR: DIMM %d unsupported refresh rate/type.\n",
1729 (unsigned int)dimm_num);
1730 printf("Replace the DIMM module with a supported DIMM.\n\n");
1731 spd_ddr_init_hang ();
1735 max_refresh_rate = max(max_refresh_rate, refresh_rate);
1739 rint = MULDIV64(sdram_freq, max_refresh_rate, ONE_BILLION);
1740 mfsdram(SDRAM_RTR, val);
1741 mtsdram(SDRAM_RTR, (val & ~SDRAM_RTR_RINT_MASK) |
1742 (SDRAM_RTR_RINT_ENCODE(rint)));
1745 /*------------------------------------------------------------------
1746 * This routine programs the SDRAM_TRx registers.
1747 *-----------------------------------------------------------------*/
1748 static void program_tr(unsigned long *dimm_populated,
1749 unsigned char *iic0_dimm_addr,
1750 unsigned long num_dimm_banks)
1752 unsigned long dimm_num;
1753 unsigned long sdram_ddr1;
1754 unsigned long t_rp_ns;
1755 unsigned long t_rcd_ns;
1756 unsigned long t_rrd_ns;
1757 unsigned long t_ras_ns;
1758 unsigned long t_rc_ns;
1759 unsigned long t_rfc_ns;
1760 unsigned long t_wpc_ns;
1761 unsigned long t_wtr_ns;
1762 unsigned long t_rpc_ns;
1763 unsigned long t_rp_clk;
1764 unsigned long t_rcd_clk;
1765 unsigned long t_rrd_clk;
1766 unsigned long t_ras_clk;
1767 unsigned long t_rc_clk;
1768 unsigned long t_rfc_clk;
1769 unsigned long t_wpc_clk;
1770 unsigned long t_wtr_clk;
1771 unsigned long t_rpc_clk;
1772 unsigned long sdtr1, sdtr2, sdtr3;
1773 unsigned long ddr_check;
1774 unsigned long sdram_freq;
1775 unsigned long sdr_ddrpll;
1777 PPC4xx_SYS_INFO board_cfg;
1779 /*------------------------------------------------------------------
1780 * Get the board configuration info.
1781 *-----------------------------------------------------------------*/
1782 get_sys_info(&board_cfg);
1784 mfsdr(SDR0_DDR0, sdr_ddrpll);
1785 sdram_freq = ((board_cfg.freqPLB) * SDR0_DDR0_DDRM_DECODE(sdr_ddrpll));
1787 /*------------------------------------------------------------------
1788 * Handle the timing. We need to find the worst case timing of all
1789 * the dimm modules installed.
1790 *-----------------------------------------------------------------*/
1802 /* loop through all the DIMM slots on the board */
1803 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1804 /* If a dimm is installed in a particular slot ... */
1805 if (dimm_populated[dimm_num] != SDRAM_NONE) {
1806 if (dimm_populated[dimm_num] == SDRAM_DDR2)
1811 t_rcd_ns = max(t_rcd_ns, spd_read(iic0_dimm_addr[dimm_num], 29) >> 2);
1812 t_rrd_ns = max(t_rrd_ns, spd_read(iic0_dimm_addr[dimm_num], 28) >> 2);
1813 t_rp_ns = max(t_rp_ns, spd_read(iic0_dimm_addr[dimm_num], 27) >> 2);
1814 t_ras_ns = max(t_ras_ns, spd_read(iic0_dimm_addr[dimm_num], 30));
1815 t_rc_ns = max(t_rc_ns, spd_read(iic0_dimm_addr[dimm_num], 41));
1816 t_rfc_ns = max(t_rfc_ns, spd_read(iic0_dimm_addr[dimm_num], 42));
1820 /*------------------------------------------------------------------
1821 * Set the SDRAM Timing Reg 1, SDRAM_TR1
1822 *-----------------------------------------------------------------*/
1823 mfsdram(SDRAM_SDTR1, sdtr1);
1824 sdtr1 &= ~(SDRAM_SDTR1_LDOF_MASK | SDRAM_SDTR1_RTW_MASK |
1825 SDRAM_SDTR1_WTWO_MASK | SDRAM_SDTR1_RTRO_MASK);
1827 /* default values */
1828 sdtr1 |= SDRAM_SDTR1_LDOF_2_CLK;
1829 sdtr1 |= SDRAM_SDTR1_RTW_2_CLK;
1831 /* normal operations */
1832 sdtr1 |= SDRAM_SDTR1_WTWO_0_CLK;
1833 sdtr1 |= SDRAM_SDTR1_RTRO_1_CLK;
1835 mtsdram(SDRAM_SDTR1, sdtr1);
1837 /*------------------------------------------------------------------
1838 * Set the SDRAM Timing Reg 2, SDRAM_TR2
1839 *-----------------------------------------------------------------*/
1840 mfsdram(SDRAM_SDTR2, sdtr2);
1841 sdtr2 &= ~(SDRAM_SDTR2_RCD_MASK | SDRAM_SDTR2_WTR_MASK |
1842 SDRAM_SDTR2_XSNR_MASK | SDRAM_SDTR2_WPC_MASK |
1843 SDRAM_SDTR2_RPC_MASK | SDRAM_SDTR2_RP_MASK |
1844 SDRAM_SDTR2_RRD_MASK);
1847 * convert t_rcd from nanoseconds to ddr clocks
1848 * round up if necessary
1850 t_rcd_clk = MULDIV64(sdram_freq, t_rcd_ns, ONE_BILLION);
1851 ddr_check = MULDIV64(ONE_BILLION, t_rcd_clk, t_rcd_ns);
1852 if (sdram_freq != ddr_check)
1855 switch (t_rcd_clk) {
1858 sdtr2 |= SDRAM_SDTR2_RCD_1_CLK;
1861 sdtr2 |= SDRAM_SDTR2_RCD_2_CLK;
1864 sdtr2 |= SDRAM_SDTR2_RCD_3_CLK;
1867 sdtr2 |= SDRAM_SDTR2_RCD_4_CLK;
1870 sdtr2 |= SDRAM_SDTR2_RCD_5_CLK;
1874 if (sdram_ddr1 == TRUE) { /* DDR1 */
1875 if (sdram_freq < 200000000) {
1876 sdtr2 |= SDRAM_SDTR2_WTR_1_CLK;
1877 sdtr2 |= SDRAM_SDTR2_WPC_2_CLK;
1878 sdtr2 |= SDRAM_SDTR2_RPC_2_CLK;
1880 sdtr2 |= SDRAM_SDTR2_WTR_2_CLK;
1881 sdtr2 |= SDRAM_SDTR2_WPC_3_CLK;
1882 sdtr2 |= SDRAM_SDTR2_RPC_2_CLK;
1885 /* loop through all the DIMM slots on the board */
1886 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1887 /* If a dimm is installed in a particular slot ... */
1888 if (dimm_populated[dimm_num] != SDRAM_NONE) {
1889 t_wpc_ns = max(t_wtr_ns, spd_read(iic0_dimm_addr[dimm_num], 36) >> 2);
1890 t_wtr_ns = max(t_wtr_ns, spd_read(iic0_dimm_addr[dimm_num], 37) >> 2);
1891 t_rpc_ns = max(t_rpc_ns, spd_read(iic0_dimm_addr[dimm_num], 38) >> 2);
1896 * convert from nanoseconds to ddr clocks
1897 * round up if necessary
1899 t_wpc_clk = MULDIV64(sdram_freq, t_wpc_ns, ONE_BILLION);
1900 ddr_check = MULDIV64(ONE_BILLION, t_wpc_clk, t_wpc_ns);
1901 if (sdram_freq != ddr_check)
1904 switch (t_wpc_clk) {
1908 sdtr2 |= SDRAM_SDTR2_WPC_2_CLK;
1911 sdtr2 |= SDRAM_SDTR2_WPC_3_CLK;
1914 sdtr2 |= SDRAM_SDTR2_WPC_4_CLK;
1917 sdtr2 |= SDRAM_SDTR2_WPC_5_CLK;
1920 sdtr2 |= SDRAM_SDTR2_WPC_6_CLK;
1925 * convert from nanoseconds to ddr clocks
1926 * round up if necessary
1928 t_wtr_clk = MULDIV64(sdram_freq, t_wtr_ns, ONE_BILLION);
1929 ddr_check = MULDIV64(ONE_BILLION, t_wtr_clk, t_wtr_ns);
1930 if (sdram_freq != ddr_check)
1933 switch (t_wtr_clk) {
1936 sdtr2 |= SDRAM_SDTR2_WTR_1_CLK;
1939 sdtr2 |= SDRAM_SDTR2_WTR_2_CLK;
1942 sdtr2 |= SDRAM_SDTR2_WTR_3_CLK;
1945 sdtr2 |= SDRAM_SDTR2_WTR_4_CLK;
1950 * convert from nanoseconds to ddr clocks
1951 * round up if necessary
1953 t_rpc_clk = MULDIV64(sdram_freq, t_rpc_ns, ONE_BILLION);
1954 ddr_check = MULDIV64(ONE_BILLION, t_rpc_clk, t_rpc_ns);
1955 if (sdram_freq != ddr_check)
1958 switch (t_rpc_clk) {
1962 sdtr2 |= SDRAM_SDTR2_RPC_2_CLK;
1965 sdtr2 |= SDRAM_SDTR2_RPC_3_CLK;
1968 sdtr2 |= SDRAM_SDTR2_RPC_4_CLK;
1974 sdtr2 |= SDRAM_SDTR2_XSNR_16_CLK;
1977 * convert t_rrd from nanoseconds to ddr clocks
1978 * round up if necessary
1980 t_rrd_clk = MULDIV64(sdram_freq, t_rrd_ns, ONE_BILLION);
1981 ddr_check = MULDIV64(ONE_BILLION, t_rrd_clk, t_rrd_ns);
1982 if (sdram_freq != ddr_check)
1986 sdtr2 |= SDRAM_SDTR2_RRD_3_CLK;
1988 sdtr2 |= SDRAM_SDTR2_RRD_2_CLK;
1991 * convert t_rp from nanoseconds to ddr clocks
1992 * round up if necessary
1994 t_rp_clk = MULDIV64(sdram_freq, t_rp_ns, ONE_BILLION);
1995 ddr_check = MULDIV64(ONE_BILLION, t_rp_clk, t_rp_ns);
1996 if (sdram_freq != ddr_check)
2004 sdtr2 |= SDRAM_SDTR2_RP_3_CLK;
2007 sdtr2 |= SDRAM_SDTR2_RP_4_CLK;
2010 sdtr2 |= SDRAM_SDTR2_RP_5_CLK;
2013 sdtr2 |= SDRAM_SDTR2_RP_6_CLK;
2016 sdtr2 |= SDRAM_SDTR2_RP_7_CLK;
2020 mtsdram(SDRAM_SDTR2, sdtr2);
2022 /*------------------------------------------------------------------
2023 * Set the SDRAM Timing Reg 3, SDRAM_TR3
2024 *-----------------------------------------------------------------*/
2025 mfsdram(SDRAM_SDTR3, sdtr3);
2026 sdtr3 &= ~(SDRAM_SDTR3_RAS_MASK | SDRAM_SDTR3_RC_MASK |
2027 SDRAM_SDTR3_XCS_MASK | SDRAM_SDTR3_RFC_MASK);
2030 * convert t_ras from nanoseconds to ddr clocks
2031 * round up if necessary
2033 t_ras_clk = MULDIV64(sdram_freq, t_ras_ns, ONE_BILLION);
2034 ddr_check = MULDIV64(ONE_BILLION, t_ras_clk, t_ras_ns);
2035 if (sdram_freq != ddr_check)
2038 sdtr3 |= SDRAM_SDTR3_RAS_ENCODE(t_ras_clk);
2041 * convert t_rc from nanoseconds to ddr clocks
2042 * round up if necessary
2044 t_rc_clk = MULDIV64(sdram_freq, t_rc_ns, ONE_BILLION);
2045 ddr_check = MULDIV64(ONE_BILLION, t_rc_clk, t_rc_ns);
2046 if (sdram_freq != ddr_check)
2049 sdtr3 |= SDRAM_SDTR3_RC_ENCODE(t_rc_clk);
2051 /* default xcs value */
2052 sdtr3 |= SDRAM_SDTR3_XCS;
2055 * convert t_rfc from nanoseconds to ddr clocks
2056 * round up if necessary
2058 t_rfc_clk = MULDIV64(sdram_freq, t_rfc_ns, ONE_BILLION);
2059 ddr_check = MULDIV64(ONE_BILLION, t_rfc_clk, t_rfc_ns);
2060 if (sdram_freq != ddr_check)
2063 sdtr3 |= SDRAM_SDTR3_RFC_ENCODE(t_rfc_clk);
2065 mtsdram(SDRAM_SDTR3, sdtr3);
2068 /*-----------------------------------------------------------------------------+
2070 *-----------------------------------------------------------------------------*/
2071 static void program_bxcf(unsigned long *dimm_populated,
2072 unsigned char *iic0_dimm_addr,
2073 unsigned long num_dimm_banks)
2075 unsigned long dimm_num;
2076 unsigned long num_col_addr;
2077 unsigned long num_ranks;
2078 unsigned long num_banks;
2080 unsigned long ind_rank;
2082 unsigned long ind_bank;
2083 unsigned long bank_0_populated;
2085 /*------------------------------------------------------------------
2086 * Set the BxCF regs. First, wipe out the bank config registers.
2087 *-----------------------------------------------------------------*/
2088 mtsdram(SDRAM_MB0CF, 0x00000000);
2089 mtsdram(SDRAM_MB1CF, 0x00000000);
2090 mtsdram(SDRAM_MB2CF, 0x00000000);
2091 mtsdram(SDRAM_MB3CF, 0x00000000);
2093 mode = SDRAM_BXCF_M_BE_ENABLE;
2095 bank_0_populated = 0;
2097 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
2098 if (dimm_populated[dimm_num] != SDRAM_NONE) {
2099 num_col_addr = spd_read(iic0_dimm_addr[dimm_num], 4);
2100 num_ranks = spd_read(iic0_dimm_addr[dimm_num], 5);
2101 if ((spd_read(iic0_dimm_addr[dimm_num], 2)) == 0x08)
2102 num_ranks = (num_ranks & 0x0F) +1;
2104 num_ranks = num_ranks & 0x0F;
2106 num_banks = spd_read(iic0_dimm_addr[dimm_num], 17);
2108 for (ind_bank = 0; ind_bank < 2; ind_bank++) {
2113 switch (num_col_addr) {
2115 mode |= (SDRAM_BXCF_M_AM_0 + ind);
2118 mode |= (SDRAM_BXCF_M_AM_1 + ind);
2121 mode |= (SDRAM_BXCF_M_AM_2 + ind);
2124 mode |= (SDRAM_BXCF_M_AM_3 + ind);
2127 mode |= (SDRAM_BXCF_M_AM_4 + ind);
2130 printf("DDR-SDRAM: DIMM %d BxCF configuration.\n",
2131 (unsigned int)dimm_num);
2132 printf("ERROR: Unsupported value for number of "
2133 "column addresses: %d.\n", (unsigned int)num_col_addr);
2134 printf("Replace the DIMM module with a supported DIMM.\n\n");
2135 spd_ddr_init_hang ();
2139 if ((dimm_populated[dimm_num] != SDRAM_NONE)&& (dimm_num ==1))
2140 bank_0_populated = 1;
2142 for (ind_rank = 0; ind_rank < num_ranks; ind_rank++) {
2143 mtsdram(SDRAM_MB0CF +
2144 ((dimm_num + bank_0_populated + ind_rank) << 2),
2151 /*------------------------------------------------------------------
2152 * program memory queue.
2153 *-----------------------------------------------------------------*/
2154 static void program_memory_queue(unsigned long *dimm_populated,
2155 unsigned char *iic0_dimm_addr,
2156 unsigned long num_dimm_banks)
2158 unsigned long dimm_num;
2159 phys_size_t rank_base_addr;
2160 unsigned long rank_reg;
2161 phys_size_t rank_size_bytes;
2162 unsigned long rank_size_id;
2163 unsigned long num_ranks;
2164 unsigned long baseadd_size;
2166 unsigned long bank_0_populated = 0;
2167 phys_size_t total_size = 0;
2169 /*------------------------------------------------------------------
2170 * Reset the rank_base_address.
2171 *-----------------------------------------------------------------*/
2172 rank_reg = SDRAM_R0BAS;
2174 rank_base_addr = 0x00000000;
2176 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
2177 if (dimm_populated[dimm_num] != SDRAM_NONE) {
2178 num_ranks = spd_read(iic0_dimm_addr[dimm_num], 5);
2179 if ((spd_read(iic0_dimm_addr[dimm_num], 2)) == 0x08)
2180 num_ranks = (num_ranks & 0x0F) + 1;
2182 num_ranks = num_ranks & 0x0F;
2184 rank_size_id = spd_read(iic0_dimm_addr[dimm_num], 31);
2186 /*------------------------------------------------------------------
2188 *-----------------------------------------------------------------*/
2190 switch (rank_size_id) {
2192 baseadd_size |= SDRAM_RXBAS_SDSZ_1024;
2196 baseadd_size |= SDRAM_RXBAS_SDSZ_2048;
2200 baseadd_size |= SDRAM_RXBAS_SDSZ_4096;
2204 baseadd_size |= SDRAM_RXBAS_SDSZ_32;
2208 baseadd_size |= SDRAM_RXBAS_SDSZ_64;
2212 baseadd_size |= SDRAM_RXBAS_SDSZ_128;
2216 baseadd_size |= SDRAM_RXBAS_SDSZ_256;
2220 baseadd_size |= SDRAM_RXBAS_SDSZ_512;
2224 printf("DDR-SDRAM: DIMM %d memory queue configuration.\n",
2225 (unsigned int)dimm_num);
2226 printf("ERROR: Unsupported value for the banksize: %d.\n",
2227 (unsigned int)rank_size_id);
2228 printf("Replace the DIMM module with a supported DIMM.\n\n");
2229 spd_ddr_init_hang ();
2231 rank_size_bytes = total_size << 20;
2233 if ((dimm_populated[dimm_num] != SDRAM_NONE) && (dimm_num == 1))
2234 bank_0_populated = 1;
2236 for (i = 0; i < num_ranks; i++) {
2237 mtdcr_any(rank_reg+i+dimm_num+bank_0_populated,
2238 (SDRAM_RXBAS_SDBA_ENCODE(rank_base_addr) |
2240 rank_base_addr += rank_size_bytes;
2245 #if defined(CONFIG_460EX) || defined(CONFIG_460GT)
2247 * Enable high bandwidth access on 460EX/GT.
2248 * This should/could probably be done on other
2249 * PPC's too, like 440SPe.
2250 * This is currently not used, but with this setup
2251 * it is possible to use it later on in e.g. the Linux
2252 * EMAC driver for performance gain.
2254 mtdcr(SDRAM_PLBADDULL, 0x00000000); /* MQ0_BAUL */
2255 mtdcr(SDRAM_PLBADDUHB, 0x00000008); /* MQ0_BAUH */
2259 /*-----------------------------------------------------------------------------+
2261 *-----------------------------------------------------------------------------*/
2262 static unsigned long is_ecc_enabled(void)
2264 unsigned long dimm_num;
2269 /* loop through all the DIMM slots on the board */
2270 for (dimm_num = 0; dimm_num < MAXDIMMS; dimm_num++) {
2271 mfsdram(SDRAM_MCOPT1, val);
2272 ecc = max(ecc, SDRAM_MCOPT1_MCHK_CHK_DECODE(val));
2278 static void blank_string(int size)
2282 for (i=0; i<size; i++)
2284 for (i=0; i<size; i++)
2286 for (i=0; i<size; i++)
2290 #ifdef CONFIG_DDR_ECC
2291 /*-----------------------------------------------------------------------------+
2293 *-----------------------------------------------------------------------------*/
2294 static void program_ecc(unsigned long *dimm_populated,
2295 unsigned char *iic0_dimm_addr,
2296 unsigned long num_dimm_banks,
2297 unsigned long tlb_word2_i_value)
2299 unsigned long mcopt1;
2300 unsigned long mcopt2;
2301 unsigned long mcstat;
2302 unsigned long dimm_num;
2306 /* loop through all the DIMM slots on the board */
2307 for (dimm_num = 0; dimm_num < MAXDIMMS; dimm_num++) {
2308 /* If a dimm is installed in a particular slot ... */
2309 if (dimm_populated[dimm_num] != SDRAM_NONE)
2310 ecc = max(ecc, spd_read(iic0_dimm_addr[dimm_num], 11));
2315 if (sdram_memsize() > CONFIG_MAX_MEM_MAPPED) {
2316 printf("\nWarning: Can't enable ECC on systems with more than 2GB of SDRAM!\n");
2320 mfsdram(SDRAM_MCOPT1, mcopt1);
2321 mfsdram(SDRAM_MCOPT2, mcopt2);
2323 if ((mcopt1 & SDRAM_MCOPT1_MCHK_MASK) != SDRAM_MCOPT1_MCHK_NON) {
2324 /* DDR controller must be enabled and not in self-refresh. */
2325 mfsdram(SDRAM_MCSTAT, mcstat);
2326 if (((mcopt2 & SDRAM_MCOPT2_DCEN_MASK) == SDRAM_MCOPT2_DCEN_ENABLE)
2327 && ((mcopt2 & SDRAM_MCOPT2_SREN_MASK) == SDRAM_MCOPT2_SREN_EXIT)
2328 && ((mcstat & (SDRAM_MCSTAT_MIC_MASK | SDRAM_MCSTAT_SRMS_MASK))
2329 == (SDRAM_MCSTAT_MIC_COMP | SDRAM_MCSTAT_SRMS_NOT_SF))) {
2331 program_ecc_addr(0, sdram_memsize(), tlb_word2_i_value);
2338 static void wait_ddr_idle(void)
2343 mfsdram(SDRAM_MCSTAT, val);
2344 } while ((val & SDRAM_MCSTAT_IDLE_MASK) == SDRAM_MCSTAT_IDLE_NOT);
2347 /*-----------------------------------------------------------------------------+
2349 *-----------------------------------------------------------------------------*/
2350 static void program_ecc_addr(unsigned long start_address,
2351 unsigned long num_bytes,
2352 unsigned long tlb_word2_i_value)
2354 unsigned long current_address;
2355 unsigned long end_address;
2356 unsigned long address_increment;
2357 unsigned long mcopt1;
2358 char str[] = "ECC generation -";
2359 char slash[] = "\\|/-\\|/-";
2363 current_address = start_address;
2364 mfsdram(SDRAM_MCOPT1, mcopt1);
2365 if ((mcopt1 & SDRAM_MCOPT1_MCHK_MASK) != SDRAM_MCOPT1_MCHK_NON) {
2366 mtsdram(SDRAM_MCOPT1,
2367 (mcopt1 & ~SDRAM_MCOPT1_MCHK_MASK) | SDRAM_MCOPT1_MCHK_GEN);
2373 if (tlb_word2_i_value == TLB_WORD2_I_ENABLE) {
2374 /* ECC bit set method for non-cached memory */
2375 if ((mcopt1 & SDRAM_MCOPT1_DMWD_MASK) == SDRAM_MCOPT1_DMWD_32)
2376 address_increment = 4;
2378 address_increment = 8;
2379 end_address = current_address + num_bytes;
2381 while (current_address < end_address) {
2382 *((unsigned long *)current_address) = 0x00000000;
2383 current_address += address_increment;
2385 if ((loop++ % (2 << 20)) == 0) {
2387 putc(slash[loopi++ % 8]);
2392 /* ECC bit set method for cached memory */
2393 dcbz_area(start_address, num_bytes);
2394 /* Write modified dcache lines back to memory */
2395 clean_dcache_range(start_address, start_address + num_bytes);
2398 blank_string(strlen(str));
2404 /* clear ECC error repoting registers */
2405 mtsdram(SDRAM_ECCCR, 0xffffffff);
2406 mtdcr(0x4c, 0xffffffff);
2408 mtsdram(SDRAM_MCOPT1,
2409 (mcopt1 & ~SDRAM_MCOPT1_MCHK_MASK) | SDRAM_MCOPT1_MCHK_CHK_REP);
2417 /*-----------------------------------------------------------------------------+
2418 * program_DQS_calibration.
2419 *-----------------------------------------------------------------------------*/
2420 static void program_DQS_calibration(unsigned long *dimm_populated,
2421 unsigned char *iic0_dimm_addr,
2422 unsigned long num_dimm_banks)
2426 #ifdef HARD_CODED_DQS /* calibration test with hardvalues */
2427 mtsdram(SDRAM_RQDC, 0x80000037);
2428 mtsdram(SDRAM_RDCC, 0x40000000);
2429 mtsdram(SDRAM_RFDC, 0x000001DF);
2433 /*------------------------------------------------------------------
2434 * Program RDCC register
2435 * Read sample cycle auto-update enable
2436 *-----------------------------------------------------------------*/
2438 mfsdram(SDRAM_RDCC, val);
2440 (val & ~(SDRAM_RDCC_RDSS_MASK | SDRAM_RDCC_RSAE_MASK))
2441 | SDRAM_RDCC_RSAE_ENABLE);
2443 /*------------------------------------------------------------------
2444 * Program RQDC register
2445 * Internal DQS delay mechanism enable
2446 *-----------------------------------------------------------------*/
2447 mtsdram(SDRAM_RQDC, (SDRAM_RQDC_RQDE_ENABLE|SDRAM_RQDC_RQFD_ENCODE(0x38)));
2449 /*------------------------------------------------------------------
2450 * Program RFDC register
2451 * Set Feedback Fractional Oversample
2452 * Auto-detect read sample cycle enable
2453 *-----------------------------------------------------------------*/
2454 mfsdram(SDRAM_RFDC, val);
2456 (val & ~(SDRAM_RFDC_ARSE_MASK | SDRAM_RFDC_RFOS_MASK |
2457 SDRAM_RFDC_RFFD_MASK))
2458 | (SDRAM_RFDC_ARSE_ENABLE | SDRAM_RFDC_RFOS_ENCODE(0) |
2459 SDRAM_RFDC_RFFD_ENCODE(0)));
2461 DQS_calibration_process();
2465 static int short_mem_test(void)
2472 phys_size_t base_addr;
2473 u32 test[NUMMEMTESTS][NUMMEMWORDS] = {
2474 {0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
2475 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF},
2476 {0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
2477 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000},
2478 {0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
2479 0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555},
2480 {0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
2481 0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA},
2482 {0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
2483 0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A},
2484 {0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
2485 0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5},
2486 {0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
2487 0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA},
2488 {0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
2489 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55} };
2492 for (bxcr_num = 0; bxcr_num < MAXBXCF; bxcr_num++) {
2493 mfsdram(SDRAM_MB0CF + (bxcr_num << 2), bxcf);
2496 if ((bxcf & SDRAM_BXCF_M_BE_MASK) == SDRAM_BXCF_M_BE_ENABLE) {
2497 /* Bank is enabled */
2500 * Only run test on accessable memory (below 2GB)
2502 base_addr = SDRAM_RXBAS_SDBA_DECODE(mfdcr_any(SDRAM_R0BAS+bxcr_num));
2503 if (base_addr >= CONFIG_MAX_MEM_MAPPED)
2506 /*------------------------------------------------------------------
2507 * Run the short memory test.
2508 *-----------------------------------------------------------------*/
2509 membase = (u32 *)(u32)base_addr;
2511 for (i = 0; i < NUMMEMTESTS; i++) {
2512 for (j = 0; j < NUMMEMWORDS; j++) {
2513 membase[j] = test[i][j];
2514 ppcDcbf((u32)&(membase[j]));
2517 for (l=0; l<NUMLOOPS; l++) {
2518 for (j = 0; j < NUMMEMWORDS; j++) {
2519 if (membase[j] != test[i][j]) {
2520 ppcDcbf((u32)&(membase[j]));
2523 ppcDcbf((u32)&(membase[j]));
2528 } /* if bank enabled */
2529 } /* for bxcf_num */
2534 #ifndef HARD_CODED_DQS
2535 /*-----------------------------------------------------------------------------+
2536 * DQS_calibration_process.
2537 *-----------------------------------------------------------------------------*/
2538 static void DQS_calibration_process(void)
2540 unsigned long rfdc_reg;
2546 unsigned long begin_rqfd[MAXRANKS];
2547 unsigned long begin_rffd[MAXRANKS];
2548 unsigned long end_rqfd[MAXRANKS];
2549 unsigned long end_rffd[MAXRANKS];
2551 unsigned long dlycal;
2552 unsigned long dly_val;
2553 unsigned long max_pass_length;
2554 unsigned long current_pass_length;
2555 unsigned long current_fail_length;
2556 unsigned long current_start;
2558 unsigned char fail_found;
2559 unsigned char pass_found;
2560 #if !defined(CONFIG_DDR_RQDC_FIXED)
2566 char str[] = "Auto calibration -";
2567 char slash[] = "\\|/-\\|/-";
2569 /*------------------------------------------------------------------
2570 * Test to determine the best read clock delay tuning bits.
2572 * Before the DDR controller can be used, the read clock delay needs to be
2573 * set. This is SDRAM_RQDC[RQFD] and SDRAM_RFDC[RFFD].
2574 * This value cannot be hardcoded into the program because it changes
2575 * depending on the board's setup and environment.
2576 * To do this, all delay values are tested to see if they
2577 * work or not. By doing this, you get groups of fails with groups of
2578 * passing values. The idea is to find the start and end of a passing
2579 * window and take the center of it to use as the read clock delay.
2581 * A failure has to be seen first so that when we hit a pass, we know
2582 * that it is truely the start of the window. If we get passing values
2583 * to start off with, we don't know if we are at the start of the window.
2585 * The code assumes that a failure will always be found.
2586 * If a failure is not found, there is no easy way to get the middle
2587 * of the passing window. I guess we can pretty much pick any value
2588 * but some values will be better than others. Since the lowest speed
2589 * we can clock the DDR interface at is 200 MHz (2x 100 MHz PLB speed),
2590 * from experimentation it is safe to say you will always have a failure.
2591 *-----------------------------------------------------------------*/
2593 /* first fix RQDC[RQFD] to an average of 80 degre phase shift to find RFDC[RFFD] */
2594 rqfd_start = 64; /* test-only: don't know if this is the _best_ start value */
2599 mfsdram(SDRAM_RQDC, rqdc_reg);
2600 mtsdram(SDRAM_RQDC, (rqdc_reg & ~SDRAM_RQDC_RQFD_MASK) |
2601 SDRAM_RQDC_RQFD_ENCODE(rqfd_start));
2602 #else /* CONFIG_DDR_RQDC_FIXED */
2604 * On Katmai the complete auto-calibration somehow doesn't seem to
2605 * produce the best results, meaning optimal values for RQFD/RFFD.
2606 * This was discovered by GDA using a high bandwidth scope,
2607 * analyzing the DDR2 signals. GDA provided a fixed value for RQFD,
2608 * so now on Katmai "only" RFFD is auto-calibrated.
2610 mtsdram(SDRAM_RQDC, CONFIG_DDR_RQDC_FIXED);
2611 #endif /* CONFIG_DDR_RQDC_FIXED */
2623 window_found = FALSE;
2625 max_pass_length = 0;
2628 current_pass_length = 0;
2629 current_fail_length = 0;
2631 window_found = FALSE;
2636 * get the delay line calibration register value
2638 mfsdram(SDRAM_DLCR, dlycal);
2639 dly_val = SDRAM_DLYCAL_DLCV_DECODE(dlycal) << 2;
2641 for (rffd = 0; rffd <= SDRAM_RFDC_RFFD_MAX; rffd++) {
2642 mfsdram(SDRAM_RFDC, rfdc_reg);
2643 rfdc_reg &= ~(SDRAM_RFDC_RFFD_MASK);
2645 /*------------------------------------------------------------------
2646 * Set the timing reg for the test.
2647 *-----------------------------------------------------------------*/
2648 mtsdram(SDRAM_RFDC, rfdc_reg | SDRAM_RFDC_RFFD_ENCODE(rffd));
2650 /*------------------------------------------------------------------
2651 * See if the rffd value passed.
2652 *-----------------------------------------------------------------*/
2653 if (short_mem_test()) {
2654 if (fail_found == TRUE) {
2656 if (current_pass_length == 0)
2657 current_start = rffd;
2659 current_fail_length = 0;
2660 current_pass_length++;
2662 if (current_pass_length > max_pass_length) {
2663 max_pass_length = current_pass_length;
2664 max_start = current_start;
2669 current_pass_length = 0;
2670 current_fail_length++;
2672 if (current_fail_length >= (dly_val >> 2)) {
2673 if (fail_found == FALSE) {
2675 } else if (pass_found == TRUE) {
2676 window_found = TRUE;
2683 /*------------------------------------------------------------------
2684 * Set the average RFFD value
2685 *-----------------------------------------------------------------*/
2686 rffd_average = ((max_start + max_end) >> 1);
2688 if (rffd_average < 0)
2691 if (rffd_average > SDRAM_RFDC_RFFD_MAX)
2692 rffd_average = SDRAM_RFDC_RFFD_MAX;
2693 /* now fix RFDC[RFFD] found and find RQDC[RQFD] */
2694 mtsdram(SDRAM_RFDC, rfdc_reg | SDRAM_RFDC_RFFD_ENCODE(rffd_average));
2696 #if !defined(CONFIG_DDR_RQDC_FIXED)
2697 max_pass_length = 0;
2700 current_pass_length = 0;
2701 current_fail_length = 0;
2703 window_found = FALSE;
2707 for (rqfd = 0; rqfd <= SDRAM_RQDC_RQFD_MAX; rqfd++) {
2708 mfsdram(SDRAM_RQDC, rqdc_reg);
2709 rqdc_reg &= ~(SDRAM_RQDC_RQFD_MASK);
2711 /*------------------------------------------------------------------
2712 * Set the timing reg for the test.
2713 *-----------------------------------------------------------------*/
2714 mtsdram(SDRAM_RQDC, rqdc_reg | SDRAM_RQDC_RQFD_ENCODE(rqfd));
2716 /*------------------------------------------------------------------
2717 * See if the rffd value passed.
2718 *-----------------------------------------------------------------*/
2719 if (short_mem_test()) {
2720 if (fail_found == TRUE) {
2722 if (current_pass_length == 0)
2723 current_start = rqfd;
2725 current_fail_length = 0;
2726 current_pass_length++;
2728 if (current_pass_length > max_pass_length) {
2729 max_pass_length = current_pass_length;
2730 max_start = current_start;
2735 current_pass_length = 0;
2736 current_fail_length++;
2738 if (fail_found == FALSE) {
2740 } else if (pass_found == TRUE) {
2741 window_found = TRUE;
2747 rqfd_average = ((max_start + max_end) >> 1);
2749 /*------------------------------------------------------------------
2750 * Make sure we found the valid read passing window. Halt if not
2751 *-----------------------------------------------------------------*/
2752 if (window_found == FALSE) {
2753 if (rqfd_start < SDRAM_RQDC_RQFD_MAX) {
2755 putc(slash[loopi++ % 8]);
2757 /* try again from with a different RQFD start value */
2759 goto calibration_loop;
2762 printf("\nERROR: Cannot determine a common read delay for the "
2763 "DIMM(s) installed.\n");
2764 debug("%s[%d] ERROR : \n", __FUNCTION__,__LINE__);
2765 ppc4xx_ibm_ddr2_register_dump();
2766 spd_ddr_init_hang ();
2769 if (rqfd_average < 0)
2772 if (rqfd_average > SDRAM_RQDC_RQFD_MAX)
2773 rqfd_average = SDRAM_RQDC_RQFD_MAX;
2776 (rqdc_reg & ~SDRAM_RQDC_RQFD_MASK) |
2777 SDRAM_RQDC_RQFD_ENCODE(rqfd_average));
2779 blank_string(strlen(str));
2780 #endif /* CONFIG_DDR_RQDC_FIXED */
2783 * Now complete RDSS configuration as mentioned on page 7 of the AMCC
2784 * PowerPC440SP/SPe DDR2 application note:
2785 * "DDR1/DDR2 Initialization Sequence and Dynamic Tuning"
2787 mfsdram(SDRAM_RTSR, val);
2788 if ((val & SDRAM_RTSR_TRK1SM_MASK) == SDRAM_RTSR_TRK1SM_ATPLS1) {
2789 mfsdram(SDRAM_RDCC, val);
2790 if ((val & SDRAM_RDCC_RDSS_MASK) != SDRAM_RDCC_RDSS_T4) {
2792 mtsdram(SDRAM_RDCC, val);
2796 mfsdram(SDRAM_DLCR, val);
2797 debug("%s[%d] DLCR: 0x%08X\n", __FUNCTION__, __LINE__, val);
2798 mfsdram(SDRAM_RQDC, val);
2799 debug("%s[%d] RQDC: 0x%08X\n", __FUNCTION__, __LINE__, val);
2800 mfsdram(SDRAM_RFDC, val);
2801 debug("%s[%d] RFDC: 0x%08X\n", __FUNCTION__, __LINE__, val);
2802 mfsdram(SDRAM_RDCC, val);
2803 debug("%s[%d] RDCC: 0x%08X\n", __FUNCTION__, __LINE__, val);
2805 #else /* calibration test with hardvalues */
2806 /*-----------------------------------------------------------------------------+
2807 * DQS_calibration_process.
2808 *-----------------------------------------------------------------------------*/
2809 static void test(void)
2811 unsigned long dimm_num;
2812 unsigned long ecc_temp;
2814 unsigned long *membase;
2815 unsigned long bxcf[MAXRANKS];
2818 char begin_found[MAXDIMMS];
2819 char end_found[MAXDIMMS];
2820 char search_end[MAXDIMMS];
2821 unsigned long test[NUMMEMTESTS][NUMMEMWORDS] = {
2822 {0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
2823 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF},
2824 {0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
2825 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000},
2826 {0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
2827 0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555},
2828 {0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
2829 0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA},
2830 {0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
2831 0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A},
2832 {0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
2833 0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5},
2834 {0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
2835 0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA},
2836 {0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
2837 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55} };
2839 /*------------------------------------------------------------------
2840 * Test to determine the best read clock delay tuning bits.
2842 * Before the DDR controller can be used, the read clock delay needs to be
2843 * set. This is SDRAM_RQDC[RQFD] and SDRAM_RFDC[RFFD].
2844 * This value cannot be hardcoded into the program because it changes
2845 * depending on the board's setup and environment.
2846 * To do this, all delay values are tested to see if they
2847 * work or not. By doing this, you get groups of fails with groups of
2848 * passing values. The idea is to find the start and end of a passing
2849 * window and take the center of it to use as the read clock delay.
2851 * A failure has to be seen first so that when we hit a pass, we know
2852 * that it is truely the start of the window. If we get passing values
2853 * to start off with, we don't know if we are at the start of the window.
2855 * The code assumes that a failure will always be found.
2856 * If a failure is not found, there is no easy way to get the middle
2857 * of the passing window. I guess we can pretty much pick any value
2858 * but some values will be better than others. Since the lowest speed
2859 * we can clock the DDR interface at is 200 MHz (2x 100 MHz PLB speed),
2860 * from experimentation it is safe to say you will always have a failure.
2861 *-----------------------------------------------------------------*/
2862 mfsdram(SDRAM_MCOPT1, ecc_temp);
2863 ecc_temp &= SDRAM_MCOPT1_MCHK_MASK;
2864 mfsdram(SDRAM_MCOPT1, val);
2865 mtsdram(SDRAM_MCOPT1, (val & ~SDRAM_MCOPT1_MCHK_MASK) |
2866 SDRAM_MCOPT1_MCHK_NON);
2868 window_found = FALSE;
2869 begin_found[0] = FALSE;
2870 end_found[0] = FALSE;
2871 search_end[0] = FALSE;
2872 begin_found[1] = FALSE;
2873 end_found[1] = FALSE;
2874 search_end[1] = FALSE;
2876 for (dimm_num = 0; dimm_num < MAXDIMMS; dimm_num++) {
2877 mfsdram(SDRAM_MB0CF + (bxcr_num << 2), bxcf[bxcr_num]);
2880 if ((bxcf[dimm_num] & SDRAM_BXCF_M_BE_MASK) == SDRAM_BXCF_M_BE_ENABLE) {
2882 /* Bank is enabled */
2884 (unsigned long*)(SDRAM_RXBAS_SDBA_DECODE(mfdcr_any(SDRAM_R0BAS+dimm_num)));
2886 /*------------------------------------------------------------------
2887 * Run the short memory test.
2888 *-----------------------------------------------------------------*/
2889 for (i = 0; i < NUMMEMTESTS; i++) {
2890 for (j = 0; j < NUMMEMWORDS; j++) {
2891 membase[j] = test[i][j];
2892 ppcDcbf((u32)&(membase[j]));
2895 for (j = 0; j < NUMMEMWORDS; j++) {
2896 if (membase[j] != test[i][j]) {
2897 ppcDcbf((u32)&(membase[j]));
2900 ppcDcbf((u32)&(membase[j]));
2903 if (j < NUMMEMWORDS)
2907 /*------------------------------------------------------------------
2908 * See if the rffd value passed.
2909 *-----------------------------------------------------------------*/
2910 if (i < NUMMEMTESTS) {
2911 if ((end_found[dimm_num] == FALSE) &&
2912 (search_end[dimm_num] == TRUE)) {
2913 end_found[dimm_num] = TRUE;
2915 if ((end_found[0] == TRUE) &&
2916 (end_found[1] == TRUE))
2919 if (begin_found[dimm_num] == FALSE) {
2920 begin_found[dimm_num] = TRUE;
2921 search_end[dimm_num] = TRUE;
2925 begin_found[dimm_num] = TRUE;
2926 end_found[dimm_num] = TRUE;
2930 if ((begin_found[0] == TRUE) && (begin_found[1] == TRUE))
2931 window_found = TRUE;
2933 /*------------------------------------------------------------------
2934 * Make sure we found the valid read passing window. Halt if not
2935 *-----------------------------------------------------------------*/
2936 if (window_found == FALSE) {
2937 printf("ERROR: Cannot determine a common read delay for the "
2938 "DIMM(s) installed.\n");
2939 spd_ddr_init_hang ();
2942 /*------------------------------------------------------------------
2943 * Restore the ECC variable to what it originally was
2944 *-----------------------------------------------------------------*/
2945 mtsdram(SDRAM_MCOPT1,
2946 (ppcMfdcr_sdram(SDRAM_MCOPT1) & ~SDRAM_MCOPT1_MCHK_MASK)
2951 #elif defined(CONFIG_405EX)
2952 /*-----------------------------------------------------------------------------
2953 * Function: initdram
2954 * Description: Configures the PPC405EX(r) DDR1/DDR2 SDRAM memory
2955 * banks. The configuration is performed using static, compile-
2957 *---------------------------------------------------------------------------*/
2958 phys_size_t initdram(int board_type)
2961 * Only run this SDRAM init code once. For NAND booting
2962 * targets like Kilauea, we call initdram() early from the
2963 * 4k NAND booting image (CONFIG_NAND_SPL) from nand_boot().
2964 * Later on the NAND U-Boot image runs (CONFIG_NAND_U_BOOT)
2965 * which calls initdram() again. This time the controller
2966 * mustn't be reconfigured again since we're already running
2969 #if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
2972 /* Set Memory Bank Configuration Registers */
2974 mtsdram(SDRAM_MB0CF, CFG_SDRAM0_MB0CF);
2975 mtsdram(SDRAM_MB1CF, CFG_SDRAM0_MB1CF);
2976 mtsdram(SDRAM_MB2CF, CFG_SDRAM0_MB2CF);
2977 mtsdram(SDRAM_MB3CF, CFG_SDRAM0_MB3CF);
2979 /* Set Memory Clock Timing Register */
2981 mtsdram(SDRAM_CLKTR, CFG_SDRAM0_CLKTR);
2983 /* Set Refresh Time Register */
2985 mtsdram(SDRAM_RTR, CFG_SDRAM0_RTR);
2987 /* Set SDRAM Timing Registers */
2989 mtsdram(SDRAM_SDTR1, CFG_SDRAM0_SDTR1);
2990 mtsdram(SDRAM_SDTR2, CFG_SDRAM0_SDTR2);
2991 mtsdram(SDRAM_SDTR3, CFG_SDRAM0_SDTR3);
2993 /* Set Mode and Extended Mode Registers */
2995 mtsdram(SDRAM_MMODE, CFG_SDRAM0_MMODE);
2996 mtsdram(SDRAM_MEMODE, CFG_SDRAM0_MEMODE);
2998 /* Set Memory Controller Options 1 Register */
3000 mtsdram(SDRAM_MCOPT1, CFG_SDRAM0_MCOPT1);
3002 /* Set Manual Initialization Control Registers */
3004 mtsdram(SDRAM_INITPLR0, CFG_SDRAM0_INITPLR0);
3005 mtsdram(SDRAM_INITPLR1, CFG_SDRAM0_INITPLR1);
3006 mtsdram(SDRAM_INITPLR2, CFG_SDRAM0_INITPLR2);
3007 mtsdram(SDRAM_INITPLR3, CFG_SDRAM0_INITPLR3);
3008 mtsdram(SDRAM_INITPLR4, CFG_SDRAM0_INITPLR4);
3009 mtsdram(SDRAM_INITPLR5, CFG_SDRAM0_INITPLR5);
3010 mtsdram(SDRAM_INITPLR6, CFG_SDRAM0_INITPLR6);
3011 mtsdram(SDRAM_INITPLR7, CFG_SDRAM0_INITPLR7);
3012 mtsdram(SDRAM_INITPLR8, CFG_SDRAM0_INITPLR8);
3013 mtsdram(SDRAM_INITPLR9, CFG_SDRAM0_INITPLR9);
3014 mtsdram(SDRAM_INITPLR10, CFG_SDRAM0_INITPLR10);
3015 mtsdram(SDRAM_INITPLR11, CFG_SDRAM0_INITPLR11);
3016 mtsdram(SDRAM_INITPLR12, CFG_SDRAM0_INITPLR12);
3017 mtsdram(SDRAM_INITPLR13, CFG_SDRAM0_INITPLR13);
3018 mtsdram(SDRAM_INITPLR14, CFG_SDRAM0_INITPLR14);
3019 mtsdram(SDRAM_INITPLR15, CFG_SDRAM0_INITPLR15);
3021 /* Set On-Die Termination Registers */
3023 mtsdram(SDRAM_CODT, CFG_SDRAM0_CODT);
3024 mtsdram(SDRAM_MODT0, CFG_SDRAM0_MODT0);
3025 mtsdram(SDRAM_MODT1, CFG_SDRAM0_MODT1);
3027 /* Set Write Timing Register */
3029 mtsdram(SDRAM_WRDTR, CFG_SDRAM0_WRDTR);
3032 * Start Initialization by SDRAM0_MCOPT2[SREN] = 0 and
3033 * SDRAM0_MCOPT2[IPTR] = 1
3036 mtsdram(SDRAM_MCOPT2, (SDRAM_MCOPT2_SREN_EXIT |
3037 SDRAM_MCOPT2_IPTR_EXECUTE));
3040 * Poll SDRAM0_MCSTAT[MIC] for assertion to indicate the
3041 * completion of initialization.
3045 mfsdram(SDRAM_MCSTAT, val);
3046 } while ((val & SDRAM_MCSTAT_MIC_MASK) != SDRAM_MCSTAT_MIC_COMP);
3048 /* Set Delay Control Registers */
3050 mtsdram(SDRAM_DLCR, CFG_SDRAM0_DLCR);
3051 mtsdram(SDRAM_RDCC, CFG_SDRAM0_RDCC);
3052 mtsdram(SDRAM_RQDC, CFG_SDRAM0_RQDC);
3053 mtsdram(SDRAM_RFDC, CFG_SDRAM0_RFDC);
3056 * Enable Controller by SDRAM0_MCOPT2[DCEN] = 1:
3059 mfsdram(SDRAM_MCOPT2, val);
3060 mtsdram(SDRAM_MCOPT2, val | SDRAM_MCOPT2_DCEN_ENABLE);
3062 #if defined(CONFIG_DDR_ECC)
3063 ecc_init(CFG_SDRAM_BASE, CFG_MBYTES_SDRAM << 20);
3064 #endif /* defined(CONFIG_DDR_ECC) */
3066 ppc4xx_ibm_ddr2_register_dump();
3067 #endif /* !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) */
3069 return (CFG_MBYTES_SDRAM << 20);
3071 #endif /* defined(CONFIG_SPD_EEPROM) && defined(CONFIG_440SP) || ... */
3073 static void ppc4xx_ibm_ddr2_register_dump(void)
3075 #if defined(DEBUG) && defined(CONFIG_SDRAM_PPC4xx_IBM_DDR2)
3076 #define PPC4xx_IBM_DDR2_DUMP_REGISTER(mnemonic) \
3079 mfsdram(SDRAM_##mnemonic, data); \
3080 printf("%20s[%02x] = 0x%08X\n", \
3081 "SDRAM_" #mnemonic, SDRAM_##mnemonic, data); \
3084 printf("\nPPC4xx IBM DDR2 Register Dump:\n");
3086 #if (defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
3087 defined(CONFIG_460EX) || defined(CONFIG_460GT))
3088 PPC4xx_IBM_DDR2_DUMP_REGISTER(R0BAS);
3089 PPC4xx_IBM_DDR2_DUMP_REGISTER(R1BAS);
3090 PPC4xx_IBM_DDR2_DUMP_REGISTER(R2BAS);
3091 PPC4xx_IBM_DDR2_DUMP_REGISTER(R3BAS);
3092 #endif /* (defined(CONFIG_440SP) || ... */
3093 #if defined(CONFIG_405EX)
3094 PPC4xx_IBM_DDR2_DUMP_REGISTER(BESR);
3095 PPC4xx_IBM_DDR2_DUMP_REGISTER(BEARL);
3096 PPC4xx_IBM_DDR2_DUMP_REGISTER(BEARH);
3097 PPC4xx_IBM_DDR2_DUMP_REGISTER(WMIRQ);
3098 PPC4xx_IBM_DDR2_DUMP_REGISTER(PLBOPT);
3099 PPC4xx_IBM_DDR2_DUMP_REGISTER(PUABA);
3100 #endif /* defined(CONFIG_405EX) */
3101 PPC4xx_IBM_DDR2_DUMP_REGISTER(MB0CF);
3102 PPC4xx_IBM_DDR2_DUMP_REGISTER(MB1CF);
3103 PPC4xx_IBM_DDR2_DUMP_REGISTER(MB2CF);
3104 PPC4xx_IBM_DDR2_DUMP_REGISTER(MB3CF);
3105 PPC4xx_IBM_DDR2_DUMP_REGISTER(MCSTAT);
3106 PPC4xx_IBM_DDR2_DUMP_REGISTER(MCOPT1);
3107 PPC4xx_IBM_DDR2_DUMP_REGISTER(MCOPT2);
3108 PPC4xx_IBM_DDR2_DUMP_REGISTER(MODT0);
3109 PPC4xx_IBM_DDR2_DUMP_REGISTER(MODT1);
3110 PPC4xx_IBM_DDR2_DUMP_REGISTER(MODT2);
3111 PPC4xx_IBM_DDR2_DUMP_REGISTER(MODT3);
3112 PPC4xx_IBM_DDR2_DUMP_REGISTER(CODT);
3113 #if (defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
3114 defined(CONFIG_460EX) || defined(CONFIG_460GT))
3115 PPC4xx_IBM_DDR2_DUMP_REGISTER(VVPR);
3116 PPC4xx_IBM_DDR2_DUMP_REGISTER(OPARS);
3118 * OPART is only used as a trigger register.
3120 * No data is contained in this register, and reading or writing
3121 * to is can cause bad things to happen (hangs). Just skip it and
3124 printf("%20s = N/A\n", "SDRAM_OPART");
3125 #endif /* defined(CONFIG_440SP) || ... */
3126 PPC4xx_IBM_DDR2_DUMP_REGISTER(RTR);
3127 PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR0);
3128 PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR1);
3129 PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR2);
3130 PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR3);
3131 PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR4);
3132 PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR5);
3133 PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR6);
3134 PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR7);
3135 PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR8);
3136 PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR9);
3137 PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR10);
3138 PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR11);
3139 PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR12);
3140 PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR13);
3141 PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR14);
3142 PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR15);
3143 PPC4xx_IBM_DDR2_DUMP_REGISTER(RQDC);
3144 PPC4xx_IBM_DDR2_DUMP_REGISTER(RFDC);
3145 PPC4xx_IBM_DDR2_DUMP_REGISTER(RDCC);
3146 PPC4xx_IBM_DDR2_DUMP_REGISTER(DLCR);
3147 PPC4xx_IBM_DDR2_DUMP_REGISTER(CLKTR);
3148 PPC4xx_IBM_DDR2_DUMP_REGISTER(WRDTR);
3149 PPC4xx_IBM_DDR2_DUMP_REGISTER(SDTR1);
3150 PPC4xx_IBM_DDR2_DUMP_REGISTER(SDTR2);
3151 PPC4xx_IBM_DDR2_DUMP_REGISTER(SDTR3);
3152 PPC4xx_IBM_DDR2_DUMP_REGISTER(MMODE);
3153 PPC4xx_IBM_DDR2_DUMP_REGISTER(MEMODE);
3154 PPC4xx_IBM_DDR2_DUMP_REGISTER(ECCCR);
3155 #if (defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
3156 defined(CONFIG_460EX) || defined(CONFIG_460GT))
3157 PPC4xx_IBM_DDR2_DUMP_REGISTER(CID);
3158 #endif /* defined(CONFIG_440SP) || ... */
3159 PPC4xx_IBM_DDR2_DUMP_REGISTER(RID);
3160 PPC4xx_IBM_DDR2_DUMP_REGISTER(FCSR);
3161 PPC4xx_IBM_DDR2_DUMP_REGISTER(RTSR);
3162 #endif /* defined(DEBUG) && defined(CONFIG_SDRAM_PPC4xx_IBM_DDR2) */