2 * cpu/ppc4xx/44x_spd_ddr.c
3 * This SPD DDR detection code supports IBM/AMCC PPC44x cpu with a
4 * DDR controller. Those are 440GP/GX/EP/GR.
7 * Bill Hunter, Wave 7 Optics, williamhunter@attbi.com
11 * Kenneth Johansson ,Ericsson AB.
12 * kenneth.johansson@etx.ericsson.se
14 * hacked up by bill hunter. fixed so we could run before
15 * serial_init and console_init. previous version avoided this by
16 * running out of cache memory during serial/console init, then running
20 * Jun Gu, Artesyn Technology, jung@artesyncp.com
21 * Support for AMCC 440 based on OpenBIOS draminit.c from IBM.
23 * (C) Copyright 2005-2007
24 * Stefan Roese, DENX Software Engineering, sr@denx.de.
26 * See file CREDITS for list of people who contributed to this
29 * This program is free software; you can redistribute it and/or
30 * modify it under the terms of the GNU General Public License as
31 * published by the Free Software Foundation; either version 2 of
32 * the License, or (at your option) any later version.
34 * This program is distributed in the hope that it will be useful,
35 * but WITHOUT ANY WARRANTY; without even the implied warranty of
36 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
37 * GNU General Public License for more details.
39 * You should have received a copy of the GNU General Public License
40 * along with this program; if not, write to the Free Software
41 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
45 /* define DEBUG for debugging output (obviously ;-)) */
51 #include <asm/processor.h>
58 #if defined(CONFIG_SPD_EEPROM) && \
59 (defined(CONFIG_440GP) || defined(CONFIG_440GX) || \
60 defined(CONFIG_440EP) || defined(CONFIG_440GR))
65 #ifndef CONFIG_SYS_I2C_SPEED
66 #define CONFIG_SYS_I2C_SPEED 50000
69 #ifndef CONFIG_SYS_I2C_SLAVE
70 #define CONFIG_SYS_I2C_SLAVE 0xFE
73 #define ONE_BILLION 1000000000
76 * Board-specific Platform code can reimplement spd_ddr_init_hang () if needed
78 void __spd_ddr_init_hang (void)
82 void spd_ddr_init_hang (void) __attribute__((weak, alias("__spd_ddr_init_hang")));
84 /*-----------------------------------------------------------------------------+
86 +-----------------------------------------------------------------------------*/
87 #define DEFAULT_SPD_ADDR1 0x53
88 #define DEFAULT_SPD_ADDR2 0x52
89 #define MAXBANKS 4 /* at most 4 dimm banks */
90 #define MAX_SPD_BYTES 256
91 #define NUMHALFCYCLES 4
99 * This DDR2 setup code can dynamically setup the TLB entries for the DDR2 memory
100 * region. Right now the cache should still be disabled in U-Boot because of the
101 * EMAC driver, that need it's buffer descriptor to be located in non cached
104 * If at some time this restriction doesn't apply anymore, just define
105 * CONFIG_4xx_DCACHE in the board config file and this code should setup
106 * everything correctly.
108 #ifdef CONFIG_4xx_DCACHE
109 #define MY_TLB_WORD2_I_ENABLE 0 /* enable caching on SDRAM */
111 #define MY_TLB_WORD2_I_ENABLE TLB_WORD2_I_ENABLE /* disable caching on SDRAM */
114 /* bank_parms is used to sort the bank sizes by descending order */
117 unsigned long bank_size_bytes;
120 typedef struct bank_param BANKPARMS;
122 #ifdef CONFIG_SYS_SIMULATE_SPD_EEPROM
123 extern const unsigned char cfg_simulate_spd_eeprom[128];
126 static unsigned char spd_read(uchar chip, uint addr);
127 static void get_spd_info(unsigned long *dimm_populated,
128 unsigned char *iic0_dimm_addr,
129 unsigned long num_dimm_banks);
130 static void check_mem_type(unsigned long *dimm_populated,
131 unsigned char *iic0_dimm_addr,
132 unsigned long num_dimm_banks);
133 static void check_volt_type(unsigned long *dimm_populated,
134 unsigned char *iic0_dimm_addr,
135 unsigned long num_dimm_banks);
136 static void program_cfg0(unsigned long *dimm_populated,
137 unsigned char *iic0_dimm_addr,
138 unsigned long num_dimm_banks);
139 static void program_cfg1(unsigned long *dimm_populated,
140 unsigned char *iic0_dimm_addr,
141 unsigned long num_dimm_banks);
142 static void program_rtr(unsigned long *dimm_populated,
143 unsigned char *iic0_dimm_addr,
144 unsigned long num_dimm_banks);
145 static void program_tr0(unsigned long *dimm_populated,
146 unsigned char *iic0_dimm_addr,
147 unsigned long num_dimm_banks);
148 static void program_tr1(void);
150 static unsigned long program_bxcr(unsigned long *dimm_populated,
151 unsigned char *iic0_dimm_addr,
152 unsigned long num_dimm_banks);
155 * This function is reading data from the DIMM module EEPROM over the SPD bus
156 * and uses that to program the sdram controller.
158 * This works on boards that has the same schematics that the AMCC walnut has.
160 * BUG: Don't handle ECC memory
161 * BUG: A few values in the TR register is currently hardcoded
163 long int spd_sdram(void) {
164 unsigned char iic0_dimm_addr[] = SPD_EEPROM_ADDRESS;
165 unsigned long dimm_populated[sizeof(iic0_dimm_addr)];
166 unsigned long total_size;
169 unsigned long num_dimm_banks; /* on board dimm banks */
171 num_dimm_banks = sizeof(iic0_dimm_addr);
174 * Make sure I2C controller is initialized
177 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
180 * Read the SPD information using I2C interface. Check to see if the
181 * DIMM slots are populated.
183 get_spd_info(dimm_populated, iic0_dimm_addr, num_dimm_banks);
186 * Check the memory type for the dimms plugged.
188 check_mem_type(dimm_populated, iic0_dimm_addr, num_dimm_banks);
191 * Check the voltage type for the dimms plugged.
193 check_volt_type(dimm_populated, iic0_dimm_addr, num_dimm_banks);
195 #if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
197 * Soft-reset SDRAM controller.
199 mtsdr(sdr_srst, SDR0_SRST_DMC);
200 mtsdr(sdr_srst, 0x00000000);
204 * program 440GP SDRAM controller options (SDRAM0_CFG0)
206 program_cfg0(dimm_populated, iic0_dimm_addr, num_dimm_banks);
209 * program 440GP SDRAM controller options (SDRAM0_CFG1)
211 program_cfg1(dimm_populated, iic0_dimm_addr, num_dimm_banks);
214 * program SDRAM refresh register (SDRAM0_RTR)
216 program_rtr(dimm_populated, iic0_dimm_addr, num_dimm_banks);
219 * program SDRAM Timing Register 0 (SDRAM0_TR0)
221 program_tr0(dimm_populated, iic0_dimm_addr, num_dimm_banks);
224 * program the BxCR registers to find out total sdram installed
226 total_size = program_bxcr(dimm_populated, iic0_dimm_addr,
229 #ifdef CONFIG_PROG_SDRAM_TLB /* this define should eventually be removed */
230 /* and program tlb entries for this size (dynamic) */
231 program_tlb(0, 0, total_size, MY_TLB_WORD2_I_ENABLE);
235 * program SDRAM Clock Timing Register (SDRAM0_CLKTR)
237 mtsdram(mem_clktr, 0x40000000);
240 * delay to ensure 200 usec has elapsed
245 * enable the memory controller
247 mfsdram(mem_cfg0, cfg0);
248 mtsdram(mem_cfg0, cfg0 | SDRAM_CFG0_DCEN);
251 * wait for SDRAM_CFG0_DC_EN to complete
254 mfsdram(mem_mcsts, mcsts);
255 if ((mcsts & SDRAM_MCSTS_MRSC) != 0)
260 * program SDRAM Timing Register 1, adding some delays
264 #ifdef CONFIG_DDR_ECC
266 * If ecc is enabled, initialize the parity bits.
268 ecc_init(CONFIG_SYS_SDRAM_BASE, total_size);
274 static unsigned char spd_read(uchar chip, uint addr)
276 unsigned char data[2];
278 #ifdef CONFIG_SYS_SIMULATE_SPD_EEPROM
279 if (chip == CONFIG_SYS_SIMULATE_SPD_EEPROM) {
281 * Onboard spd eeprom requested -> simulate values
283 return cfg_simulate_spd_eeprom[addr];
285 #endif /* CONFIG_SYS_SIMULATE_SPD_EEPROM */
287 if (i2c_probe(chip) == 0) {
288 if (i2c_read(chip, addr, 1, data, 1) == 0) {
296 static void get_spd_info(unsigned long *dimm_populated,
297 unsigned char *iic0_dimm_addr,
298 unsigned long num_dimm_banks)
300 unsigned long dimm_num;
301 unsigned long dimm_found;
302 unsigned char num_of_bytes;
303 unsigned char total_size;
306 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
310 num_of_bytes = spd_read(iic0_dimm_addr[dimm_num], 0);
311 total_size = spd_read(iic0_dimm_addr[dimm_num], 1);
313 if ((num_of_bytes != 0) && (total_size != 0)) {
314 dimm_populated[dimm_num] = TRUE;
316 debug("DIMM slot %lu: populated\n", dimm_num);
318 dimm_populated[dimm_num] = FALSE;
319 debug("DIMM slot %lu: Not populated\n", dimm_num);
323 if (dimm_found == FALSE) {
324 printf("ERROR - No memory installed. Install a DDR-SDRAM DIMM.\n\n");
325 spd_ddr_init_hang ();
329 static void check_mem_type(unsigned long *dimm_populated,
330 unsigned char *iic0_dimm_addr,
331 unsigned long num_dimm_banks)
333 unsigned long dimm_num;
334 unsigned char dimm_type;
336 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
337 if (dimm_populated[dimm_num] == TRUE) {
338 dimm_type = spd_read(iic0_dimm_addr[dimm_num], 2);
341 debug("DIMM slot %lu: DDR SDRAM detected\n", dimm_num);
344 printf("ERROR: Unsupported DIMM detected in slot %lu.\n",
346 printf("Only DDR SDRAM DIMMs are supported.\n");
347 printf("Replace the DIMM module with a supported DIMM.\n\n");
348 spd_ddr_init_hang ();
355 static void check_volt_type(unsigned long *dimm_populated,
356 unsigned char *iic0_dimm_addr,
357 unsigned long num_dimm_banks)
359 unsigned long dimm_num;
360 unsigned long voltage_type;
362 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
363 if (dimm_populated[dimm_num] == TRUE) {
364 voltage_type = spd_read(iic0_dimm_addr[dimm_num], 8);
365 if (voltage_type != 0x04) {
366 printf("ERROR: DIMM %lu with unsupported voltage level.\n",
368 spd_ddr_init_hang ();
370 debug("DIMM %lu voltage level supported.\n", dimm_num);
377 static void program_cfg0(unsigned long *dimm_populated,
378 unsigned char *iic0_dimm_addr,
379 unsigned long num_dimm_banks)
381 unsigned long dimm_num;
383 unsigned long ecc_enabled;
385 unsigned char attributes;
386 unsigned long data_width;
387 unsigned long dimm_32bit;
388 unsigned long dimm_64bit;
391 * get Memory Controller Options 0 data
393 mfsdram(mem_cfg0, cfg0);
398 cfg0 &= ~(SDRAM_CFG0_DCEN | SDRAM_CFG0_MCHK_MASK |
399 SDRAM_CFG0_RDEN | SDRAM_CFG0_PMUD |
400 SDRAM_CFG0_DMWD_MASK |
401 SDRAM_CFG0_UIOS_MASK | SDRAM_CFG0_PDP);
405 * FIXME: assume the DDR SDRAMs in both banks are the same
408 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
409 if (dimm_populated[dimm_num] == TRUE) {
410 ecc = spd_read(iic0_dimm_addr[dimm_num], 11);
416 * program Registered DIMM Enable
418 attributes = spd_read(iic0_dimm_addr[dimm_num], 21);
419 if ((attributes & 0x02) != 0x00) {
420 cfg0 |= SDRAM_CFG0_RDEN;
424 * program DDR SDRAM Data Width
427 (unsigned long)spd_read(iic0_dimm_addr[dimm_num],6) +
428 (((unsigned long)spd_read(iic0_dimm_addr[dimm_num],7)) << 8);
429 if (data_width == 64 || data_width == 72) {
431 cfg0 |= SDRAM_CFG0_DMWD_64;
432 } else if (data_width == 32 || data_width == 40) {
434 cfg0 |= SDRAM_CFG0_DMWD_32;
436 printf("WARNING: DIMM with datawidth of %lu bits.\n",
438 printf("Only DIMMs with 32 or 64 bit datawidths supported.\n");
439 spd_ddr_init_hang ();
446 * program Memory Data Error Checking
448 if (ecc_enabled == TRUE) {
449 cfg0 |= SDRAM_CFG0_MCHK_GEN;
451 cfg0 |= SDRAM_CFG0_MCHK_NON;
455 * program Page Management Unit (0 == enabled)
457 cfg0 &= ~SDRAM_CFG0_PMUD;
460 * program Memory Controller Options 0
461 * Note: DCEN must be enabled after all DDR SDRAM controller
462 * configuration registers get initialized.
464 mtsdram(mem_cfg0, cfg0);
467 static void program_cfg1(unsigned long *dimm_populated,
468 unsigned char *iic0_dimm_addr,
469 unsigned long num_dimm_banks)
472 mfsdram(mem_cfg1, cfg1);
475 * Self-refresh exit, disable PM
477 cfg1 &= ~(SDRAM_CFG1_SRE | SDRAM_CFG1_PMEN);
480 * program Memory Controller Options 1
482 mtsdram(mem_cfg1, cfg1);
485 static void program_rtr(unsigned long *dimm_populated,
486 unsigned char *iic0_dimm_addr,
487 unsigned long num_dimm_banks)
489 unsigned long dimm_num;
490 unsigned long bus_period_x_10;
491 unsigned long refresh_rate = 0;
492 unsigned char refresh_rate_type;
493 unsigned long refresh_interval;
494 unsigned long sdram_rtr;
495 PPC4xx_SYS_INFO sys_info;
500 get_sys_info(&sys_info);
501 bus_period_x_10 = ONE_BILLION / (sys_info.freqPLB / 10);
503 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
504 if (dimm_populated[dimm_num] == TRUE) {
505 refresh_rate_type = 0x7F & spd_read(iic0_dimm_addr[dimm_num], 12);
506 switch (refresh_rate_type) {
508 refresh_rate = 15625;
511 refresh_rate = 15625/4;
514 refresh_rate = 15625/2;
517 refresh_rate = 15626*2;
520 refresh_rate = 15625*4;
523 refresh_rate = 15625*8;
526 printf("ERROR: DIMM %lu, unsupported refresh rate/type.\n",
528 printf("Replace the DIMM module with a supported DIMM.\n");
536 refresh_interval = refresh_rate * 10 / bus_period_x_10;
537 sdram_rtr = (refresh_interval & 0x3ff8) << 16;
540 * program Refresh Timer Register (SDRAM0_RTR)
542 mtsdram(mem_rtr, sdram_rtr);
545 static void program_tr0(unsigned long *dimm_populated,
546 unsigned char *iic0_dimm_addr,
547 unsigned long num_dimm_banks)
549 unsigned long dimm_num;
552 unsigned char t_rp_ns;
553 unsigned char t_rcd_ns;
554 unsigned char t_ras_ns;
555 unsigned long t_rp_clk;
556 unsigned long t_ras_rcd_clk;
557 unsigned long t_rcd_clk;
558 unsigned long t_rfc_clk;
559 unsigned long plb_check;
560 unsigned char cas_bit;
561 unsigned long cas_index;
562 unsigned char cas_2_0_available;
563 unsigned char cas_2_5_available;
564 unsigned char cas_3_0_available;
565 unsigned long cycle_time_ns_x_10[3];
566 unsigned long tcyc_3_0_ns_x_10;
567 unsigned long tcyc_2_5_ns_x_10;
568 unsigned long tcyc_2_0_ns_x_10;
569 unsigned long tcyc_reg;
570 unsigned long bus_period_x_10;
571 PPC4xx_SYS_INFO sys_info;
572 unsigned long residue;
577 get_sys_info(&sys_info);
578 bus_period_x_10 = ONE_BILLION / (sys_info.freqPLB / 10);
581 * get SDRAM Timing Register 0 (SDRAM_TR0) and clear bits
583 mfsdram(mem_tr0, tr0);
584 tr0 &= ~(SDRAM_TR0_SDWR_MASK | SDRAM_TR0_SDWD_MASK |
585 SDRAM_TR0_SDCL_MASK | SDRAM_TR0_SDPA_MASK |
586 SDRAM_TR0_SDCP_MASK | SDRAM_TR0_SDLD_MASK |
587 SDRAM_TR0_SDRA_MASK | SDRAM_TR0_SDRD_MASK);
596 cas_2_0_available = TRUE;
597 cas_2_5_available = TRUE;
598 cas_3_0_available = TRUE;
599 tcyc_2_0_ns_x_10 = 0;
600 tcyc_2_5_ns_x_10 = 0;
601 tcyc_3_0_ns_x_10 = 0;
603 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
604 if (dimm_populated[dimm_num] == TRUE) {
605 wcsbc = spd_read(iic0_dimm_addr[dimm_num], 15);
606 t_rp_ns = spd_read(iic0_dimm_addr[dimm_num], 27) >> 2;
607 t_rcd_ns = spd_read(iic0_dimm_addr[dimm_num], 29) >> 2;
608 t_ras_ns = spd_read(iic0_dimm_addr[dimm_num], 30);
609 cas_bit = spd_read(iic0_dimm_addr[dimm_num], 18);
611 for (cas_index = 0; cas_index < 3; cas_index++) {
614 tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 9);
617 tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 23);
620 tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 25);
624 if ((tcyc_reg & 0x0F) >= 10) {
625 printf("ERROR: Tcyc incorrect for DIMM in slot %lu\n",
627 spd_ddr_init_hang ();
630 cycle_time_ns_x_10[cas_index] =
631 (((tcyc_reg & 0xF0) >> 4) * 10) + (tcyc_reg & 0x0F);
636 if ((cas_bit & 0x80) != 0) {
638 } else if ((cas_bit & 0x40) != 0) {
640 } else if ((cas_bit & 0x20) != 0) {
644 if (((cas_bit & 0x10) != 0) && (cas_index < 3)) {
645 tcyc_3_0_ns_x_10 = cycle_time_ns_x_10[cas_index];
648 if (cas_index != 0) {
651 cas_3_0_available = FALSE;
654 if (((cas_bit & 0x08) != 0) || (cas_index < 3)) {
655 tcyc_2_5_ns_x_10 = cycle_time_ns_x_10[cas_index];
658 if (cas_index != 0) {
661 cas_2_5_available = FALSE;
664 if (((cas_bit & 0x04) != 0) || (cas_index < 3)) {
665 tcyc_2_0_ns_x_10 = cycle_time_ns_x_10[cas_index];
668 if (cas_index != 0) {
671 cas_2_0_available = FALSE;
679 * Program SD_WR and SD_WCSBC fields
681 tr0 |= SDRAM_TR0_SDWR_2_CLK; /* Write Recovery: 2 CLK */
684 tr0 |= SDRAM_TR0_SDWD_0_CLK;
687 tr0 |= SDRAM_TR0_SDWD_1_CLK;
692 * Program SD_CASL field
694 if ((cas_2_0_available == TRUE) &&
695 (bus_period_x_10 >= tcyc_2_0_ns_x_10)) {
696 tr0 |= SDRAM_TR0_SDCL_2_0_CLK;
697 } else if ((cas_2_5_available == TRUE) &&
698 (bus_period_x_10 >= tcyc_2_5_ns_x_10)) {
699 tr0 |= SDRAM_TR0_SDCL_2_5_CLK;
700 } else if ((cas_3_0_available == TRUE) &&
701 (bus_period_x_10 >= tcyc_3_0_ns_x_10)) {
702 tr0 |= SDRAM_TR0_SDCL_3_0_CLK;
704 printf("ERROR: No supported CAS latency with the installed DIMMs.\n");
705 printf("Only CAS latencies of 2.0, 2.5, and 3.0 are supported.\n");
706 printf("Make sure the PLB speed is within the supported range.\n");
707 spd_ddr_init_hang ();
711 * Calculate Trp in clock cycles and round up if necessary
712 * Program SD_PTA field
714 t_rp_clk = sys_info.freqPLB * t_rp_ns / ONE_BILLION;
715 plb_check = ONE_BILLION * t_rp_clk / t_rp_ns;
716 if (sys_info.freqPLB != plb_check) {
719 switch ((unsigned long)t_rp_clk) {
723 tr0 |= SDRAM_TR0_SDPA_2_CLK;
726 tr0 |= SDRAM_TR0_SDPA_3_CLK;
729 tr0 |= SDRAM_TR0_SDPA_4_CLK;
734 * Program SD_CTP field
736 t_ras_rcd_clk = sys_info.freqPLB * (t_ras_ns - t_rcd_ns) / ONE_BILLION;
737 plb_check = ONE_BILLION * t_ras_rcd_clk / (t_ras_ns - t_rcd_ns);
738 if (sys_info.freqPLB != plb_check) {
741 switch (t_ras_rcd_clk) {
745 tr0 |= SDRAM_TR0_SDCP_2_CLK;
748 tr0 |= SDRAM_TR0_SDCP_3_CLK;
751 tr0 |= SDRAM_TR0_SDCP_4_CLK;
754 tr0 |= SDRAM_TR0_SDCP_5_CLK;
759 * Program SD_LDF field
761 tr0 |= SDRAM_TR0_SDLD_2_CLK;
764 * Program SD_RFTA field
765 * FIXME tRFC hardcoded as 75 nanoseconds
767 t_rfc_clk = sys_info.freqPLB / (ONE_BILLION / 75);
768 residue = sys_info.freqPLB % (ONE_BILLION / 75);
769 if (residue >= (ONE_BILLION / 150)) {
780 tr0 |= SDRAM_TR0_SDRA_6_CLK;
783 tr0 |= SDRAM_TR0_SDRA_7_CLK;
786 tr0 |= SDRAM_TR0_SDRA_8_CLK;
789 tr0 |= SDRAM_TR0_SDRA_9_CLK;
792 tr0 |= SDRAM_TR0_SDRA_10_CLK;
795 tr0 |= SDRAM_TR0_SDRA_11_CLK;
798 tr0 |= SDRAM_TR0_SDRA_12_CLK;
801 tr0 |= SDRAM_TR0_SDRA_13_CLK;
806 * Program SD_RCD field
808 t_rcd_clk = sys_info.freqPLB * t_rcd_ns / ONE_BILLION;
809 plb_check = ONE_BILLION * t_rcd_clk / t_rcd_ns;
810 if (sys_info.freqPLB != plb_check) {
817 tr0 |= SDRAM_TR0_SDRD_2_CLK;
820 tr0 |= SDRAM_TR0_SDRD_3_CLK;
823 tr0 |= SDRAM_TR0_SDRD_4_CLK;
827 debug("tr0: %x\n", tr0);
828 mtsdram(mem_tr0, tr0);
831 static int short_mem_test(void)
834 unsigned long bxcr_num;
835 unsigned long *membase;
836 const unsigned long test[NUMMEMTESTS][NUMMEMWORDS] = {
837 {0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
838 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF},
839 {0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
840 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000},
841 {0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
842 0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555},
843 {0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
844 0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA},
845 {0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
846 0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A},
847 {0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
848 0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5},
849 {0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
850 0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA},
851 {0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
852 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55}};
854 for (bxcr_num = 0; bxcr_num < MAXBXCR; bxcr_num++) {
855 mtdcr(memcfga, mem_b0cr + (bxcr_num << 2));
856 if ((mfdcr(memcfgd) & SDRAM_BXCR_SDBE) == SDRAM_BXCR_SDBE) {
857 /* Bank is enabled */
858 membase = (unsigned long*)
859 (mfdcr(memcfgd) & SDRAM_BXCR_SDBA_MASK);
862 * Run the short memory test
864 for (i = 0; i < NUMMEMTESTS; i++) {
865 for (j = 0; j < NUMMEMWORDS; j++) {
866 /* printf("bank enabled base:%x\n", &membase[j]); */
867 membase[j] = test[i][j];
868 ppcDcbf((unsigned long)&(membase[j]));
871 for (j = 0; j < NUMMEMWORDS; j++) {
872 if (membase[j] != test[i][j]) {
873 ppcDcbf((unsigned long)&(membase[j]));
876 ppcDcbf((unsigned long)&(membase[j]));
884 * see if the rdclt value passed
894 static void program_tr1(void)
899 unsigned long ecc_temp;
900 unsigned long dlycal;
901 unsigned long dly_val;
903 unsigned long max_pass_length;
904 unsigned long current_pass_length;
905 unsigned long current_fail_length;
906 unsigned long current_start;
908 unsigned long rdclt_offset;
912 unsigned char window_found;
913 unsigned char fail_found;
914 unsigned char pass_found;
915 PPC4xx_SYS_INFO sys_info;
920 get_sys_info(&sys_info);
923 * get SDRAM Timing Register 0 (SDRAM_TR0) and clear bits
925 mfsdram(mem_tr1, tr1);
926 tr1 &= ~(SDRAM_TR1_RDSS_MASK | SDRAM_TR1_RDSL_MASK |
927 SDRAM_TR1_RDCD_MASK | SDRAM_TR1_RDCT_MASK);
929 mfsdram(mem_tr0, tr0);
930 if (((tr0 & SDRAM_TR0_SDCL_MASK) == SDRAM_TR0_SDCL_2_5_CLK) &&
931 (sys_info.freqPLB > 100000000)) {
932 tr1 |= SDRAM_TR1_RDSS_TR2;
933 tr1 |= SDRAM_TR1_RDSL_STAGE3;
934 tr1 |= SDRAM_TR1_RDCD_RCD_1_2;
936 tr1 |= SDRAM_TR1_RDSS_TR1;
937 tr1 |= SDRAM_TR1_RDSL_STAGE2;
938 tr1 |= SDRAM_TR1_RDCD_RCD_0_0;
942 * save CFG0 ECC setting to a temporary variable and turn ECC off
944 mfsdram(mem_cfg0, cfg0);
945 ecc_temp = cfg0 & SDRAM_CFG0_MCHK_MASK;
946 mtsdram(mem_cfg0, (cfg0 & ~SDRAM_CFG0_MCHK_MASK) | SDRAM_CFG0_MCHK_NON);
949 * get the delay line calibration register value
951 mfsdram(mem_dlycal, dlycal);
952 dly_val = SDRAM_DLYCAL_DLCV_DECODE(dlycal) << 2;
957 current_pass_length = 0;
958 current_fail_length = 0;
961 window_found = FALSE;
964 debug("Starting memory test ");
966 for (k = 0; k < NUMHALFCYCLES; k++) {
967 for (rdclt = 0; rdclt < dly_val; rdclt++) {
969 * Set the timing reg for the test.
971 mtsdram(mem_tr1, (tr1 | SDRAM_TR1_RDCT_ENCODE(rdclt)));
973 if (short_mem_test()) {
974 if (fail_found == TRUE) {
976 if (current_pass_length == 0) {
977 current_start = rdclt_offset + rdclt;
980 current_fail_length = 0;
981 current_pass_length++;
983 if (current_pass_length > max_pass_length) {
984 max_pass_length = current_pass_length;
985 max_start = current_start;
986 max_end = rdclt_offset + rdclt;
990 current_pass_length = 0;
991 current_fail_length++;
993 if (current_fail_length >= (dly_val>>2)) {
994 if (fail_found == FALSE) {
996 } else if (pass_found == TRUE) {
1005 if (window_found == TRUE) {
1009 tr1 = tr1 ^ SDRAM_TR1_RDCD_MASK;
1010 rdclt_offset += dly_val;
1015 * make sure we find the window
1017 if (window_found == FALSE) {
1018 printf("ERROR: Cannot determine a common read delay.\n");
1019 spd_ddr_init_hang ();
1023 * restore the orignal ECC setting
1025 mtsdram(mem_cfg0, (cfg0 & ~SDRAM_CFG0_MCHK_MASK) | ecc_temp);
1028 * set the SDRAM TR1 RDCD value
1030 tr1 &= ~SDRAM_TR1_RDCD_MASK;
1031 if ((tr0 & SDRAM_TR0_SDCL_MASK) == SDRAM_TR0_SDCL_2_5_CLK) {
1032 tr1 |= SDRAM_TR1_RDCD_RCD_1_2;
1034 tr1 |= SDRAM_TR1_RDCD_RCD_0_0;
1038 * set the SDRAM TR1 RDCLT value
1040 tr1 &= ~SDRAM_TR1_RDCT_MASK;
1041 while (max_end >= (dly_val << 1)) {
1042 max_end -= (dly_val << 1);
1043 max_start -= (dly_val << 1);
1046 rdclt_average = ((max_start + max_end) >> 1);
1048 if (rdclt_average < 0) {
1052 if (rdclt_average >= dly_val) {
1053 rdclt_average -= dly_val;
1054 tr1 = tr1 ^ SDRAM_TR1_RDCD_MASK;
1056 tr1 |= SDRAM_TR1_RDCT_ENCODE(rdclt_average);
1058 debug("tr1: %x\n", tr1);
1061 * program SDRAM Timing Register 1 TR1
1063 mtsdram(mem_tr1, tr1);
1066 static unsigned long program_bxcr(unsigned long *dimm_populated,
1067 unsigned char *iic0_dimm_addr,
1068 unsigned long num_dimm_banks)
1070 unsigned long dimm_num;
1071 unsigned long bank_base_addr;
1076 unsigned char num_row_addr;
1077 unsigned char num_col_addr;
1078 unsigned char num_banks;
1079 unsigned char bank_size_id;
1080 unsigned long ctrl_bank_num[MAXBANKS];
1081 unsigned long bx_cr_num;
1082 unsigned long largest_size_index;
1083 unsigned long largest_size;
1084 unsigned long current_size_index;
1085 BANKPARMS bank_parms[MAXBXCR];
1086 unsigned long sorted_bank_num[MAXBXCR]; /* DDR Controller bank number table (sorted by size) */
1087 unsigned long sorted_bank_size[MAXBXCR]; /* DDR Controller bank size table (sorted by size)*/
1090 * Set the BxCR regs. First, wipe out the bank config registers.
1092 for (bx_cr_num = 0; bx_cr_num < MAXBXCR; bx_cr_num++) {
1093 mtdcr(memcfga, mem_b0cr + (bx_cr_num << 2));
1094 mtdcr(memcfgd, 0x00000000);
1095 bank_parms[bx_cr_num].bank_size_bytes = 0;
1098 #ifdef CONFIG_BAMBOO
1100 * This next section is hardware dependent and must be programmed
1101 * to match the hardware. For bamboo, the following holds...
1102 * 1. SDRAM0_B0CR: Bank 0 of dimm 0 ctrl_bank_num : 0 (soldered onboard)
1103 * 2. SDRAM0_B1CR: Bank 0 of dimm 1 ctrl_bank_num : 1
1104 * 3. SDRAM0_B2CR: Bank 1 of dimm 1 ctrl_bank_num : 1
1105 * 4. SDRAM0_B3CR: Bank 0 of dimm 2 ctrl_bank_num : 3
1106 * ctrl_bank_num corresponds to the first usable DDR controller bank number by DIMM
1108 ctrl_bank_num[0] = 0;
1109 ctrl_bank_num[1] = 1;
1110 ctrl_bank_num[2] = 3;
1113 * Ocotea, Ebony and the other IBM/AMCC eval boards have
1114 * 2 DIMM slots with each max 2 banks
1116 ctrl_bank_num[0] = 0;
1117 ctrl_bank_num[1] = 2;
1121 * reset the bank_base address
1123 bank_base_addr = CONFIG_SYS_SDRAM_BASE;
1125 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1126 if (dimm_populated[dimm_num] == TRUE) {
1127 num_row_addr = spd_read(iic0_dimm_addr[dimm_num], 3);
1128 num_col_addr = spd_read(iic0_dimm_addr[dimm_num], 4);
1129 num_banks = spd_read(iic0_dimm_addr[dimm_num], 5);
1130 bank_size_id = spd_read(iic0_dimm_addr[dimm_num], 31);
1131 debug("DIMM%d: row=%d col=%d banks=%d\n", dimm_num,
1132 num_row_addr, num_col_addr, num_banks);
1135 * Set the SDRAM0_BxCR regs
1138 switch (bank_size_id) {
1140 cr |= SDRAM_BXCR_SDSZ_8;
1143 cr |= SDRAM_BXCR_SDSZ_16;
1146 cr |= SDRAM_BXCR_SDSZ_32;
1149 cr |= SDRAM_BXCR_SDSZ_64;
1152 cr |= SDRAM_BXCR_SDSZ_128;
1155 cr |= SDRAM_BXCR_SDSZ_256;
1158 cr |= SDRAM_BXCR_SDSZ_512;
1161 printf("DDR-SDRAM: DIMM %lu BxCR configuration.\n",
1163 printf("ERROR: Unsupported value for the banksize: %d.\n",
1165 printf("Replace the DIMM module with a supported DIMM.\n\n");
1166 spd_ddr_init_hang ();
1169 switch (num_col_addr) {
1171 cr |= SDRAM_BXCR_SDAM_1;
1174 cr |= SDRAM_BXCR_SDAM_2;
1177 cr |= SDRAM_BXCR_SDAM_3;
1180 cr |= SDRAM_BXCR_SDAM_4;
1183 printf("DDR-SDRAM: DIMM %lu BxCR configuration.\n",
1185 printf("ERROR: Unsupported value for number of "
1186 "column addresses: %d.\n", num_col_addr);
1187 printf("Replace the DIMM module with a supported DIMM.\n\n");
1188 spd_ddr_init_hang ();
1194 cr |= SDRAM_BXCR_SDBE;
1196 for (i = 0; i < num_banks; i++) {
1197 bank_parms[ctrl_bank_num[dimm_num]+i].bank_size_bytes =
1198 (4 << 20) * bank_size_id;
1199 bank_parms[ctrl_bank_num[dimm_num]+i].cr = cr;
1200 debug("DIMM%d-bank %d (SDRAM0_B%dCR): bank_size_bytes=%d\n",
1201 dimm_num, i, ctrl_bank_num[dimm_num]+i,
1202 bank_parms[ctrl_bank_num[dimm_num]+i].bank_size_bytes);
1207 /* Initialize sort tables */
1208 for (i = 0; i < MAXBXCR; i++) {
1209 sorted_bank_num[i] = i;
1210 sorted_bank_size[i] = bank_parms[i].bank_size_bytes;
1213 for (i = 0; i < MAXBXCR-1; i++) {
1214 largest_size = sorted_bank_size[i];
1215 largest_size_index = 255;
1217 /* Find the largest remaining value */
1218 for (j = i + 1; j < MAXBXCR; j++) {
1219 if (sorted_bank_size[j] > largest_size) {
1220 /* Save largest remaining value and its index */
1221 largest_size = sorted_bank_size[j];
1222 largest_size_index = j;
1226 if (largest_size_index != 255) {
1227 /* Swap the current and largest values */
1228 current_size_index = sorted_bank_num[largest_size_index];
1229 sorted_bank_size[largest_size_index] = sorted_bank_size[i];
1230 sorted_bank_size[i] = largest_size;
1231 sorted_bank_num[largest_size_index] = sorted_bank_num[i];
1232 sorted_bank_num[i] = current_size_index;
1236 /* Set the SDRAM0_BxCR regs thanks to sort tables */
1237 for (bx_cr_num = 0, bank_base_addr = 0; bx_cr_num < MAXBXCR; bx_cr_num++) {
1238 if (bank_parms[sorted_bank_num[bx_cr_num]].bank_size_bytes) {
1239 mtdcr(memcfga, mem_b0cr + (sorted_bank_num[bx_cr_num] << 2));
1240 temp = mfdcr(memcfgd) & ~(SDRAM_BXCR_SDBA_MASK | SDRAM_BXCR_SDSZ_MASK |
1241 SDRAM_BXCR_SDAM_MASK | SDRAM_BXCR_SDBE);
1242 temp = temp | (bank_base_addr & SDRAM_BXCR_SDBA_MASK) |
1243 bank_parms[sorted_bank_num[bx_cr_num]].cr;
1244 mtdcr(memcfgd, temp);
1245 bank_base_addr += bank_parms[sorted_bank_num[bx_cr_num]].bank_size_bytes;
1246 debug("SDRAM0_B%dCR=0x%08lx\n", sorted_bank_num[bx_cr_num], temp);
1250 return(bank_base_addr);
1252 #endif /* CONFIG_SPD_EEPROM */