2 * Copyright (c) 2005 Cisco Systems. All rights reserved.
3 * Roland Dreier <rolandd@cisco.com>
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
12 #ifndef __440SPE_PCIE_H
13 #define __440SPE_PCIE_H
15 #define mdelay(n) ({unsigned long __ms=(n); while (__ms--) udelay(1000);})
17 #define DCRN_SDR0_CFGADDR 0x00e
18 #define DCRN_SDR0_CFGDATA 0x00f
20 #define DCRN_PCIE0_BASE 0x100
21 #define DCRN_PCIE1_BASE 0x120
22 #define DCRN_PCIE2_BASE 0x140
23 #define PCIE0 DCRN_PCIE0_BASE
24 #define PCIE1 DCRN_PCIE1_BASE
25 #define PCIE2 DCRN_PCIE2_BASE
27 #define DCRN_PEGPL_CFGBAH(base) (base + 0x00)
28 #define DCRN_PEGPL_CFGBAL(base) (base + 0x01)
29 #define DCRN_PEGPL_CFGMSK(base) (base + 0x02)
30 #define DCRN_PEGPL_MSGBAH(base) (base + 0x03)
31 #define DCRN_PEGPL_MSGBAL(base) (base + 0x04)
32 #define DCRN_PEGPL_MSGMSK(base) (base + 0x05)
33 #define DCRN_PEGPL_OMR1BAH(base) (base + 0x06)
34 #define DCRN_PEGPL_OMR1BAL(base) (base + 0x07)
35 #define DCRN_PEGPL_OMR1MSKH(base) (base + 0x08)
36 #define DCRN_PEGPL_OMR1MSKL(base) (base + 0x09)
37 #define DCRN_PEGPL_REGBAH(base) (base + 0x12)
38 #define DCRN_PEGPL_REGBAL(base) (base + 0x13)
39 #define DCRN_PEGPL_REGMSK(base) (base + 0x14)
40 #define DCRN_PEGPL_SPECIAL(base) (base + 0x15)
45 #define PESDR0_PLLLCT1 0x03a0
46 #define PESDR0_PLLLCT2 0x03a1
47 #define PESDR0_PLLLCT3 0x03a2
49 #define PESDR0_UTLSET1 0x0300
50 #define PESDR0_UTLSET2 0x0301
51 #define PESDR0_DLPSET 0x0302
52 #define PESDR0_LOOP 0x0303
53 #define PESDR0_RCSSET 0x0304
54 #define PESDR0_RCSSTS 0x0305
55 #define PESDR0_HSSL0SET1 0x0306
56 #define PESDR0_HSSL0SET2 0x0307
57 #define PESDR0_HSSL0STS 0x0308
58 #define PESDR0_HSSL1SET1 0x0309
59 #define PESDR0_HSSL1SET2 0x030a
60 #define PESDR0_HSSL1STS 0x030b
61 #define PESDR0_HSSL2SET1 0x030c
62 #define PESDR0_HSSL2SET2 0x030d
63 #define PESDR0_HSSL2STS 0x030e
64 #define PESDR0_HSSL3SET1 0x030f
65 #define PESDR0_HSSL3SET2 0x0310
66 #define PESDR0_HSSL3STS 0x0311
67 #define PESDR0_HSSL4SET1 0x0312
68 #define PESDR0_HSSL4SET2 0x0313
69 #define PESDR0_HSSL4STS 0x0314
70 #define PESDR0_HSSL5SET1 0x0315
71 #define PESDR0_HSSL5SET2 0x0316
72 #define PESDR0_HSSL5STS 0x0317
73 #define PESDR0_HSSL6SET1 0x0318
74 #define PESDR0_HSSL6SET2 0x0319
75 #define PESDR0_HSSL6STS 0x031a
76 #define PESDR0_HSSL7SET1 0x031b
77 #define PESDR0_HSSL7SET2 0x031c
78 #define PESDR0_HSSL7STS 0x031d
79 #define PESDR0_HSSCTLSET 0x031e
80 #define PESDR0_LANE_ABCD 0x031f
81 #define PESDR0_LANE_EFGH 0x0320
83 #define PESDR1_UTLSET1 0x0340
84 #define PESDR1_UTLSET2 0x0341
85 #define PESDR1_DLPSET 0x0342
86 #define PESDR1_LOOP 0x0343
87 #define PESDR1_RCSSET 0x0344
88 #define PESDR1_RCSSTS 0x0345
89 #define PESDR1_HSSL0SET1 0x0346
90 #define PESDR1_HSSL0SET2 0x0347
91 #define PESDR1_HSSL0STS 0x0348
92 #define PESDR1_HSSL1SET1 0x0349
93 #define PESDR1_HSSL1SET2 0x034a
94 #define PESDR1_HSSL1STS 0x034b
95 #define PESDR1_HSSL2SET1 0x034c
96 #define PESDR1_HSSL2SET2 0x034d
97 #define PESDR1_HSSL2STS 0x034e
98 #define PESDR1_HSSL3SET1 0x034f
99 #define PESDR1_HSSL3SET2 0x0350
100 #define PESDR1_HSSL3STS 0x0351
101 #define PESDR1_HSSCTLSET 0x0352
102 #define PESDR1_LANE_ABCD 0x0353
104 #define PESDR2_UTLSET1 0x0370
105 #define PESDR2_UTLSET2 0x0371
106 #define PESDR2_DLPSET 0x0372
107 #define PESDR2_LOOP 0x0373
108 #define PESDR2_RCSSET 0x0374
109 #define PESDR2_RCSSTS 0x0375
110 #define PESDR2_HSSL0SET1 0x0376
111 #define PESDR2_HSSL0SET2 0x0377
112 #define PESDR2_HSSL0STS 0x0378
113 #define PESDR2_HSSL1SET1 0x0379
114 #define PESDR2_HSSL1SET2 0x037a
115 #define PESDR2_HSSL1STS 0x037b
116 #define PESDR2_HSSL2SET1 0x037c
117 #define PESDR2_HSSL2SET2 0x037d
118 #define PESDR2_HSSL2STS 0x037e
119 #define PESDR2_HSSL3SET1 0x037f
120 #define PESDR2_HSSL3SET2 0x0380
121 #define PESDR2_HSSL3STS 0x0381
122 #define PESDR2_HSSCTLSET 0x0382
123 #define PESDR2_LANE_ABCD 0x0383
126 * UTL register offsets
128 #define PEUTL_PBBSZ 0x20
129 #define PEUTL_OPDBSZ 0x68
130 #define PEUTL_IPHBSZ 0x70
131 #define PEUTL_IPDBSZ 0x78
132 #define PEUTL_OUTTR 0x90
133 #define PEUTL_INTR 0x98
134 #define PEUTL_PCTL 0xa0
135 #define PEUTL_RCIRQEN 0xb8
138 * Config space register offsets
140 #define PECFG_BAR0LMPA 0x210
141 #define PECFG_BAR0HMPA 0x214
142 #define PECFG_PIMEN 0x33c
143 #define PECFG_PIM0LAL 0x340
144 #define PECFG_PIM0LAH 0x344
145 #define PECFG_POM0LAL 0x380
146 #define PECFG_POM0LAH 0x384
148 #define SDR_READ(offset) ({\
149 mtdcr(DCRN_SDR0_CFGADDR, offset); \
150 mfdcr(DCRN_SDR0_CFGDATA);})
152 #define SDR_WRITE(offset, data) ({\
153 mtdcr(DCRN_SDR0_CFGADDR, offset); \
154 mtdcr(DCRN_SDR0_CFGDATA,data);})
156 int ppc440spe_init_pcie(void);
157 int ppc440spe_init_pcie_rootport(int port);
158 void yucca_setup_pcie_fpga_rootpoint(int port);
159 void ppc440spe_setup_pcie(struct pci_controller *hose, int port);
160 int yucca_pcie_card_present(int port);
161 int pcie_hose_scan(struct pci_controller *hose, int bus);
162 #endif /* __440SPE_PCIE_H */