3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * Copyright (c) 2005 Cisco Systems. All rights reserved.
6 * Roland Dreier <rolandd@cisco.com>
8 * See file CREDITS for list of people who contributed to this
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
23 #include <asm/processor.h>
24 #include <asm-ppc/io.h>
29 #include "440spe_pcie.h"
31 #if defined(CONFIG_440SPE)
32 #if defined(CONFIG_PCI)
36 PTYPE_LEGACY_ENDPOINT = 0x1,
37 PTYPE_ROOT_PORT = 0x4,
44 static int pcie_read_config(struct pci_controller *hose, unsigned int devfn,
45 int offset, int len, u32 *val) {
49 * 440SPE implements only one function per port
51 if (!((PCI_FUNC(devfn) == 0) && (PCI_DEV(devfn) == 1)))
54 devfn = PCI_BDF(0,0,0);
59 *val = in_8(hose->cfg_data + offset);
62 *val = in_le16((u16 *)(hose->cfg_data + offset));
65 *val = in_le32((u32 *)(hose->cfg_data + offset));
71 static int pcie_write_config(struct pci_controller *hose, unsigned int devfn,
72 int offset, int len, u32 val) {
75 * 440SPE implements only one function per port
77 if (!((PCI_FUNC(devfn) == 0) && (PCI_DEV(devfn) == 1)))
80 devfn = PCI_BDF(0,0,0);
85 out_8(hose->cfg_data + offset, val);
88 out_le16((u16 *)(hose->cfg_data + offset), val);
91 out_le32((u32 *)(hose->cfg_data + offset), val);
97 int pcie_read_config_byte(struct pci_controller *hose,pci_dev_t dev,int offset,u8 *val)
102 rv = pcie_read_config(hose, dev, offset, 1, &v);
107 int pcie_read_config_word(struct pci_controller *hose,pci_dev_t dev,int offset,u16 *val)
112 rv = pcie_read_config(hose, dev, offset, 2, &v);
117 int pcie_read_config_dword(struct pci_controller *hose,pci_dev_t dev,int offset,u32 *val)
122 rv = pcie_read_config(hose, dev, offset, 3, &v);
127 int pcie_write_config_byte(struct pci_controller *hose,pci_dev_t dev,int offset,u8 val)
129 return pcie_write_config(hose,(u32)dev,offset,1,val);
132 int pcie_write_config_word(struct pci_controller *hose,pci_dev_t dev,int offset,u16 val)
134 return pcie_write_config(hose,(u32)dev,offset,2,(u32 )val);
137 int pcie_write_config_dword(struct pci_controller *hose,pci_dev_t dev,int offset,u32 val)
139 return pcie_write_config(hose,(u32)dev,offset,3,(u32 )val);
142 static void ppc440spe_setup_utl(u32 port) {
144 volatile void *utl_base = NULL;
151 mtdcr(DCRN_PEGPL_REGBAH(PCIE0), 0x0000000d);
152 mtdcr(DCRN_PEGPL_REGBAL(PCIE0), 0x60000400);
153 mtdcr(DCRN_PEGPL_REGMSK(PCIE0), 0xFFFFFC01);
154 mtdcr(DCRN_PEGPL_SPECIAL(PCIE0), 0x68782800);
155 utl_base = (unsigned int *)(CFG_PCIE1_REGBASE);
159 mtdcr(DCRN_PEGPL_REGBAH(PCIE1), 0x0000000d);
160 mtdcr(DCRN_PEGPL_REGBAL(PCIE1), 0x60001400);
161 mtdcr(DCRN_PEGPL_REGMSK(PCIE1), 0xFFFFFC01);
162 mtdcr(DCRN_PEGPL_SPECIAL(PCIE1), 0x68782800);
163 utl_base = (unsigned int *)(CFG_PCIE3_REGBASE);
167 mtdcr(DCRN_PEGPL_REGBAH(PCIE2), 0x0000000d);
168 mtdcr(DCRN_PEGPL_REGBAL(PCIE2), 0x60002400);
169 mtdcr(DCRN_PEGPL_REGMSK(PCIE2), 0xFFFFFC01);
170 mtdcr(DCRN_PEGPL_SPECIAL(PCIE2), 0x68782800);
171 utl_base = (unsigned int *)(CFG_PCIE5_REGBASE);
176 * Set buffer allocations and then assert VRB and TXE.
178 out_be32(utl_base + PEUTL_OUTTR, 0x08000000);
179 out_be32(utl_base + PEUTL_INTR, 0x02000000);
180 out_be32(utl_base + PEUTL_OPDBSZ, 0x10000000);
181 out_be32(utl_base + PEUTL_PBBSZ, 0x53000000);
182 out_be32(utl_base + PEUTL_IPHBSZ, 0x08000000);
183 out_be32(utl_base + PEUTL_IPDBSZ, 0x10000000);
184 out_be32(utl_base + PEUTL_RCIRQEN, 0x00f00000);
185 out_be32(utl_base + PEUTL_PCTL, 0x8080007d);
188 static int check_error(void)
190 u32 valPE0, valPE1, valPE2;
193 /* SDR0_PEGPLLLCT1 reset */
194 if (!(valPE0 = SDR_READ(PESDR0_PLLLCT1) & 0x01000000)) {
195 printf("PCIE: SDR0_PEGPLLLCT1 reset error 0x%x\n", valPE0);
198 valPE0 = SDR_READ(PESDR0_RCSSET);
199 valPE1 = SDR_READ(PESDR1_RCSSET);
200 valPE2 = SDR_READ(PESDR2_RCSSET);
202 /* SDR0_PExRCSSET rstgu */
203 if (!(valPE0 & 0x01000000) ||
204 !(valPE1 & 0x01000000) ||
205 !(valPE2 & 0x01000000)) {
206 printf("PCIE: SDR0_PExRCSSET rstgu error\n");
210 /* SDR0_PExRCSSET rstdl */
211 if (!(valPE0 & 0x00010000) ||
212 !(valPE1 & 0x00010000) ||
213 !(valPE2 & 0x00010000)) {
214 printf("PCIE: SDR0_PExRCSSET rstdl error\n");
218 /* SDR0_PExRCSSET rstpyn */
219 if ((valPE0 & 0x00001000) ||
220 (valPE1 & 0x00001000) ||
221 (valPE2 & 0x00001000)) {
222 printf("PCIE: SDR0_PExRCSSET rstpyn error\n");
226 /* SDR0_PExRCSSET hldplb */
227 if ((valPE0 & 0x10000000) ||
228 (valPE1 & 0x10000000) ||
229 (valPE2 & 0x10000000)) {
230 printf("PCIE: SDR0_PExRCSSET hldplb error\n");
234 /* SDR0_PExRCSSET rdy */
235 if ((valPE0 & 0x00100000) ||
236 (valPE1 & 0x00100000) ||
237 (valPE2 & 0x00100000)) {
238 printf("PCIE: SDR0_PExRCSSET rdy error\n");
242 /* SDR0_PExRCSSET shutdown */
243 if ((valPE0 & 0x00000100) ||
244 (valPE1 & 0x00000100) ||
245 (valPE2 & 0x00000100)) {
246 printf("PCIE: SDR0_PExRCSSET shutdown error\n");
253 * Initialize PCI Express core
255 int ppc440spe_init_pcie(void)
259 /* Set PLL clock receiver to LVPECL */
260 SDR_WRITE(PESDR0_PLLLCT1, SDR_READ(PESDR0_PLLLCT1) | 1 << 28);
265 if (!(SDR_READ(PESDR0_PLLLCT2) & 0x10000))
267 printf("PCIE: PESDR_PLLCT2 resistance calibration failed (0x%08x)\n",
268 SDR_READ(PESDR0_PLLLCT2));
271 /* De-assert reset of PCIe PLL, wait for lock */
272 SDR_WRITE(PESDR0_PLLLCT1, SDR_READ(PESDR0_PLLLCT1) & ~(1 << 24));
276 if (!(SDR_READ(PESDR0_PLLLCT3) & 0x10000000)) {
283 printf("PCIE: VCO output not locked\n");
289 int ppc440spe_init_pcie_rootport(int port)
291 static int core_init;
292 volatile u32 val = 0;
297 if (ppc440spe_init_pcie())
302 * Initialize various parts of the PCI Express core for our port:
304 * - Set as a root port and enable max width
305 * (PXIE0 -> X8, PCIE1 and PCIE2 -> X4).
306 * - Set up UTL configuration.
307 * - Increase SERDES drive strength to levels suggested by AMCC.
308 * - De-assert RSTPYN, RSTDL and RSTGU.
310 * NOTICE for revB chip: PESDRn_UTLSET2 is not set - we leave it with
311 * default setting 0x11310000. The register has new fields,
312 * PESDRn_UTLSET2[LKINE] in particular: clearing it leads to PCIE core
317 SDR_WRITE(PESDR0_DLPSET, 1 << 24 | PTYPE_ROOT_PORT << 20 | LNKW_X8 << 12);
319 SDR_WRITE(PESDR0_UTLSET1, 0x21222222);
320 if (!ppc440spe_revB())
321 SDR_WRITE(PESDR0_UTLSET2, 0x11000000);
322 SDR_WRITE(PESDR0_HSSL0SET1, 0x35000000);
323 SDR_WRITE(PESDR0_HSSL1SET1, 0x35000000);
324 SDR_WRITE(PESDR0_HSSL2SET1, 0x35000000);
325 SDR_WRITE(PESDR0_HSSL3SET1, 0x35000000);
326 SDR_WRITE(PESDR0_HSSL4SET1, 0x35000000);
327 SDR_WRITE(PESDR0_HSSL5SET1, 0x35000000);
328 SDR_WRITE(PESDR0_HSSL6SET1, 0x35000000);
329 SDR_WRITE(PESDR0_HSSL7SET1, 0x35000000);
330 SDR_WRITE(PESDR0_RCSSET,
331 (SDR_READ(PESDR0_RCSSET) & ~(1 << 24 | 1 << 16)) | 1 << 12);
335 SDR_WRITE(PESDR1_DLPSET, 1 << 24 | PTYPE_ROOT_PORT << 20 | LNKW_X4 << 12);
336 SDR_WRITE(PESDR1_UTLSET1, 0x21222222);
337 if (!ppc440spe_revB())
338 SDR_WRITE(PESDR1_UTLSET2, 0x11000000);
339 SDR_WRITE(PESDR1_HSSL0SET1, 0x35000000);
340 SDR_WRITE(PESDR1_HSSL1SET1, 0x35000000);
341 SDR_WRITE(PESDR1_HSSL2SET1, 0x35000000);
342 SDR_WRITE(PESDR1_HSSL3SET1, 0x35000000);
343 SDR_WRITE(PESDR1_RCSSET,
344 (SDR_READ(PESDR1_RCSSET) & ~(1 << 24 | 1 << 16)) | 1 << 12);
348 SDR_WRITE(PESDR2_DLPSET, 1 << 24 | PTYPE_ROOT_PORT << 20 | LNKW_X4 << 12);
349 SDR_WRITE(PESDR2_UTLSET1, 0x21222222);
350 if (!ppc440spe_revB())
351 SDR_WRITE(PESDR2_UTLSET2, 0x11000000);
352 SDR_WRITE(PESDR2_HSSL0SET1, 0x35000000);
353 SDR_WRITE(PESDR2_HSSL1SET1, 0x35000000);
354 SDR_WRITE(PESDR2_HSSL2SET1, 0x35000000);
355 SDR_WRITE(PESDR2_HSSL3SET1, 0x35000000);
356 SDR_WRITE(PESDR2_RCSSET,
357 (SDR_READ(PESDR2_RCSSET) & ~(1 << 24 | 1 << 16)) | 1 << 12);
361 * Notice: the following delay has critical impact on device
362 * initialization - if too short (<50ms) the link doesn't get up.
367 case 0: val = SDR_READ(PESDR0_RCSSTS); break;
368 case 1: val = SDR_READ(PESDR1_RCSSTS); break;
369 case 2: val = SDR_READ(PESDR2_RCSSTS); break;
372 if (val & (1 << 20)) {
373 printf("PCIE%d: PGRST failed %08x\n", port, val);
384 val = SDR_READ(PESDR0_LOOP);
387 val = SDR_READ(PESDR1_LOOP);
390 val = SDR_READ(PESDR2_LOOP);
393 if (!(val & 0x00001000)) {
394 printf("PCIE%d: link is not up.\n", port);
399 * Setup UTL registers - but only on revA!
400 * We use default settings for revB chip.
402 if (!ppc440spe_revB())
403 ppc440spe_setup_utl(port);
406 * We map PCI Express configuration access into the 512MB regions
408 * NOTICE: revB is very strict about PLB real addressess and ranges to
409 * be mapped for config space; it seems to only work with d_nnnn_nnnn
410 * range (hangs the core upon config transaction attempts when set
411 * otherwise) while revA uses c_nnnn_nnnn.
414 * PCIE0: 0xc_4000_0000
415 * PCIE1: 0xc_8000_0000
416 * PCIE2: 0xc_c000_0000
419 * PCIE0: 0xd_0000_0000
420 * PCIE1: 0xd_2000_0000
421 * PCIE2: 0xd_4000_0000
425 if (ppc440spe_revB()) {
426 mtdcr(DCRN_PEGPL_CFGBAH(PCIE0), 0x0000000d);
427 mtdcr(DCRN_PEGPL_CFGBAL(PCIE0), 0x00000000);
430 mtdcr(DCRN_PEGPL_CFGBAH(PCIE0), 0x0000000c);
431 mtdcr(DCRN_PEGPL_CFGBAL(PCIE0), 0x40000000);
433 mtdcr(DCRN_PEGPL_CFGMSK(PCIE0), 0xe0000001); /* 512MB region, valid */
437 if (ppc440spe_revB()) {
438 mtdcr(DCRN_PEGPL_CFGBAH(PCIE1), 0x0000000d);
439 mtdcr(DCRN_PEGPL_CFGBAL(PCIE1), 0x20000000);
441 mtdcr(DCRN_PEGPL_CFGBAH(PCIE1), 0x0000000c);
442 mtdcr(DCRN_PEGPL_CFGBAL(PCIE1), 0x80000000);
444 mtdcr(DCRN_PEGPL_CFGMSK(PCIE1), 0xe0000001); /* 512MB region, valid */
448 if (ppc440spe_revB()) {
449 mtdcr(DCRN_PEGPL_CFGBAH(PCIE2), 0x0000000d);
450 mtdcr(DCRN_PEGPL_CFGBAL(PCIE2), 0x40000000);
452 mtdcr(DCRN_PEGPL_CFGBAH(PCIE2), 0x0000000c);
453 mtdcr(DCRN_PEGPL_CFGBAL(PCIE2), 0xc0000000);
455 mtdcr(DCRN_PEGPL_CFGMSK(PCIE2), 0xe0000001); /* 512MB region, valid */
460 * Check for VC0 active and assert RDY.
465 while(!(SDR_READ(PESDR0_RCSSTS) & (1 << 16))) {
467 printf("PCIE0: VC0 not active\n");
472 SDR_WRITE(PESDR0_RCSSET, SDR_READ(PESDR0_RCSSET) | 1 << 20);
475 while(!(SDR_READ(PESDR1_RCSSTS) & (1 << 16))) {
477 printf("PCIE1: VC0 not active\n");
483 SDR_WRITE(PESDR1_RCSSET, SDR_READ(PESDR1_RCSSET) | 1 << 20);
486 while(!(SDR_READ(PESDR2_RCSSTS) & (1 << 16))) {
488 printf("PCIE2: VC0 not active\n");
494 SDR_WRITE(PESDR2_RCSSET, SDR_READ(PESDR2_RCSSET) | 1 << 20);
502 void ppc440spe_setup_pcie(struct pci_controller *hose, int port)
504 volatile void *mbase = NULL;
507 pcie_read_config_byte,
508 pcie_read_config_word,
509 pcie_read_config_dword,
510 pcie_write_config_byte,
511 pcie_write_config_word,
512 pcie_write_config_dword);
516 mbase = (u32 *)CFG_PCIE0_XCFGBASE;
517 hose->cfg_data = (u8 *)CFG_PCIE0_CFGBASE;
520 mbase = (u32 *)CFG_PCIE1_XCFGBASE;
521 hose->cfg_data = (u8 *)CFG_PCIE1_CFGBASE;
524 mbase = (u32 *)CFG_PCIE2_XCFGBASE;
525 hose->cfg_data = (u8 *)CFG_PCIE2_CFGBASE;
530 * Set bus numbers on our root port
532 if (ppc440spe_revB()) {
533 out_8((u8 *)mbase + PCI_PRIMARY_BUS, 0);
534 out_8((u8 *)mbase + PCI_SECONDARY_BUS, 1);
535 out_8((u8 *)mbase + PCI_SUBORDINATE_BUS, 1);
537 out_8((u8 *)mbase + PCI_PRIMARY_BUS, 0);
538 out_8((u8 *)mbase + PCI_SECONDARY_BUS, 0);
542 * Set up outbound translation to hose->mem_space from PLB
543 * addresses at an offset of 0xd_0000_0000. We set the low
544 * bits of the mask to 11 to turn off splitting into 8
545 * subregions and to enable the outbound translation.
547 out_le32(mbase + PECFG_POM0LAH, 0x00000000);
548 out_le32(mbase + PECFG_POM0LAL, (CFG_PCIE_MEMBASE +
549 port * CFG_PCIE_MEMSIZE));
553 mtdcr(DCRN_PEGPL_OMR1BAH(PCIE0), 0x0000000d);
554 mtdcr(DCRN_PEGPL_OMR1BAL(PCIE0), CFG_PCIE_MEMBASE +
555 port * CFG_PCIE_MEMSIZE);
556 mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE0), 0x7fffffff);
557 mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE0),
558 ~(CFG_PCIE_MEMSIZE - 1) | 3);
561 mtdcr(DCRN_PEGPL_OMR1BAH(PCIE1), 0x0000000d);
562 mtdcr(DCRN_PEGPL_OMR1BAL(PCIE1), (CFG_PCIE_MEMBASE +
563 port * CFG_PCIE_MEMSIZE));
564 mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE1), 0x7fffffff);
565 mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE1),
566 ~(CFG_PCIE_MEMSIZE - 1) | 3);
569 mtdcr(DCRN_PEGPL_OMR1BAH(PCIE2), 0x0000000d);
570 mtdcr(DCRN_PEGPL_OMR1BAL(PCIE2), (CFG_PCIE_MEMBASE +
571 port * CFG_PCIE_MEMSIZE));
572 mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE2), 0x7fffffff);
573 mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE2),
574 ~(CFG_PCIE_MEMSIZE - 1) | 3);
578 /* Set up 16GB inbound memory window at 0 */
579 out_le32(mbase + PCI_BASE_ADDRESS_0, 0);
580 out_le32(mbase + PCI_BASE_ADDRESS_1, 0);
581 out_le32(mbase + PECFG_BAR0HMPA, 0x7fffffc);
582 out_le32(mbase + PECFG_BAR0LMPA, 0);
583 out_le32(mbase + PECFG_PIM0LAL, 0);
584 out_le32(mbase + PECFG_PIM0LAH, 0);
585 out_le32(mbase + PECFG_PIMEN, 0x1);
587 /* Enable I/O, Mem, and Busmaster cycles */
588 out_le16((u16 *)(mbase + PCI_COMMAND),
589 in_le16((u16 *)(mbase + PCI_COMMAND)) |
590 PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
592 #endif /* CONFIG_PCI */
593 #endif /* CONFIG_440SPE */