3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * Copyright (c) 2005 Cisco Systems. All rights reserved.
6 * Roland Dreier <rolandd@cisco.com>
8 * See file CREDITS for list of people who contributed to this
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
23 #include <asm/processor.h>
24 #include <asm-ppc/io.h>
29 #include "440spe_pcie.h"
31 #if defined(CONFIG_440SPE)
32 #if defined(CONFIG_PCI)
36 PTYPE_LEGACY_ENDPOINT = 0x1,
37 PTYPE_ROOT_PORT = 0x4,
44 static int pcie_read_config(struct pci_controller *hose, unsigned int devfn,
45 int offset, int len, u32 *val) {
49 * 440SPE implements only one function per port
51 if (!((PCI_FUNC(devfn) == 0) && (PCI_DEV(devfn) == 1)))
54 devfn = PCI_BDF(0,0,0);
59 *val = in_8(hose->cfg_data + offset);
62 *val = in_le16((u16 *)(hose->cfg_data + offset));
65 *val = in_le32((u32 *)(hose->cfg_data + offset));
71 static int pcie_write_config(struct pci_controller *hose, unsigned int devfn,
72 int offset, int len, u32 val) {
75 * 440SPE implements only one function per port
77 if (!((PCI_FUNC(devfn) == 0) && (PCI_DEV(devfn) == 1)))
80 devfn = PCI_BDF(0,0,0);
85 out_8(hose->cfg_data + offset, val);
88 out_le16((u16 *)(hose->cfg_data + offset), val);
91 out_le32((u32 *)(hose->cfg_data + offset), val);
97 int pcie_read_config_byte(struct pci_controller *hose,pci_dev_t dev,int offset,u8 *val)
102 rv = pcie_read_config(hose, dev, offset, 1, &v);
107 int pcie_read_config_word(struct pci_controller *hose,pci_dev_t dev,int offset,u16 *val)
112 rv = pcie_read_config(hose, dev, offset, 2, &v);
117 int pcie_read_config_dword(struct pci_controller *hose,pci_dev_t dev,int offset,u32 *val)
122 rv = pcie_read_config(hose, dev, offset, 3, &v);
127 int pcie_write_config_byte(struct pci_controller *hose,pci_dev_t dev,int offset,u8 val)
129 return pcie_write_config(hose,(u32)dev,offset,1,val);
132 int pcie_write_config_word(struct pci_controller *hose,pci_dev_t dev,int offset,u16 val)
134 return pcie_write_config(hose,(u32)dev,offset,2,(u32 )val);
137 int pcie_write_config_dword(struct pci_controller *hose,pci_dev_t dev,int offset,u32 val)
139 return pcie_write_config(hose,(u32)dev,offset,3,(u32 )val);
142 static void ppc440spe_setup_utl(u32 port) {
144 volatile void *utl_base = NULL;
151 mtdcr(DCRN_PEGPL_REGBAH(PCIE0), 0x0000000c);
152 mtdcr(DCRN_PEGPL_REGBAL(PCIE0), 0x20000000);
153 mtdcr(DCRN_PEGPL_REGMSK(PCIE0), 0x00007001);
154 mtdcr(DCRN_PEGPL_SPECIAL(PCIE0), 0x68782800);
158 mtdcr(DCRN_PEGPL_REGBAH(PCIE1), 0x0000000c);
159 mtdcr(DCRN_PEGPL_REGBAL(PCIE1), 0x20001000);
160 mtdcr(DCRN_PEGPL_REGMSK(PCIE1), 0x00007001);
161 mtdcr(DCRN_PEGPL_SPECIAL(PCIE1), 0x68782800);
165 mtdcr(DCRN_PEGPL_REGBAH(PCIE2), 0x0000000c);
166 mtdcr(DCRN_PEGPL_REGBAL(PCIE2), 0x20002000);
167 mtdcr(DCRN_PEGPL_REGMSK(PCIE2), 0x00007001);
168 mtdcr(DCRN_PEGPL_SPECIAL(PCIE2), 0x68782800);
171 utl_base = (unsigned int *)(CFG_PCIE_BASE + 0x1000 * port);
174 * Set buffer allocations and then assert VRB and TXE.
176 out_be32(utl_base + PEUTL_OUTTR, 0x08000000);
177 out_be32(utl_base + PEUTL_INTR, 0x02000000);
178 out_be32(utl_base + PEUTL_OPDBSZ, 0x10000000);
179 out_be32(utl_base + PEUTL_PBBSZ, 0x53000000);
180 out_be32(utl_base + PEUTL_IPHBSZ, 0x08000000);
181 out_be32(utl_base + PEUTL_IPDBSZ, 0x10000000);
182 out_be32(utl_base + PEUTL_RCIRQEN, 0x00f00000);
183 out_be32(utl_base + PEUTL_PCTL, 0x80800066);
186 static int check_error(void)
188 u32 valPE0, valPE1, valPE2;
191 /* SDR0_PEGPLLLCT1 reset */
192 if (!(valPE0 = SDR_READ(PESDR0_PLLLCT1) & 0x01000000)) {
193 printf("PCIE: SDR0_PEGPLLLCT1 reset error 0x%x\n", valPE0);
196 valPE0 = SDR_READ(PESDR0_RCSSET);
197 valPE1 = SDR_READ(PESDR1_RCSSET);
198 valPE2 = SDR_READ(PESDR2_RCSSET);
200 /* SDR0_PExRCSSET rstgu */
201 if (!(valPE0 & 0x01000000) ||
202 !(valPE1 & 0x01000000) ||
203 !(valPE2 & 0x01000000)) {
204 printf("PCIE: SDR0_PExRCSSET rstgu error\n");
208 /* SDR0_PExRCSSET rstdl */
209 if (!(valPE0 & 0x00010000) ||
210 !(valPE1 & 0x00010000) ||
211 !(valPE2 & 0x00010000)) {
212 printf("PCIE: SDR0_PExRCSSET rstdl error\n");
216 /* SDR0_PExRCSSET rstpyn */
217 if ((valPE0 & 0x00001000) ||
218 (valPE1 & 0x00001000) ||
219 (valPE2 & 0x00001000)) {
220 printf("PCIE: SDR0_PExRCSSET rstpyn error\n");
224 /* SDR0_PExRCSSET hldplb */
225 if ((valPE0 & 0x10000000) ||
226 (valPE1 & 0x10000000) ||
227 (valPE2 & 0x10000000)) {
228 printf("PCIE: SDR0_PExRCSSET hldplb error\n");
232 /* SDR0_PExRCSSET rdy */
233 if ((valPE0 & 0x00100000) ||
234 (valPE1 & 0x00100000) ||
235 (valPE2 & 0x00100000)) {
236 printf("PCIE: SDR0_PExRCSSET rdy error\n");
240 /* SDR0_PExRCSSET shutdown */
241 if ((valPE0 & 0x00000100) ||
242 (valPE1 & 0x00000100) ||
243 (valPE2 & 0x00000100)) {
244 printf("PCIE: SDR0_PExRCSSET shutdown error\n");
251 * Initialize PCI Express core
253 int ppc440spe_init_pcie(void)
257 /* Set PLL clock receiver to LVPECL */
258 SDR_WRITE(PESDR0_PLLLCT1, SDR_READ(PESDR0_PLLLCT1) | 1 << 28);
263 if (!(SDR_READ(PESDR0_PLLLCT2) & 0x10000))
265 printf("PCIE: PESDR_PLLCT2 resistance calibration failed (0x%08x)\n",
266 SDR_READ(PESDR0_PLLLCT2));
269 /* De-assert reset of PCIe PLL, wait for lock */
270 SDR_WRITE(PESDR0_PLLLCT1, SDR_READ(PESDR0_PLLLCT1) & ~(1 << 24));
274 if (!(SDR_READ(PESDR0_PLLLCT3) & 0x10000000)) {
281 printf("PCIE: VCO output not locked\n");
288 * Yucca board as End point and root point setup
290 * testing inbound and out bound windows
292 * YUCCA board can be plugged into another yucca board or you can get PCI-E
293 * cable which can be used to setup loop back from one port to another port.
294 * Please rememeber that unless there is a endpoint plugged in to root port it
295 * will not initialize. It is the same in case of endpoint , unless there is
296 * root port attached it will not initialize.
298 * In this release of software all the PCI-E ports are configured as either
299 * endpoint or rootpoint.In future we will have support for selective ports
300 * setup as endpoint and root point in single board.
302 * Once your board came up as root point , you can verify by reading
303 * /proc/bus/pci/devices. Where you can see the configuration registers
304 * of end point device attached to the port.
306 * Enpoint cofiguration can be verified by connecting Yucca board to any
307 * host or another yucca board. Then try to scan the device. In case of
308 * linux use "lspci" or appripriate os command.
310 * How do I verify the inbound and out bound windows ?(yucca to yucca)
311 * in this configuration inbound and outbound windows are setup to access
312 * sram memroy area. SRAM is at 0x4 0000 0000 , on PLB bus. This address
313 * is mapped at 0x90000000. From u-boot prompt write data 0xb000 0000,
314 * This is waere your POM(PLB out bound memory window) mapped. then
315 * read the data from other yucca board's u-boot prompt at address
316 * 0x9000 0000(SRAM). Data should match.
317 * In case of inbound , write data to u-boot command prompt at 0xb000 0000
318 * which is mapped to 0x4 0000 0000. Now on rootpoint yucca u-boot prompt check
319 * data at 0x9000 0000(SRAM).Data should match.
321 int ppc440spe_init_pcie_rootport(int port)
323 static int core_init;
324 volatile u32 val = 0;
329 if (ppc440spe_init_pcie())
334 * Initialize various parts of the PCI Express core for our port:
336 * - Set as a root port and enable max width
337 * (PXIE0 -> X8, PCIE1 and PCIE2 -> X4).
338 * - Set up UTL configuration.
339 * - Increase SERDES drive strength to levels suggested by AMCC.
340 * - De-assert RSTPYN, RSTDL and RSTGU.
342 * NOTICE for revB chip: PESDRn_UTLSET2 is not set - we leave it with
343 * default setting 0x11310000. The register has new fields,
344 * PESDRn_UTLSET2[LKINE] in particular: clearing it leads to PCIE core
349 SDR_WRITE(PESDR0_DLPSET, 1 << 24 | PTYPE_ROOT_PORT << 20 | LNKW_X8 << 12);
351 SDR_WRITE(PESDR0_UTLSET1, 0x21222222);
352 if (!ppc440spe_revB())
353 SDR_WRITE(PESDR0_UTLSET2, 0x11000000);
354 SDR_WRITE(PESDR0_HSSL0SET1, 0x35000000);
355 SDR_WRITE(PESDR0_HSSL1SET1, 0x35000000);
356 SDR_WRITE(PESDR0_HSSL2SET1, 0x35000000);
357 SDR_WRITE(PESDR0_HSSL3SET1, 0x35000000);
358 SDR_WRITE(PESDR0_HSSL4SET1, 0x35000000);
359 SDR_WRITE(PESDR0_HSSL5SET1, 0x35000000);
360 SDR_WRITE(PESDR0_HSSL6SET1, 0x35000000);
361 SDR_WRITE(PESDR0_HSSL7SET1, 0x35000000);
362 SDR_WRITE(PESDR0_RCSSET,
363 (SDR_READ(PESDR0_RCSSET) & ~(1 << 24 | 1 << 16)) | 1 << 12);
367 SDR_WRITE(PESDR1_DLPSET, 1 << 24 | PTYPE_ROOT_PORT << 20 | LNKW_X4 << 12);
368 SDR_WRITE(PESDR1_UTLSET1, 0x21222222);
369 if (!ppc440spe_revB())
370 SDR_WRITE(PESDR1_UTLSET2, 0x11000000);
371 SDR_WRITE(PESDR1_HSSL0SET1, 0x35000000);
372 SDR_WRITE(PESDR1_HSSL1SET1, 0x35000000);
373 SDR_WRITE(PESDR1_HSSL2SET1, 0x35000000);
374 SDR_WRITE(PESDR1_HSSL3SET1, 0x35000000);
375 SDR_WRITE(PESDR1_RCSSET,
376 (SDR_READ(PESDR1_RCSSET) & ~(1 << 24 | 1 << 16)) | 1 << 12);
380 SDR_WRITE(PESDR2_DLPSET, 1 << 24 | PTYPE_ROOT_PORT << 20 | LNKW_X4 << 12);
381 SDR_WRITE(PESDR2_UTLSET1, 0x21222222);
382 if (!ppc440spe_revB())
383 SDR_WRITE(PESDR2_UTLSET2, 0x11000000);
384 SDR_WRITE(PESDR2_HSSL0SET1, 0x35000000);
385 SDR_WRITE(PESDR2_HSSL1SET1, 0x35000000);
386 SDR_WRITE(PESDR2_HSSL2SET1, 0x35000000);
387 SDR_WRITE(PESDR2_HSSL3SET1, 0x35000000);
388 SDR_WRITE(PESDR2_RCSSET,
389 (SDR_READ(PESDR2_RCSSET) & ~(1 << 24 | 1 << 16)) | 1 << 12);
393 * Notice: the following delay has critical impact on device
394 * initialization - if too short (<50ms) the link doesn't get up.
400 val = SDR_READ(PESDR0_RCSSTS);
403 val = SDR_READ(PESDR1_RCSSTS);
406 val = SDR_READ(PESDR2_RCSSTS);
410 if (val & (1 << 20)) {
411 printf("PCIE%d: PGRST failed %08x\n", port, val);
421 val = SDR_READ(PESDR0_LOOP);
424 val = SDR_READ(PESDR1_LOOP);
427 val = SDR_READ(PESDR2_LOOP);
430 if (!(val & 0x00001000)) {
431 printf("PCIE%d: link is not up.\n", port);
436 * Setup UTL registers - but only on revA!
437 * We use default settings for revB chip.
439 if (!ppc440spe_revB())
440 ppc440spe_setup_utl(port);
443 * We map PCI Express configuration access into the 512MB regions
445 * NOTICE: revB is very strict about PLB real addressess and ranges to
446 * be mapped for config space; it seems to only work with d_nnnn_nnnn
447 * range (hangs the core upon config transaction attempts when set
448 * otherwise) while revA uses c_nnnn_nnnn.
451 * PCIE0: 0xc_4000_0000
452 * PCIE1: 0xc_8000_0000
453 * PCIE2: 0xc_c000_0000
456 * PCIE0: 0xd_0000_0000
457 * PCIE1: 0xd_2000_0000
458 * PCIE2: 0xd_4000_0000
463 if (ppc440spe_revB()) {
464 mtdcr(DCRN_PEGPL_CFGBAH(PCIE0), 0x0000000d);
465 mtdcr(DCRN_PEGPL_CFGBAL(PCIE0), 0x00000000);
468 mtdcr(DCRN_PEGPL_CFGBAH(PCIE0), 0x0000000c);
469 mtdcr(DCRN_PEGPL_CFGBAL(PCIE0), 0x40000000);
471 mtdcr(DCRN_PEGPL_CFGMSK(PCIE0), 0xe0000001); /* 512MB region, valid */
475 if (ppc440spe_revB()) {
476 mtdcr(DCRN_PEGPL_CFGBAH(PCIE1), 0x0000000d);
477 mtdcr(DCRN_PEGPL_CFGBAL(PCIE1), 0x20000000);
479 mtdcr(DCRN_PEGPL_CFGBAH(PCIE1), 0x0000000c);
480 mtdcr(DCRN_PEGPL_CFGBAL(PCIE1), 0x80000000);
482 mtdcr(DCRN_PEGPL_CFGMSK(PCIE1), 0xe0000001); /* 512MB region, valid */
486 if (ppc440spe_revB()) {
487 mtdcr(DCRN_PEGPL_CFGBAH(PCIE2), 0x0000000d);
488 mtdcr(DCRN_PEGPL_CFGBAL(PCIE2), 0x40000000);
490 mtdcr(DCRN_PEGPL_CFGBAH(PCIE2), 0x0000000c);
491 mtdcr(DCRN_PEGPL_CFGBAL(PCIE2), 0xc0000000);
493 mtdcr(DCRN_PEGPL_CFGMSK(PCIE2), 0xe0000001); /* 512MB region, valid */
498 * Check for VC0 active and assert RDY.
503 while(!(SDR_READ(PESDR0_RCSSTS) & (1 << 16))) {
505 printf("PCIE0: VC0 not active\n");
510 SDR_WRITE(PESDR0_RCSSET, SDR_READ(PESDR0_RCSSET) | 1 << 20);
513 while(!(SDR_READ(PESDR1_RCSSTS) & (1 << 16))) {
515 printf("PCIE1: VC0 not active\n");
521 SDR_WRITE(PESDR1_RCSSET, SDR_READ(PESDR1_RCSSET) | 1 << 20);
524 while(!(SDR_READ(PESDR2_RCSSTS) & (1 << 16))) {
526 printf("PCIE2: VC0 not active\n");
532 SDR_WRITE(PESDR2_RCSSET, SDR_READ(PESDR2_RCSSET) | 1 << 20);
540 int ppc440spe_init_pcie_endport(int port)
542 static int core_init;
543 volatile u32 val = 0;
548 if (ppc440spe_init_pcie())
553 * Initialize various parts of the PCI Express core for our port:
555 * - Set as a end port and enable max width
556 * (PXIE0 -> X8, PCIE1 and PCIE2 -> X4).
557 * - Set up UTL configuration.
558 * - Increase SERDES drive strength to levels suggested by AMCC.
559 * - De-assert RSTPYN, RSTDL and RSTGU.
561 * NOTICE for revB chip: PESDRn_UTLSET2 is not set - we leave it with
562 * default setting 0x11310000. The register has new fields,
563 * PESDRn_UTLSET2[LKINE] in particular: clearing it leads to PCIE core
568 SDR_WRITE(PESDR0_DLPSET, 1 << 24 | PTYPE_LEGACY_ENDPOINT << 20 | LNKW_X8 << 12);
570 SDR_WRITE(PESDR0_UTLSET1, 0x20222222);
571 if (!ppc440spe_revB())
572 SDR_WRITE(PESDR0_UTLSET2, 0x11000000);
573 SDR_WRITE(PESDR0_HSSL0SET1, 0x35000000);
574 SDR_WRITE(PESDR0_HSSL1SET1, 0x35000000);
575 SDR_WRITE(PESDR0_HSSL2SET1, 0x35000000);
576 SDR_WRITE(PESDR0_HSSL3SET1, 0x35000000);
577 SDR_WRITE(PESDR0_HSSL4SET1, 0x35000000);
578 SDR_WRITE(PESDR0_HSSL5SET1, 0x35000000);
579 SDR_WRITE(PESDR0_HSSL6SET1, 0x35000000);
580 SDR_WRITE(PESDR0_HSSL7SET1, 0x35000000);
581 SDR_WRITE(PESDR0_RCSSET,
582 (SDR_READ(PESDR0_RCSSET) & ~(1 << 24 | 1 << 16)) | 1 << 12);
586 SDR_WRITE(PESDR1_DLPSET, 1 << 24 | PTYPE_LEGACY_ENDPOINT << 20 | LNKW_X4 << 12);
587 SDR_WRITE(PESDR1_UTLSET1, 0x20222222);
588 if (!ppc440spe_revB())
589 SDR_WRITE(PESDR1_UTLSET2, 0x11000000);
590 SDR_WRITE(PESDR1_HSSL0SET1, 0x35000000);
591 SDR_WRITE(PESDR1_HSSL1SET1, 0x35000000);
592 SDR_WRITE(PESDR1_HSSL2SET1, 0x35000000);
593 SDR_WRITE(PESDR1_HSSL3SET1, 0x35000000);
594 SDR_WRITE(PESDR1_RCSSET,
595 (SDR_READ(PESDR1_RCSSET) & ~(1 << 24 | 1 << 16)) | 1 << 12);
599 SDR_WRITE(PESDR2_DLPSET, 1 << 24 | PTYPE_LEGACY_ENDPOINT << 20 | LNKW_X4 << 12);
600 SDR_WRITE(PESDR2_UTLSET1, 0x20222222);
601 if (!ppc440spe_revB())
602 SDR_WRITE(PESDR2_UTLSET2, 0x11000000);
603 SDR_WRITE(PESDR2_HSSL0SET1, 0x35000000);
604 SDR_WRITE(PESDR2_HSSL1SET1, 0x35000000);
605 SDR_WRITE(PESDR2_HSSL2SET1, 0x35000000);
606 SDR_WRITE(PESDR2_HSSL3SET1, 0x35000000);
607 SDR_WRITE(PESDR2_RCSSET,
608 (SDR_READ(PESDR2_RCSSET) & ~(1 << 24 | 1 << 16)) | 1 << 12);
612 * Notice: the following delay has critical impact on device
613 * initialization - if too short (<50ms) the link doesn't get up.
618 case 0: val = SDR_READ(PESDR0_RCSSTS); break;
619 case 1: val = SDR_READ(PESDR1_RCSSTS); break;
620 case 2: val = SDR_READ(PESDR2_RCSSTS); break;
623 if (val & (1 << 20)) {
624 printf("PCIE%d: PGRST failed %08x\n", port, val);
635 val = SDR_READ(PESDR0_LOOP);
638 val = SDR_READ(PESDR1_LOOP);
641 val = SDR_READ(PESDR2_LOOP);
644 if (!(val & 0x00001000)) {
645 printf("PCIE%d: link is not up.\n", port);
650 * Setup UTL registers - but only on revA!
651 * We use default settings for revB chip.
653 if (!ppc440spe_revB())
654 ppc440spe_setup_utl(port);
657 * We map PCI Express configuration access into the 512MB regions
659 * NOTICE: revB is very strict about PLB real addressess and ranges to
660 * be mapped for config space; it seems to only work with d_nnnn_nnnn
661 * range (hangs the core upon config transaction attempts when set
662 * otherwise) while revA uses c_nnnn_nnnn.
665 * PCIE0: 0xc_4000_0000
666 * PCIE1: 0xc_8000_0000
667 * PCIE2: 0xc_c000_0000
670 * PCIE0: 0xd_0000_0000
671 * PCIE1: 0xd_2000_0000
672 * PCIE2: 0xd_4000_0000
676 if (ppc440spe_revB()) {
677 mtdcr(DCRN_PEGPL_CFGBAH(PCIE0), 0x0000000d);
678 mtdcr(DCRN_PEGPL_CFGBAL(PCIE0), 0x00000000);
681 mtdcr(DCRN_PEGPL_CFGBAH(PCIE0), 0x0000000c);
682 mtdcr(DCRN_PEGPL_CFGBAL(PCIE0), 0x40000000);
684 mtdcr(DCRN_PEGPL_CFGMSK(PCIE0), 0xe0000001); /* 512MB region, valid */
688 if (ppc440spe_revB()) {
689 mtdcr(DCRN_PEGPL_CFGBAH(PCIE1), 0x0000000d);
690 mtdcr(DCRN_PEGPL_CFGBAL(PCIE1), 0x20000000);
692 mtdcr(DCRN_PEGPL_CFGBAH(PCIE1), 0x0000000c);
693 mtdcr(DCRN_PEGPL_CFGBAL(PCIE1), 0x80000000);
695 mtdcr(DCRN_PEGPL_CFGMSK(PCIE1), 0xe0000001); /* 512MB region, valid */
699 if (ppc440spe_revB()) {
700 mtdcr(DCRN_PEGPL_CFGBAH(PCIE2), 0x0000000d);
701 mtdcr(DCRN_PEGPL_CFGBAL(PCIE2), 0x40000000);
703 mtdcr(DCRN_PEGPL_CFGBAH(PCIE2), 0x0000000c);
704 mtdcr(DCRN_PEGPL_CFGBAL(PCIE2), 0xc0000000);
706 mtdcr(DCRN_PEGPL_CFGMSK(PCIE2), 0xe0000001); /* 512MB region, valid */
711 * Check for VC0 active and assert RDY.
716 while(!(SDR_READ(PESDR0_RCSSTS) & (1 << 16))) {
718 printf("PCIE0: VC0 not active\n");
723 SDR_WRITE(PESDR0_RCSSET, SDR_READ(PESDR0_RCSSET) | 1 << 20);
726 while(!(SDR_READ(PESDR1_RCSSTS) & (1 << 16))) {
728 printf("PCIE1: VC0 not active\n");
734 SDR_WRITE(PESDR1_RCSSET, SDR_READ(PESDR1_RCSSET) | 1 << 20);
737 while(!(SDR_READ(PESDR2_RCSSTS) & (1 << 16))) {
739 printf("PCIE2: VC0 not active\n");
745 SDR_WRITE(PESDR2_RCSSET, SDR_READ(PESDR2_RCSSET) | 1 << 20);
753 void ppc440spe_setup_pcie_rootpoint(struct pci_controller *hose, int port)
755 volatile void *mbase = NULL;
756 volatile void *rmbase = NULL;
759 pcie_read_config_byte,
760 pcie_read_config_word,
761 pcie_read_config_dword,
762 pcie_write_config_byte,
763 pcie_write_config_word,
764 pcie_write_config_dword);
768 mbase = (u32 *)CFG_PCIE0_XCFGBASE;
769 rmbase = (u32 *)CFG_PCIE0_CFGBASE;
770 hose->cfg_data = (u8 *)CFG_PCIE0_CFGBASE;
773 mbase = (u32 *)CFG_PCIE1_XCFGBASE;
774 rmbase = (u32 *)CFG_PCIE1_CFGBASE;
775 hose->cfg_data = (u8 *)CFG_PCIE1_CFGBASE;
778 mbase = (u32 *)CFG_PCIE2_XCFGBASE;
779 rmbase = (u32 *)CFG_PCIE2_CFGBASE;
780 hose->cfg_data = (u8 *)CFG_PCIE2_CFGBASE;
785 * Set bus numbers on our root port
787 out_8((u8 *)mbase + PCI_PRIMARY_BUS, 0);
788 out_8((u8 *)mbase + PCI_SECONDARY_BUS, 1);
789 out_8((u8 *)mbase + PCI_SUBORDINATE_BUS, 1);
792 * Set up outbound translation to hose->mem_space from PLB
793 * addresses at an offset of 0xd_0000_0000. We set the low
794 * bits of the mask to 11 to turn off splitting into 8
795 * subregions and to enable the outbound translation.
797 out_le32(mbase + PECFG_POM0LAH, 0x00000000);
798 out_le32(mbase + PECFG_POM0LAL, 0x00000000);
802 mtdcr(DCRN_PEGPL_OMR1BAH(PCIE0), 0x0000000d);
803 mtdcr(DCRN_PEGPL_OMR1BAL(PCIE0), CFG_PCIE_MEMBASE +
804 port * CFG_PCIE_MEMSIZE);
805 mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE0), 0x7fffffff);
806 mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE0),
807 ~(CFG_PCIE_MEMSIZE - 1) | 3);
810 mtdcr(DCRN_PEGPL_OMR1BAH(PCIE1), 0x0000000d);
811 mtdcr(DCRN_PEGPL_OMR1BAL(PCIE1), (CFG_PCIE_MEMBASE +
812 port * CFG_PCIE_MEMSIZE));
813 mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE1), 0x7fffffff);
814 mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE1),
815 ~(CFG_PCIE_MEMSIZE - 1) | 3);
818 mtdcr(DCRN_PEGPL_OMR1BAH(PCIE2), 0x0000000d);
819 mtdcr(DCRN_PEGPL_OMR1BAL(PCIE2), (CFG_PCIE_MEMBASE +
820 port * CFG_PCIE_MEMSIZE));
821 mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE2), 0x7fffffff);
822 mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE2),
823 ~(CFG_PCIE_MEMSIZE - 1) | 3);
827 /* Set up 16GB inbound memory window at 0 */
828 out_le32(mbase + PCI_BASE_ADDRESS_0, 0);
829 out_le32(mbase + PCI_BASE_ADDRESS_1, 0);
830 out_le32(mbase + PECFG_BAR0HMPA, 0x7fffffc);
831 out_le32(mbase + PECFG_BAR0LMPA, 0);
833 out_le32(mbase + PECFG_PIM01SAH, 0xffff0000);
834 out_le32(mbase + PECFG_PIM01SAL, 0x00000000);
835 out_le32(mbase + PECFG_PIM0LAL, 0);
836 out_le32(mbase + PECFG_PIM0LAH, 0);
837 out_le32(mbase + PECFG_PIM1LAL, 0x00000000);
838 out_le32(mbase + PECFG_PIM1LAH, 0x00000004);
839 out_le32(mbase + PECFG_PIMEN, 0x1);
841 /* Enable I/O, Mem, and Busmaster cycles */
842 out_le16((u16 *)(mbase + PCI_COMMAND),
843 in_le16((u16 *)(mbase + PCI_COMMAND)) |
844 PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
845 printf("PCIE:%d successfully set as rootpoint\n",port);
848 int ppc440spe_setup_pcie_endpoint(struct pci_controller *hose, int port)
850 volatile void *mbase = NULL;
854 pcie_read_config_byte,
855 pcie_read_config_word,
856 pcie_read_config_dword,
857 pcie_write_config_byte,
858 pcie_write_config_word,
859 pcie_write_config_dword);
863 mbase = (u32 *)CFG_PCIE0_XCFGBASE;
864 hose->cfg_data = (u8 *)CFG_PCIE0_CFGBASE;
867 mbase = (u32 *)CFG_PCIE1_XCFGBASE;
868 hose->cfg_data = (u8 *)CFG_PCIE1_CFGBASE;
871 mbase = (u32 *)CFG_PCIE2_XCFGBASE;
872 hose->cfg_data = (u8 *)CFG_PCIE2_CFGBASE;
877 * Set up outbound translation to hose->mem_space from PLB
878 * addresses at an offset of 0xd_0000_0000. We set the low
879 * bits of the mask to 11 to turn off splitting into 8
880 * subregions and to enable the outbound translation.
882 out_le32(mbase + PECFG_POM0LAH, 0x00001ff8);
883 out_le32(mbase + PECFG_POM0LAL, 0x00001000);
887 mtdcr(DCRN_PEGPL_OMR1BAH(PCIE0), 0x0000000d);
888 mtdcr(DCRN_PEGPL_OMR1BAL(PCIE0), CFG_PCIE_MEMBASE +
889 port * CFG_PCIE_MEMSIZE);
890 mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE0), 0x7fffffff);
891 mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE0),
892 ~(CFG_PCIE_MEMSIZE - 1) | 3);
895 mtdcr(DCRN_PEGPL_OMR1BAH(PCIE1), 0x0000000d);
896 mtdcr(DCRN_PEGPL_OMR1BAL(PCIE1), (CFG_PCIE_MEMBASE +
897 port * CFG_PCIE_MEMSIZE));
898 mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE1), 0x7fffffff);
899 mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE1),
900 ~(CFG_PCIE_MEMSIZE - 1) | 3);
903 mtdcr(DCRN_PEGPL_OMR1BAH(PCIE2), 0x0000000d);
904 mtdcr(DCRN_PEGPL_OMR1BAL(PCIE2), (CFG_PCIE_MEMBASE +
905 port * CFG_PCIE_MEMSIZE));
906 mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE2), 0x7fffffff);
907 mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE2),
908 ~(CFG_PCIE_MEMSIZE - 1) | 3);
912 /* Set up 16GB inbound memory window at 0 */
913 out_le32(mbase + PCI_BASE_ADDRESS_0, 0);
914 out_le32(mbase + PCI_BASE_ADDRESS_1, 0);
915 out_le32(mbase + PECFG_BAR0HMPA, 0x7fffffc);
916 out_le32(mbase + PECFG_BAR0LMPA, 0);
917 out_le32(mbase + PECFG_PIM0LAL, 0x00000000);
918 out_le32(mbase + PECFG_PIM0LAH, 0x00000004); /* pointing to SRAM */
919 out_le32(mbase + PECFG_PIMEN, 0x1);
921 /* Enable I/O, Mem, and Busmaster cycles */
922 out_le16((u16 *)(mbase + PCI_COMMAND),
923 in_le16((u16 *)(mbase + PCI_COMMAND)) |
924 PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
925 out_le16(mbase + 0x200,0xcaad); /* Setting vendor ID */
926 out_le16(mbase + 0x202,0xfeed); /* Setting device ID */
930 while (!(SDR_READ(PESDR0_RCSSTS) & (1 << 8))) {
932 printf("PCIE0: BMEN is not active\n");
939 while (!(SDR_READ(PESDR1_RCSSTS) & (1 << 8))) {
941 printf("PCIE1: BMEN is not active\n");
948 while (!(SDR_READ(PESDR2_RCSSTS) & (1 << 8))) {
950 printf("PCIE2: BMEN is not active\n");
957 printf("PCIE:%d successfully set as endpoint\n",port);
961 #endif /* CONFIG_PCI */
962 #endif /* CONFIG_440SPE */