2 * (C) Copyright 2006 - 2007
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * Copyright (c) 2005 Cisco Systems. All rights reserved.
6 * Roland Dreier <rolandd@cisco.com>
8 * See file CREDITS for list of people who contributed to this
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
23 #include <asm/processor.h>
24 #include <asm-ppc/io.h>
29 #if defined(CONFIG_440SPE) && defined(CONFIG_PCI)
31 #include "440spe_pcie.h"
35 PTYPE_LEGACY_ENDPOINT = 0x1,
36 PTYPE_ROOT_PORT = 0x4,
43 static inline int pcie_in_8(const volatile unsigned char __iomem *addr)
47 PCIE_IN(lbzx, ret, addr);
52 static inline int pcie_in_le16(const volatile unsigned short __iomem *addr)
56 PCIE_IN(lhbrx, ret, addr)
61 static inline unsigned pcie_in_le32(const volatile unsigned __iomem *addr)
65 PCIE_IN(lwbrx, ret, addr);
71 static int pcie_read_config(struct pci_controller *hose, unsigned int devfn,
72 int offset, int len, u32 *val) {
76 * 440SPE implements only one function per port
78 if (!((PCI_FUNC(devfn) == 0) && (PCI_DEV(devfn) == 1)))
81 devfn = PCI_BDF(0,0,0);
86 *val = pcie_in_8(hose->cfg_data + offset);
89 *val = pcie_in_le16((u16 *)(hose->cfg_data + offset));
92 *val = pcie_in_le32((u32*)(hose->cfg_data + offset));
98 static int pcie_write_config(struct pci_controller *hose, unsigned int devfn,
99 int offset, int len, u32 val) {
102 * 440SPE implements only one function per port
104 if (!((PCI_FUNC(devfn) == 0) && (PCI_DEV(devfn) == 1)))
107 devfn = PCI_BDF(0,0,0);
108 offset += devfn << 4;
112 out_8(hose->cfg_data + offset, val);
115 out_le16((u16 *)(hose->cfg_data + offset), val);
118 out_le32((u32 *)(hose->cfg_data + offset), val);
124 int pcie_read_config_byte(struct pci_controller *hose,pci_dev_t dev,int offset,u8 *val)
129 rv = pcie_read_config(hose, dev, offset, 1, &v);
134 int pcie_read_config_word(struct pci_controller *hose,pci_dev_t dev,int offset,u16 *val)
139 rv = pcie_read_config(hose, dev, offset, 2, &v);
144 int pcie_read_config_dword(struct pci_controller *hose,pci_dev_t dev,int offset,u32 *val)
149 rv = pcie_read_config(hose, dev, offset, 3, &v);
154 int pcie_write_config_byte(struct pci_controller *hose,pci_dev_t dev,int offset,u8 val)
156 return pcie_write_config(hose,(u32)dev,offset,1,val);
159 int pcie_write_config_word(struct pci_controller *hose,pci_dev_t dev,int offset,u16 val)
161 return pcie_write_config(hose,(u32)dev,offset,2,(u32 )val);
164 int pcie_write_config_dword(struct pci_controller *hose,pci_dev_t dev,int offset,u32 val)
166 return pcie_write_config(hose,(u32)dev,offset,3,(u32 )val);
169 static void ppc440spe_setup_utl(u32 port) {
171 volatile void *utl_base = NULL;
178 mtdcr(DCRN_PEGPL_REGBAH(PCIE0), 0x0000000c);
179 mtdcr(DCRN_PEGPL_REGBAL(PCIE0), 0x20000000);
180 mtdcr(DCRN_PEGPL_REGMSK(PCIE0), 0x00007001);
181 mtdcr(DCRN_PEGPL_SPECIAL(PCIE0), 0x68782800);
185 mtdcr(DCRN_PEGPL_REGBAH(PCIE1), 0x0000000c);
186 mtdcr(DCRN_PEGPL_REGBAL(PCIE1), 0x20001000);
187 mtdcr(DCRN_PEGPL_REGMSK(PCIE1), 0x00007001);
188 mtdcr(DCRN_PEGPL_SPECIAL(PCIE1), 0x68782800);
192 mtdcr(DCRN_PEGPL_REGBAH(PCIE2), 0x0000000c);
193 mtdcr(DCRN_PEGPL_REGBAL(PCIE2), 0x20002000);
194 mtdcr(DCRN_PEGPL_REGMSK(PCIE2), 0x00007001);
195 mtdcr(DCRN_PEGPL_SPECIAL(PCIE2), 0x68782800);
198 utl_base = (unsigned int *)(CFG_PCIE_BASE + 0x1000 * port);
201 * Set buffer allocations and then assert VRB and TXE.
203 out_be32(utl_base + PEUTL_OUTTR, 0x08000000);
204 out_be32(utl_base + PEUTL_INTR, 0x02000000);
205 out_be32(utl_base + PEUTL_OPDBSZ, 0x10000000);
206 out_be32(utl_base + PEUTL_PBBSZ, 0x53000000);
207 out_be32(utl_base + PEUTL_IPHBSZ, 0x08000000);
208 out_be32(utl_base + PEUTL_IPDBSZ, 0x10000000);
209 out_be32(utl_base + PEUTL_RCIRQEN, 0x00f00000);
210 out_be32(utl_base + PEUTL_PCTL, 0x80800066);
213 static int check_error(void)
215 u32 valPE0, valPE1, valPE2;
218 /* SDR0_PEGPLLLCT1 reset */
219 if (!(valPE0 = SDR_READ(PESDR0_PLLLCT1) & 0x01000000)) {
220 printf("PCIE: SDR0_PEGPLLLCT1 reset error 0x%x\n", valPE0);
223 valPE0 = SDR_READ(PESDR0_RCSSET);
224 valPE1 = SDR_READ(PESDR1_RCSSET);
225 valPE2 = SDR_READ(PESDR2_RCSSET);
227 /* SDR0_PExRCSSET rstgu */
228 if (!(valPE0 & 0x01000000) ||
229 !(valPE1 & 0x01000000) ||
230 !(valPE2 & 0x01000000)) {
231 printf("PCIE: SDR0_PExRCSSET rstgu error\n");
235 /* SDR0_PExRCSSET rstdl */
236 if (!(valPE0 & 0x00010000) ||
237 !(valPE1 & 0x00010000) ||
238 !(valPE2 & 0x00010000)) {
239 printf("PCIE: SDR0_PExRCSSET rstdl error\n");
243 /* SDR0_PExRCSSET rstpyn */
244 if ((valPE0 & 0x00001000) ||
245 (valPE1 & 0x00001000) ||
246 (valPE2 & 0x00001000)) {
247 printf("PCIE: SDR0_PExRCSSET rstpyn error\n");
251 /* SDR0_PExRCSSET hldplb */
252 if ((valPE0 & 0x10000000) ||
253 (valPE1 & 0x10000000) ||
254 (valPE2 & 0x10000000)) {
255 printf("PCIE: SDR0_PExRCSSET hldplb error\n");
259 /* SDR0_PExRCSSET rdy */
260 if ((valPE0 & 0x00100000) ||
261 (valPE1 & 0x00100000) ||
262 (valPE2 & 0x00100000)) {
263 printf("PCIE: SDR0_PExRCSSET rdy error\n");
267 /* SDR0_PExRCSSET shutdown */
268 if ((valPE0 & 0x00000100) ||
269 (valPE1 & 0x00000100) ||
270 (valPE2 & 0x00000100)) {
271 printf("PCIE: SDR0_PExRCSSET shutdown error\n");
278 * Initialize PCI Express core
280 int ppc440spe_init_pcie(void)
284 /* Set PLL clock receiver to LVPECL */
285 SDR_WRITE(PESDR0_PLLLCT1, SDR_READ(PESDR0_PLLLCT1) | 1 << 28);
290 if (!(SDR_READ(PESDR0_PLLLCT2) & 0x10000))
292 printf("PCIE: PESDR_PLLCT2 resistance calibration failed (0x%08x)\n",
293 SDR_READ(PESDR0_PLLLCT2));
296 /* De-assert reset of PCIe PLL, wait for lock */
297 SDR_WRITE(PESDR0_PLLLCT1, SDR_READ(PESDR0_PLLLCT1) & ~(1 << 24));
301 if (!(SDR_READ(PESDR0_PLLLCT3) & 0x10000000)) {
308 printf("PCIE: VCO output not locked\n");
315 * Yucca board as End point and root point setup
317 * testing inbound and out bound windows
319 * YUCCA board can be plugged into another yucca board or you can get PCI-E
320 * cable which can be used to setup loop back from one port to another port.
321 * Please rememeber that unless there is a endpoint plugged in to root port it
322 * will not initialize. It is the same in case of endpoint , unless there is
323 * root port attached it will not initialize.
325 * In this release of software all the PCI-E ports are configured as either
326 * endpoint or rootpoint.In future we will have support for selective ports
327 * setup as endpoint and root point in single board.
329 * Once your board came up as root point , you can verify by reading
330 * /proc/bus/pci/devices. Where you can see the configuration registers
331 * of end point device attached to the port.
333 * Enpoint cofiguration can be verified by connecting Yucca board to any
334 * host or another yucca board. Then try to scan the device. In case of
335 * linux use "lspci" or appripriate os command.
337 * How do I verify the inbound and out bound windows ?(yucca to yucca)
338 * in this configuration inbound and outbound windows are setup to access
339 * sram memroy area. SRAM is at 0x4 0000 0000 , on PLB bus. This address
340 * is mapped at 0x90000000. From u-boot prompt write data 0xb000 0000,
341 * This is waere your POM(PLB out bound memory window) mapped. then
342 * read the data from other yucca board's u-boot prompt at address
343 * 0x9000 0000(SRAM). Data should match.
344 * In case of inbound , write data to u-boot command prompt at 0xb000 0000
345 * which is mapped to 0x4 0000 0000. Now on rootpoint yucca u-boot prompt check
346 * data at 0x9000 0000(SRAM).Data should match.
348 int ppc440spe_init_pcie_rootport(int port)
350 static int core_init;
351 volatile u32 val = 0;
356 if (ppc440spe_init_pcie())
361 * Initialize various parts of the PCI Express core for our port:
363 * - Set as a root port and enable max width
364 * (PXIE0 -> X8, PCIE1 and PCIE2 -> X4).
365 * - Set up UTL configuration.
366 * - Increase SERDES drive strength to levels suggested by AMCC.
367 * - De-assert RSTPYN, RSTDL and RSTGU.
369 * NOTICE for revB chip: PESDRn_UTLSET2 is not set - we leave it with
370 * default setting 0x11310000. The register has new fields,
371 * PESDRn_UTLSET2[LKINE] in particular: clearing it leads to PCIE core
376 SDR_WRITE(PESDR0_DLPSET, 1 << 24 | PTYPE_ROOT_PORT << 20 | LNKW_X8 << 12);
378 SDR_WRITE(PESDR0_UTLSET1, 0x21222222);
379 if (!ppc440spe_revB())
380 SDR_WRITE(PESDR0_UTLSET2, 0x11000000);
381 SDR_WRITE(PESDR0_HSSL0SET1, 0x35000000);
382 SDR_WRITE(PESDR0_HSSL1SET1, 0x35000000);
383 SDR_WRITE(PESDR0_HSSL2SET1, 0x35000000);
384 SDR_WRITE(PESDR0_HSSL3SET1, 0x35000000);
385 SDR_WRITE(PESDR0_HSSL4SET1, 0x35000000);
386 SDR_WRITE(PESDR0_HSSL5SET1, 0x35000000);
387 SDR_WRITE(PESDR0_HSSL6SET1, 0x35000000);
388 SDR_WRITE(PESDR0_HSSL7SET1, 0x35000000);
389 SDR_WRITE(PESDR0_RCSSET,
390 (SDR_READ(PESDR0_RCSSET) & ~(1 << 24 | 1 << 16)) | 1 << 12);
394 SDR_WRITE(PESDR1_DLPSET, 1 << 24 | PTYPE_ROOT_PORT << 20 | LNKW_X4 << 12);
395 SDR_WRITE(PESDR1_UTLSET1, 0x21222222);
396 if (!ppc440spe_revB())
397 SDR_WRITE(PESDR1_UTLSET2, 0x11000000);
398 SDR_WRITE(PESDR1_HSSL0SET1, 0x35000000);
399 SDR_WRITE(PESDR1_HSSL1SET1, 0x35000000);
400 SDR_WRITE(PESDR1_HSSL2SET1, 0x35000000);
401 SDR_WRITE(PESDR1_HSSL3SET1, 0x35000000);
402 SDR_WRITE(PESDR1_RCSSET,
403 (SDR_READ(PESDR1_RCSSET) & ~(1 << 24 | 1 << 16)) | 1 << 12);
407 SDR_WRITE(PESDR2_DLPSET, 1 << 24 | PTYPE_ROOT_PORT << 20 | LNKW_X4 << 12);
408 SDR_WRITE(PESDR2_UTLSET1, 0x21222222);
409 if (!ppc440spe_revB())
410 SDR_WRITE(PESDR2_UTLSET2, 0x11000000);
411 SDR_WRITE(PESDR2_HSSL0SET1, 0x35000000);
412 SDR_WRITE(PESDR2_HSSL1SET1, 0x35000000);
413 SDR_WRITE(PESDR2_HSSL2SET1, 0x35000000);
414 SDR_WRITE(PESDR2_HSSL3SET1, 0x35000000);
415 SDR_WRITE(PESDR2_RCSSET,
416 (SDR_READ(PESDR2_RCSSET) & ~(1 << 24 | 1 << 16)) | 1 << 12);
420 * Notice: the following delay has critical impact on device
421 * initialization - if too short (<50ms) the link doesn't get up.
427 val = SDR_READ(PESDR0_RCSSTS);
430 val = SDR_READ(PESDR1_RCSSTS);
433 val = SDR_READ(PESDR2_RCSSTS);
437 if (val & (1 << 20)) {
438 printf("PCIE%d: PGRST failed %08x\n", port, val);
448 val = SDR_READ(PESDR0_LOOP);
451 val = SDR_READ(PESDR1_LOOP);
454 val = SDR_READ(PESDR2_LOOP);
457 if (!(val & 0x00001000)) {
458 printf("PCIE%d: link is not up.\n", port);
463 * Setup UTL registers - but only on revA!
464 * We use default settings for revB chip.
466 if (!ppc440spe_revB())
467 ppc440spe_setup_utl(port);
470 * We map PCI Express configuration access into the 512MB regions
472 * NOTICE: revB is very strict about PLB real addressess and ranges to
473 * be mapped for config space; it seems to only work with d_nnnn_nnnn
474 * range (hangs the core upon config transaction attempts when set
475 * otherwise) while revA uses c_nnnn_nnnn.
478 * PCIE0: 0xc_4000_0000
479 * PCIE1: 0xc_8000_0000
480 * PCIE2: 0xc_c000_0000
483 * PCIE0: 0xd_0000_0000
484 * PCIE1: 0xd_2000_0000
485 * PCIE2: 0xd_4000_0000
490 if (ppc440spe_revB()) {
491 mtdcr(DCRN_PEGPL_CFGBAH(PCIE0), 0x0000000d);
492 mtdcr(DCRN_PEGPL_CFGBAL(PCIE0), 0x00000000);
495 mtdcr(DCRN_PEGPL_CFGBAH(PCIE0), 0x0000000c);
496 mtdcr(DCRN_PEGPL_CFGBAL(PCIE0), 0x40000000);
498 mtdcr(DCRN_PEGPL_CFGMSK(PCIE0), 0xe0000001); /* 512MB region, valid */
502 if (ppc440spe_revB()) {
503 mtdcr(DCRN_PEGPL_CFGBAH(PCIE1), 0x0000000d);
504 mtdcr(DCRN_PEGPL_CFGBAL(PCIE1), 0x20000000);
506 mtdcr(DCRN_PEGPL_CFGBAH(PCIE1), 0x0000000c);
507 mtdcr(DCRN_PEGPL_CFGBAL(PCIE1), 0x80000000);
509 mtdcr(DCRN_PEGPL_CFGMSK(PCIE1), 0xe0000001); /* 512MB region, valid */
513 if (ppc440spe_revB()) {
514 mtdcr(DCRN_PEGPL_CFGBAH(PCIE2), 0x0000000d);
515 mtdcr(DCRN_PEGPL_CFGBAL(PCIE2), 0x40000000);
517 mtdcr(DCRN_PEGPL_CFGBAH(PCIE2), 0x0000000c);
518 mtdcr(DCRN_PEGPL_CFGBAL(PCIE2), 0xc0000000);
520 mtdcr(DCRN_PEGPL_CFGMSK(PCIE2), 0xe0000001); /* 512MB region, valid */
525 * Check for VC0 active and assert RDY.
530 while(!(SDR_READ(PESDR0_RCSSTS) & (1 << 16))) {
532 printf("PCIE0: VC0 not active\n");
537 SDR_WRITE(PESDR0_RCSSET, SDR_READ(PESDR0_RCSSET) | 1 << 20);
540 while(!(SDR_READ(PESDR1_RCSSTS) & (1 << 16))) {
542 printf("PCIE1: VC0 not active\n");
548 SDR_WRITE(PESDR1_RCSSET, SDR_READ(PESDR1_RCSSET) | 1 << 20);
551 while(!(SDR_READ(PESDR2_RCSSTS) & (1 << 16))) {
553 printf("PCIE2: VC0 not active\n");
559 SDR_WRITE(PESDR2_RCSSET, SDR_READ(PESDR2_RCSSET) | 1 << 20);
567 int ppc440spe_init_pcie_endport(int port)
569 static int core_init;
570 volatile u32 val = 0;
575 if (ppc440spe_init_pcie())
580 * Initialize various parts of the PCI Express core for our port:
582 * - Set as a end port and enable max width
583 * (PXIE0 -> X8, PCIE1 and PCIE2 -> X4).
584 * - Set up UTL configuration.
585 * - Increase SERDES drive strength to levels suggested by AMCC.
586 * - De-assert RSTPYN, RSTDL and RSTGU.
588 * NOTICE for revB chip: PESDRn_UTLSET2 is not set - we leave it with
589 * default setting 0x11310000. The register has new fields,
590 * PESDRn_UTLSET2[LKINE] in particular: clearing it leads to PCIE core
595 SDR_WRITE(PESDR0_DLPSET, 1 << 24 | PTYPE_LEGACY_ENDPOINT << 20 | LNKW_X8 << 12);
597 SDR_WRITE(PESDR0_UTLSET1, 0x20222222);
598 if (!ppc440spe_revB())
599 SDR_WRITE(PESDR0_UTLSET2, 0x11000000);
600 SDR_WRITE(PESDR0_HSSL0SET1, 0x35000000);
601 SDR_WRITE(PESDR0_HSSL1SET1, 0x35000000);
602 SDR_WRITE(PESDR0_HSSL2SET1, 0x35000000);
603 SDR_WRITE(PESDR0_HSSL3SET1, 0x35000000);
604 SDR_WRITE(PESDR0_HSSL4SET1, 0x35000000);
605 SDR_WRITE(PESDR0_HSSL5SET1, 0x35000000);
606 SDR_WRITE(PESDR0_HSSL6SET1, 0x35000000);
607 SDR_WRITE(PESDR0_HSSL7SET1, 0x35000000);
608 SDR_WRITE(PESDR0_RCSSET,
609 (SDR_READ(PESDR0_RCSSET) & ~(1 << 24 | 1 << 16)) | 1 << 12);
613 SDR_WRITE(PESDR1_DLPSET, 1 << 24 | PTYPE_LEGACY_ENDPOINT << 20 | LNKW_X4 << 12);
614 SDR_WRITE(PESDR1_UTLSET1, 0x20222222);
615 if (!ppc440spe_revB())
616 SDR_WRITE(PESDR1_UTLSET2, 0x11000000);
617 SDR_WRITE(PESDR1_HSSL0SET1, 0x35000000);
618 SDR_WRITE(PESDR1_HSSL1SET1, 0x35000000);
619 SDR_WRITE(PESDR1_HSSL2SET1, 0x35000000);
620 SDR_WRITE(PESDR1_HSSL3SET1, 0x35000000);
621 SDR_WRITE(PESDR1_RCSSET,
622 (SDR_READ(PESDR1_RCSSET) & ~(1 << 24 | 1 << 16)) | 1 << 12);
626 SDR_WRITE(PESDR2_DLPSET, 1 << 24 | PTYPE_LEGACY_ENDPOINT << 20 | LNKW_X4 << 12);
627 SDR_WRITE(PESDR2_UTLSET1, 0x20222222);
628 if (!ppc440spe_revB())
629 SDR_WRITE(PESDR2_UTLSET2, 0x11000000);
630 SDR_WRITE(PESDR2_HSSL0SET1, 0x35000000);
631 SDR_WRITE(PESDR2_HSSL1SET1, 0x35000000);
632 SDR_WRITE(PESDR2_HSSL2SET1, 0x35000000);
633 SDR_WRITE(PESDR2_HSSL3SET1, 0x35000000);
634 SDR_WRITE(PESDR2_RCSSET,
635 (SDR_READ(PESDR2_RCSSET) & ~(1 << 24 | 1 << 16)) | 1 << 12);
639 * Notice: the following delay has critical impact on device
640 * initialization - if too short (<50ms) the link doesn't get up.
645 case 0: val = SDR_READ(PESDR0_RCSSTS); break;
646 case 1: val = SDR_READ(PESDR1_RCSSTS); break;
647 case 2: val = SDR_READ(PESDR2_RCSSTS); break;
650 if (val & (1 << 20)) {
651 printf("PCIE%d: PGRST failed %08x\n", port, val);
662 val = SDR_READ(PESDR0_LOOP);
665 val = SDR_READ(PESDR1_LOOP);
668 val = SDR_READ(PESDR2_LOOP);
671 if (!(val & 0x00001000)) {
672 printf("PCIE%d: link is not up.\n", port);
677 * Setup UTL registers - but only on revA!
678 * We use default settings for revB chip.
680 if (!ppc440spe_revB())
681 ppc440spe_setup_utl(port);
684 * We map PCI Express configuration access into the 512MB regions
686 * NOTICE: revB is very strict about PLB real addressess and ranges to
687 * be mapped for config space; it seems to only work with d_nnnn_nnnn
688 * range (hangs the core upon config transaction attempts when set
689 * otherwise) while revA uses c_nnnn_nnnn.
692 * PCIE0: 0xc_4000_0000
693 * PCIE1: 0xc_8000_0000
694 * PCIE2: 0xc_c000_0000
697 * PCIE0: 0xd_0000_0000
698 * PCIE1: 0xd_2000_0000
699 * PCIE2: 0xd_4000_0000
703 if (ppc440spe_revB()) {
704 mtdcr(DCRN_PEGPL_CFGBAH(PCIE0), 0x0000000d);
705 mtdcr(DCRN_PEGPL_CFGBAL(PCIE0), 0x00000000);
708 mtdcr(DCRN_PEGPL_CFGBAH(PCIE0), 0x0000000c);
709 mtdcr(DCRN_PEGPL_CFGBAL(PCIE0), 0x40000000);
711 mtdcr(DCRN_PEGPL_CFGMSK(PCIE0), 0xe0000001); /* 512MB region, valid */
715 if (ppc440spe_revB()) {
716 mtdcr(DCRN_PEGPL_CFGBAH(PCIE1), 0x0000000d);
717 mtdcr(DCRN_PEGPL_CFGBAL(PCIE1), 0x20000000);
719 mtdcr(DCRN_PEGPL_CFGBAH(PCIE1), 0x0000000c);
720 mtdcr(DCRN_PEGPL_CFGBAL(PCIE1), 0x80000000);
722 mtdcr(DCRN_PEGPL_CFGMSK(PCIE1), 0xe0000001); /* 512MB region, valid */
726 if (ppc440spe_revB()) {
727 mtdcr(DCRN_PEGPL_CFGBAH(PCIE2), 0x0000000d);
728 mtdcr(DCRN_PEGPL_CFGBAL(PCIE2), 0x40000000);
730 mtdcr(DCRN_PEGPL_CFGBAH(PCIE2), 0x0000000c);
731 mtdcr(DCRN_PEGPL_CFGBAL(PCIE2), 0xc0000000);
733 mtdcr(DCRN_PEGPL_CFGMSK(PCIE2), 0xe0000001); /* 512MB region, valid */
738 * Check for VC0 active and assert RDY.
743 while(!(SDR_READ(PESDR0_RCSSTS) & (1 << 16))) {
745 printf("PCIE0: VC0 not active\n");
750 SDR_WRITE(PESDR0_RCSSET, SDR_READ(PESDR0_RCSSET) | 1 << 20);
753 while(!(SDR_READ(PESDR1_RCSSTS) & (1 << 16))) {
755 printf("PCIE1: VC0 not active\n");
761 SDR_WRITE(PESDR1_RCSSET, SDR_READ(PESDR1_RCSSET) | 1 << 20);
764 while(!(SDR_READ(PESDR2_RCSSTS) & (1 << 16))) {
766 printf("PCIE2: VC0 not active\n");
772 SDR_WRITE(PESDR2_RCSSET, SDR_READ(PESDR2_RCSSET) | 1 << 20);
780 void ppc440spe_setup_pcie_rootpoint(struct pci_controller *hose, int port)
782 volatile void *mbase = NULL;
783 volatile void *rmbase = NULL;
786 pcie_read_config_byte,
787 pcie_read_config_word,
788 pcie_read_config_dword,
789 pcie_write_config_byte,
790 pcie_write_config_word,
791 pcie_write_config_dword);
795 mbase = (u32 *)CFG_PCIE0_XCFGBASE;
796 rmbase = (u32 *)CFG_PCIE0_CFGBASE;
797 hose->cfg_data = (u8 *)CFG_PCIE0_CFGBASE;
800 mbase = (u32 *)CFG_PCIE1_XCFGBASE;
801 rmbase = (u32 *)CFG_PCIE1_CFGBASE;
802 hose->cfg_data = (u8 *)CFG_PCIE1_CFGBASE;
805 mbase = (u32 *)CFG_PCIE2_XCFGBASE;
806 rmbase = (u32 *)CFG_PCIE2_CFGBASE;
807 hose->cfg_data = (u8 *)CFG_PCIE2_CFGBASE;
812 * Set bus numbers on our root port
814 if (ppc440spe_revB()) {
815 out_8((u8 *)mbase + PCI_PRIMARY_BUS, 0);
816 out_8((u8 *)mbase + PCI_SECONDARY_BUS, 1);
817 out_8((u8 *)mbase + PCI_SUBORDINATE_BUS, 1);
819 out_8((u8 *)mbase + PCI_PRIMARY_BUS, 0);
820 out_8((u8 *)mbase + PCI_SECONDARY_BUS, 0);
824 * Set up outbound translation to hose->mem_space from PLB
825 * addresses at an offset of 0xd_0000_0000. We set the low
826 * bits of the mask to 11 to turn off splitting into 8
827 * subregions and to enable the outbound translation.
829 out_le32(mbase + PECFG_POM0LAH, 0x00000000);
830 out_le32(mbase + PECFG_POM0LAL, 0x00000000);
834 mtdcr(DCRN_PEGPL_OMR1BAH(PCIE0), 0x0000000d);
835 mtdcr(DCRN_PEGPL_OMR1BAL(PCIE0), CFG_PCIE_MEMBASE +
836 port * CFG_PCIE_MEMSIZE);
837 mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE0), 0x7fffffff);
838 mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE0),
839 ~(CFG_PCIE_MEMSIZE - 1) | 3);
842 mtdcr(DCRN_PEGPL_OMR1BAH(PCIE1), 0x0000000d);
843 mtdcr(DCRN_PEGPL_OMR1BAL(PCIE1), (CFG_PCIE_MEMBASE +
844 port * CFG_PCIE_MEMSIZE));
845 mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE1), 0x7fffffff);
846 mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE1),
847 ~(CFG_PCIE_MEMSIZE - 1) | 3);
850 mtdcr(DCRN_PEGPL_OMR1BAH(PCIE2), 0x0000000d);
851 mtdcr(DCRN_PEGPL_OMR1BAL(PCIE2), (CFG_PCIE_MEMBASE +
852 port * CFG_PCIE_MEMSIZE));
853 mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE2), 0x7fffffff);
854 mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE2),
855 ~(CFG_PCIE_MEMSIZE - 1) | 3);
859 /* Set up 16GB inbound memory window at 0 */
860 out_le32(mbase + PCI_BASE_ADDRESS_0, 0);
861 out_le32(mbase + PCI_BASE_ADDRESS_1, 0);
862 out_le32(mbase + PECFG_BAR0HMPA, 0x7fffffc);
863 out_le32(mbase + PECFG_BAR0LMPA, 0);
865 out_le32(mbase + PECFG_PIM01SAH, 0xffff0000);
866 out_le32(mbase + PECFG_PIM01SAL, 0x00000000);
867 out_le32(mbase + PECFG_PIM0LAL, 0);
868 out_le32(mbase + PECFG_PIM0LAH, 0);
869 out_le32(mbase + PECFG_PIM1LAL, 0x00000000);
870 out_le32(mbase + PECFG_PIM1LAH, 0x00000004);
871 out_le32(mbase + PECFG_PIMEN, 0x1);
873 /* Enable I/O, Mem, and Busmaster cycles */
874 out_le16((u16 *)(mbase + PCI_COMMAND),
875 in_le16((u16 *)(mbase + PCI_COMMAND)) |
876 PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
877 printf("PCIE:%d successfully set as rootpoint\n",port);
880 int ppc440spe_setup_pcie_endpoint(struct pci_controller *hose, int port)
882 volatile void *mbase = NULL;
886 pcie_read_config_byte,
887 pcie_read_config_word,
888 pcie_read_config_dword,
889 pcie_write_config_byte,
890 pcie_write_config_word,
891 pcie_write_config_dword);
895 mbase = (u32 *)CFG_PCIE0_XCFGBASE;
896 hose->cfg_data = (u8 *)CFG_PCIE0_CFGBASE;
899 mbase = (u32 *)CFG_PCIE1_XCFGBASE;
900 hose->cfg_data = (u8 *)CFG_PCIE1_CFGBASE;
903 mbase = (u32 *)CFG_PCIE2_XCFGBASE;
904 hose->cfg_data = (u8 *)CFG_PCIE2_CFGBASE;
909 * Set up outbound translation to hose->mem_space from PLB
910 * addresses at an offset of 0xd_0000_0000. We set the low
911 * bits of the mask to 11 to turn off splitting into 8
912 * subregions and to enable the outbound translation.
914 out_le32(mbase + PECFG_POM0LAH, 0x00001ff8);
915 out_le32(mbase + PECFG_POM0LAL, 0x00001000);
919 mtdcr(DCRN_PEGPL_OMR1BAH(PCIE0), 0x0000000d);
920 mtdcr(DCRN_PEGPL_OMR1BAL(PCIE0), CFG_PCIE_MEMBASE +
921 port * CFG_PCIE_MEMSIZE);
922 mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE0), 0x7fffffff);
923 mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE0),
924 ~(CFG_PCIE_MEMSIZE - 1) | 3);
927 mtdcr(DCRN_PEGPL_OMR1BAH(PCIE1), 0x0000000d);
928 mtdcr(DCRN_PEGPL_OMR1BAL(PCIE1), (CFG_PCIE_MEMBASE +
929 port * CFG_PCIE_MEMSIZE));
930 mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE1), 0x7fffffff);
931 mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE1),
932 ~(CFG_PCIE_MEMSIZE - 1) | 3);
935 mtdcr(DCRN_PEGPL_OMR1BAH(PCIE2), 0x0000000d);
936 mtdcr(DCRN_PEGPL_OMR1BAL(PCIE2), (CFG_PCIE_MEMBASE +
937 port * CFG_PCIE_MEMSIZE));
938 mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE2), 0x7fffffff);
939 mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE2),
940 ~(CFG_PCIE_MEMSIZE - 1) | 3);
944 /* Set up 16GB inbound memory window at 0 */
945 out_le32(mbase + PCI_BASE_ADDRESS_0, 0);
946 out_le32(mbase + PCI_BASE_ADDRESS_1, 0);
947 out_le32(mbase + PECFG_BAR0HMPA, 0x7fffffc);
948 out_le32(mbase + PECFG_BAR0LMPA, 0);
949 out_le32(mbase + PECFG_PIM0LAL, 0x00000000);
950 out_le32(mbase + PECFG_PIM0LAH, 0x00000004); /* pointing to SRAM */
951 out_le32(mbase + PECFG_PIMEN, 0x1);
953 /* Enable I/O, Mem, and Busmaster cycles */
954 out_le16((u16 *)(mbase + PCI_COMMAND),
955 in_le16((u16 *)(mbase + PCI_COMMAND)) |
956 PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
957 out_le16(mbase + 0x200,0xcaad); /* Setting vendor ID */
958 out_le16(mbase + 0x202,0xfeed); /* Setting device ID */
962 while (!(SDR_READ(PESDR0_RCSSTS) & (1 << 8))) {
964 printf("PCIE0: BMEN is not active\n");
971 while (!(SDR_READ(PESDR1_RCSSTS) & (1 << 8))) {
973 printf("PCIE1: BMEN is not active\n");
980 while (!(SDR_READ(PESDR2_RCSSTS) & (1 << 8))) {
982 printf("PCIE2: BMEN is not active\n");
989 printf("PCIE:%d successfully set as endpoint\n",port);
993 #endif /* CONFIG_440SPE && CONFIG_PCI */