1 /*-----------------------------------------------------------------------------+
3 * This source code has been made available to you by IBM on an AS-IS
4 * basis. Anyone receiving this source is licensed under IBM
5 * copyrights to use it in any way he or she deems fit, including
6 * copying it, modifying it, compiling it, and redistributing it either
7 * with or without modifications. No license under IBM patents or
8 * patent applications is to be implied by the copyright license.
10 * Any user of this software should understand that IBM cannot provide
11 * technical support for this software and will not be responsible for
12 * any consequences resulting from the use of this software.
14 * Any person who transfers this source code or any derivative work
15 * must include the IBM copyright notice, this paragraph, and the
16 * preceding two paragraphs in the transferred software.
18 * COPYRIGHT I B M CORPORATION 1995
19 * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
20 *-----------------------------------------------------------------------------*/
21 /*-----------------------------------------------------------------------------+
23 * File Name: enetemac.c
25 * Function: Device driver for the ethernet EMAC3 macro on the 405GP.
31 * Date Description of Change BY
32 * --------- --------------------- ---
33 * 05-May-99 Created MKW
34 * 27-Jun-99 Clean up JWB
35 * 16-Jul-99 Added MAL error recovery and better IP packet handling MKW
36 * 29-Jul-99 Added Full duplex support MKW
37 * 06-Aug-99 Changed names for Mal CR reg MKW
38 * 23-Aug-99 Turned off SYE when running at 10Mbs MKW
39 * 24-Aug-99 Marked descriptor empty after call_xlc MKW
40 * 07-Sep-99 Set MAL RX buffer size reg to ENET_MAX_MTU_ALIGNED / 16 MCG
41 * to avoid chaining maximum sized packets. Push starting
42 * RX descriptor address up to the next cache line boundary.
43 * 16-Jan-00 Added support for booting with IP of 0x0 MKW
44 * 15-Mar-00 Updated enetInit() to enable broadcast addresses in the
45 * EMAC_RXM register. JWB
46 * 12-Mar-01 anne-sophie.harnois@nextream.fr
47 * - Variables are compatible with those already defined in
49 * - Receive buffer descriptor ring is used to send buffers
51 * - Info print about send/received/handled packet number if
52 * INFO_405_ENET is set
53 * 17-Apr-01 stefan.roese@esd-electronics.com
54 * - MAL reset in "eth_halt" included
55 * - Enet speed and duplex output now in one line
56 * 08-May-01 stefan.roese@esd-electronics.com
57 * - MAL error handling added (eth_init called again)
58 * 13-Nov-01 stefan.roese@esd-electronics.com
59 * - Set IST bit in EMAC_M1 reg upon 100MBit or full duplex
60 * 04-Jan-02 stefan.roese@esd-electronics.com
61 * - Wait for PHY auto negotiation to complete added
62 * 06-Feb-02 stefan.roese@esd-electronics.com
63 * - Bug fixed in waiting for auto negotiation to complete
64 * 26-Feb-02 stefan.roese@esd-electronics.com
65 * - rx and tx buffer descriptors now allocated (no fixed address
67 * 17-Jun-02 stefan.roese@esd-electronics.com
68 * - MAL error debug printf 'M' removed (rx de interrupt may
69 * occur upon many incoming packets with only 4 rx buffers).
70 *-----------------------------------------------------------------------------*
71 * 17-Nov-03 travis.sawyer@sandburst.com
72 * - ported from 405gp_enet.c to utilized upto 4 EMAC ports
73 * in the 440GX. This port should work with the 440GP
75 *-----------------------------------------------------------------------------*/
78 #if defined(CONFIG_440) && defined(CONFIG_NET_MULTI)
82 #include <asm/processor.h>
85 #include <440gx_enet.h>
92 #define EMAC_RESET_TIMEOUT 1000 /* 1000 ms reset timeout */
93 #define PHY_AUTONEGOTIATE_TIMEOUT 4000 /* 4000 ms autonegotiate timeout */
96 /* Ethernet Transmit and Receive Buffers */
98 * In the same way ENET_MAX_MTU and ENET_MAX_MTU_ALIGNED are set from
99 * PKTSIZE and PKTSIZE_ALIGN (include/net.h)
101 #define ENET_MAX_MTU PKTSIZE
102 #define ENET_MAX_MTU_ALIGNED PKTSIZE_ALIGN
105 /* define the number of channels implemented */
106 #define EMAC_RXCHL EMAC_NUM_DEV
107 #define EMAC_TXCHL EMAC_NUM_DEV
109 /*-----------------------------------------------------------------------------+
110 * Defines for MAL/EMAC interrupt conditions as reported in the UIC (Universal
111 * Interrupt Controller).
112 *-----------------------------------------------------------------------------*/
113 #define MAL_UIC_ERR ( UIC_MAL_SERR | UIC_MAL_TXDE | UIC_MAL_RXDE)
114 #define MAL_UIC_DEF (UIC_MAL_RXEOB | MAL_UIC_ERR)
115 #define EMAC_UIC_DEF UIC_ENET
119 #define BI_PHYMODE_NONE 0
120 #define BI_PHYMODE_ZMII 1
121 #define BI_PHYMODE_RGMII 2
123 /*-----------------------------------------------------------------------------+
124 * Global variables. TX and RX descriptors and buffers.
125 *-----------------------------------------------------------------------------*/
127 static uint32_t mal_ier;
129 /*-----------------------------------------------------------------------------+
130 * Prototypes and externals.
131 *-----------------------------------------------------------------------------*/
132 static void enet_rcv (struct eth_device *dev, unsigned long malisr);
134 int enetInt (struct eth_device *dev);
135 static void mal_err (struct eth_device *dev, unsigned long isr,
136 unsigned long uic, unsigned long maldef,
137 unsigned long mal_errr);
138 static void emac_err (struct eth_device *dev, unsigned long isr);
140 /*-----------------------------------------------------------------------------+
142 | Disable MAL channel, and EMACn
145 +-----------------------------------------------------------------------------*/
146 static void ppc_440x_eth_halt (struct eth_device *dev)
148 EMAC_440GX_HW_PST hw_p = dev->priv;
149 uint32_t failsafe = 10000;
151 out32 (EMAC_IER + hw_p->hw_addr, 0x00000000); /* disable emac interrupts */
153 /* 1st reset MAL channel */
154 /* Note: writing a 0 to a channel has no effect */
155 mtdcr (maltxcarr, (MAL_CR_MMSR >> hw_p->devnum));
156 mtdcr (malrxcarr, (MAL_CR_MMSR >> hw_p->devnum));
159 while (mfdcr (maltxcasr) & (MAL_CR_MMSR >> hw_p->devnum)) {
160 udelay (1000); /* Delay 1 MS so as not to hammer the register */
168 out32 (EMAC_M0 + hw_p->hw_addr, EMAC_M0_SRST);
170 hw_p->print_speed = 1; /* print speed message again next time */
175 extern int phy_setup_aneg (unsigned char addr);
176 extern int miiphy_reset (unsigned char addr);
178 #if defined (CONFIG_440_GX)
179 int ppc_440x_eth_setup_bridge(int devnum, bd_t * bis)
182 unsigned long zmiifer;
183 unsigned long rmiifer;
185 mfsdr(sdr_pfc1, pfc1);
186 pfc1 = SDR0_PFC1_EPS_DECODE(pfc1);
193 zmiifer |= ZMII_FER_RMII << ZMII_FER_V(0);
194 zmiifer |= ZMII_FER_RMII << ZMII_FER_V(1);
195 zmiifer |= ZMII_FER_RMII << ZMII_FER_V(2);
196 zmiifer |= ZMII_FER_RMII << ZMII_FER_V(3);
197 bis->bi_phymode[0] = BI_PHYMODE_ZMII;
198 bis->bi_phymode[1] = BI_PHYMODE_ZMII;
199 bis->bi_phymode[2] = BI_PHYMODE_ZMII;
200 bis->bi_phymode[3] = BI_PHYMODE_ZMII;
203 zmiifer = ZMII_FER_SMII << ZMII_FER_V(0);
204 zmiifer = ZMII_FER_SMII << ZMII_FER_V(1);
205 zmiifer = ZMII_FER_SMII << ZMII_FER_V(2);
206 zmiifer = ZMII_FER_SMII << ZMII_FER_V(3);
207 bis->bi_phymode[0] = BI_PHYMODE_ZMII;
208 bis->bi_phymode[1] = BI_PHYMODE_ZMII;
209 bis->bi_phymode[2] = BI_PHYMODE_ZMII;
210 bis->bi_phymode[3] = BI_PHYMODE_ZMII;
213 zmiifer |= ZMII_FER_RMII << ZMII_FER_V(0);
214 rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(2);
215 bis->bi_phymode[0] = BI_PHYMODE_ZMII;
216 bis->bi_phymode[1] = BI_PHYMODE_NONE;
217 bis->bi_phymode[2] = BI_PHYMODE_RGMII;
218 bis->bi_phymode[3] = BI_PHYMODE_NONE;
221 zmiifer |= ZMII_FER_SMII << ZMII_FER_V(0);
222 zmiifer |= ZMII_FER_SMII << ZMII_FER_V(1);
223 rmiifer |= RGMII_FER_RGMII << RGMII_FER_V (2);
224 rmiifer |= RGMII_FER_RGMII << RGMII_FER_V (3);
225 bis->bi_phymode[0] = BI_PHYMODE_ZMII;
226 bis->bi_phymode[1] = BI_PHYMODE_ZMII;
227 bis->bi_phymode[2] = BI_PHYMODE_RGMII;
228 bis->bi_phymode[3] = BI_PHYMODE_RGMII;
231 zmiifer |= ZMII_FER_SMII << ZMII_FER_V (0);
232 zmiifer |= ZMII_FER_SMII << ZMII_FER_V (1);
233 zmiifer |= ZMII_FER_SMII << ZMII_FER_V (2);
234 rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(3);
235 bis->bi_phymode[0] = BI_PHYMODE_ZMII;
236 bis->bi_phymode[1] = BI_PHYMODE_ZMII;
237 bis->bi_phymode[2] = BI_PHYMODE_ZMII;
238 bis->bi_phymode[3] = BI_PHYMODE_RGMII;
241 zmiifer |= ZMII_FER_SMII << ZMII_FER_V (0);
242 zmiifer |= ZMII_FER_SMII << ZMII_FER_V (1);
243 rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(2);
244 rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(3);
245 bis->bi_phymode[0] = BI_PHYMODE_ZMII;
246 bis->bi_phymode[1] = BI_PHYMODE_ZMII;
247 bis->bi_phymode[2] = BI_PHYMODE_RGMII;
248 bis->bi_phymode[3] = BI_PHYMODE_RGMII;
252 zmiifer = ZMII_FER_MII << ZMII_FER_V(devnum);
254 bis->bi_phymode[0] = BI_PHYMODE_ZMII;
255 bis->bi_phymode[1] = BI_PHYMODE_ZMII;
256 bis->bi_phymode[2] = BI_PHYMODE_ZMII;
257 bis->bi_phymode[3] = BI_PHYMODE_ZMII;
261 /* Ensure we setup mdio for this devnum and ONLY this devnum */
262 zmiifer |= (ZMII_FER_MDI) << ZMII_FER_V(devnum);
264 out32 (ZMII_FER, zmiifer);
265 out32 (RGMII_FER, rmiifer);
272 static int ppc_440x_eth_init (struct eth_device *dev, bd_t * bis)
278 unsigned long duplex;
279 unsigned long failsafe;
281 unsigned short devnum;
282 unsigned short reg_short;
286 EMAC_440GX_HW_PST hw_p = dev->priv;
288 /* before doing anything, figure out if we have a MAC address */
290 if (memcmp (dev->enetaddr, "\0\0\0\0\0\0", 6) == 0)
293 /* Need to get the OPB frequency so we can access the PHY */
294 get_sys_info (&sysinfo);
298 mtmsr (msr & ~(MSR_EE)); /* disable interrupts */
300 devnum = hw_p->devnum;
305 * hw_p->stats.pkts_handled <= hw_p->stats.pkts_rx <= hw_p->stats.pkts_handled+PKTBUFSRX
306 * In the most cases hw_p->stats.pkts_handled = hw_p->stats.pkts_rx, but it
307 * is possible that new packets (without relationship with
308 * current transfer) have got the time to arrived before
309 * netloop calls eth_halt
311 printf ("About preceeding transfer (eth%d):\n"
312 "- Sent packet number %d\n"
313 "- Received packet number %d\n"
314 "- Handled packet number %d\n",
317 hw_p->stats.pkts_rx, hw_p->stats.pkts_handled);
319 hw_p->stats.pkts_tx = 0;
320 hw_p->stats.pkts_rx = 0;
321 hw_p->stats.pkts_handled = 0;
324 /* MAL Channel RESET */
325 /* 1st reset MAL channel */
326 /* Note: writing a 0 to a channel has no effect */
327 mtdcr (maltxcarr, (MAL_TXRX_CASR >> hw_p->devnum));
328 mtdcr (malrxcarr, (MAL_TXRX_CASR >> hw_p->devnum));
331 /* TBS: should have udelay and failsafe here */
334 while (mfdcr (maltxcasr) & (MAL_CR_MMSR >> hw_p->devnum)) {
335 udelay (1000); /* Delay 1 MS so as not to hammer the register */
342 hw_p->tx_err_index = 0; /* Transmit Error Index for tx_err_log */
343 hw_p->rx_err_index = 0; /* Receive Error Index for rx_err_log */
345 hw_p->rx_slot = 0; /* MAL Receive Slot */
346 hw_p->rx_i_index = 0; /* Receive Interrupt Queue Index */
347 hw_p->rx_u_index = 0; /* Receive User Queue Index */
349 hw_p->tx_slot = 0; /* MAL Transmit Slot */
350 hw_p->tx_i_index = 0; /* Transmit Interrupt Queue Index */
351 hw_p->tx_u_index = 0; /* Transmit User Queue Index */
354 /* NOTE: 440GX spec states that mode is mutually exclusive */
355 /* NOTE: Therefore, disable all other EMACS, since we handle */
356 /* NOTE: only one emac at a time */
361 #if defined(CONFIG_440_GX)
362 ethgroup = ppc_440x_eth_setup_bridge(devnum, bis);
364 if ((devnum == 0) || (devnum == 1)) {
365 out32 (ZMII_FER, (ZMII_FER_SMII | ZMII_FER_MDI) << ZMII_FER_V (devnum));
367 else { /* ((devnum == 2) || (devnum == 3)) */
368 out32 (ZMII_FER, ZMII_FER_MDI << ZMII_FER_V (devnum));
369 out32 (RGMII_FER, ((RGMII_FER_RGMII << RGMII_FER_V (2)) |
370 (RGMII_FER_RGMII << RGMII_FER_V (3))));
374 out32 (ZMII_SSR, ZMII_SSR_SP << ZMII_SSR_V(devnum));
375 __asm__ volatile ("eieio");
377 /* reset emac so we have access to the phy */
379 out32 (EMAC_M0 + hw_p->hw_addr, EMAC_M0_SRST);
380 __asm__ volatile ("eieio");
383 while ((in32 (EMAC_M0 + hw_p->hw_addr) & (EMAC_M0_SRST)) && failsafe) {
388 /* Whack the M1 register */
390 mode_reg &= ~0x00000038;
391 if (sysinfo.freqOPB <= 50000000);
392 else if (sysinfo.freqOPB <= 66666667)
393 mode_reg |= EMAC_M1_OBCI_66;
394 else if (sysinfo.freqOPB <= 83333333)
395 mode_reg |= EMAC_M1_OBCI_83;
396 else if (sysinfo.freqOPB <= 100000000)
397 mode_reg |= EMAC_M1_OBCI_100;
399 mode_reg |= EMAC_M1_OBCI_GT100;
401 out32 (EMAC_M1 + hw_p->hw_addr, mode_reg);
404 /* wait for PHY to complete auto negotiation */
406 #ifndef CONFIG_CS8952_PHY
409 reg = CONFIG_PHY_ADDR;
412 reg = CONFIG_PHY1_ADDR;
414 #if defined (CONFIG_440_GX)
416 reg = CONFIG_PHY2_ADDR;
419 reg = CONFIG_PHY3_ADDR;
423 reg = CONFIG_PHY_ADDR;
427 bis->bi_phynum[devnum] = reg;
432 #if defined(CONFIG_440_GX)
433 #if defined(CONFIG_CIS8201_PHY)
435 * Cicada 8201 PHY needs to have an extended register whacked
438 if ( ((devnum == 2) || (devnum ==3)) && (4 == ethgroup) ) {
439 miiphy_write (reg, 23, 0x1200);
441 * Vitesse VSC8201/Cicada CIS8201 errata:
442 * Interoperability problem with Intel 82547EI phys
443 * This work around (provided by Vitesse) changes
444 * the default timer convergence from 8ms to 12ms
446 miiphy_write (reg, 0x1f, 0x2a30);
447 miiphy_write (reg, 0x08, 0x0200);
448 miiphy_write (reg, 0x1f, 0x52b5);
449 miiphy_write (reg, 0x02, 0x0004);
450 miiphy_write (reg, 0x01, 0x0671);
451 miiphy_write (reg, 0x00, 0x8fae);
452 miiphy_write (reg, 0x1f, 0x2a30);
453 miiphy_write (reg, 0x08, 0x0000);
454 miiphy_write (reg, 0x1f, 0x0000);
455 /* end Vitesse/Cicada errata */
459 /* Start/Restart autonegotiation */
460 phy_setup_aneg (reg);
463 miiphy_read (reg, PHY_BMSR, ®_short);
466 * Wait if PHY is capable of autonegotiation and autonegotiation is not complete
468 if ((reg_short & PHY_BMSR_AUTN_ABLE)
469 && !(reg_short & PHY_BMSR_AUTN_COMP)) {
470 puts ("Waiting for PHY auto negotiation to complete");
472 while (!(reg_short & PHY_BMSR_AUTN_COMP)) {
476 if (i > PHY_AUTONEGOTIATE_TIMEOUT) {
477 puts (" TIMEOUT !\n");
481 if ((i++ % 1000) == 0) {
484 udelay (1000); /* 1 ms */
485 miiphy_read (reg, PHY_BMSR, ®_short);
489 udelay (500000); /* another 500 ms (results in faster booting) */
492 speed = miiphy_speed (reg);
493 duplex = miiphy_duplex (reg);
495 if (hw_p->print_speed) {
496 hw_p->print_speed = 0;
497 printf ("ENET Speed is %d Mbps - %s duplex connection\n",
498 (int) speed, (duplex == HALF) ? "HALF" : "FULL");
501 /* Set ZMII/RGMII speed according to the phy link speed */
502 reg = in32 (ZMII_SSR);
503 if ( (speed == 100) || (speed == 1000) )
504 out32 (ZMII_SSR, reg | (ZMII_SSR_SP << ZMII_SSR_V (devnum)));
507 reg & (~(ZMII_SSR_SP << ZMII_SSR_V (devnum))));
509 if ((devnum == 2) || (devnum == 3)) {
511 reg = (RGMII_SSR_SP_1000MBPS << RGMII_SSR_V (devnum));
512 else if (speed == 100)
513 reg = (RGMII_SSR_SP_100MBPS << RGMII_SSR_V (devnum));
515 reg = (RGMII_SSR_SP_10MBPS << RGMII_SSR_V (devnum));
517 out32 (RGMII_SSR, reg);
520 /* set the Mal configuration reg */
521 /* Errata 1.12: MAL_1 -- Disable MAL bursting */
522 if (get_pvr () == PVR_440GP_RB)
524 MAL_CR_OPBBL | MAL_CR_LEA | MAL_CR_PLBLT_DEFAULT);
527 MAL_CR_PLBB | MAL_CR_OPBBL | MAL_CR_LEA |
528 MAL_CR_PLBLT_DEFAULT | MAL_CR_EOPIE | 0x00330000);
530 /* Free "old" buffers */
531 if (hw_p->alloc_tx_buf)
532 free (hw_p->alloc_tx_buf);
533 if (hw_p->alloc_rx_buf)
534 free (hw_p->alloc_rx_buf);
537 * Malloc MAL buffer desciptors, make sure they are
538 * aligned on cache line boundary size
539 * (401/403/IOP480 = 16, 405 = 32)
540 * and doesn't cross cache block boundaries.
543 (mal_desc_t *) malloc ((sizeof (mal_desc_t) * NUM_TX_BUFF) +
544 ((2 * CFG_CACHELINE_SIZE) - 2));
545 if (((int) hw_p->alloc_tx_buf & CACHELINE_MASK) != 0) {
547 (mal_desc_t *) ((int) hw_p->alloc_tx_buf +
550 alloc_tx_buf & CACHELINE_MASK));
552 hw_p->tx = hw_p->alloc_tx_buf;
556 (mal_desc_t *) malloc ((sizeof (mal_desc_t) * NUM_RX_BUFF) +
557 ((2 * CFG_CACHELINE_SIZE) - 2));
558 if (((int) hw_p->alloc_rx_buf & CACHELINE_MASK) != 0) {
560 (mal_desc_t *) ((int) hw_p->alloc_rx_buf +
563 alloc_rx_buf & CACHELINE_MASK));
565 hw_p->rx = hw_p->alloc_rx_buf;
568 for (i = 0; i < NUM_TX_BUFF; i++) {
569 hw_p->tx[i].ctrl = 0;
570 hw_p->tx[i].data_len = 0;
571 if (hw_p->first_init == 0)
573 (char *) malloc (ENET_MAX_MTU_ALIGNED);
574 hw_p->tx[i].data_ptr = hw_p->txbuf_ptr;
575 if ((NUM_TX_BUFF - 1) == i)
576 hw_p->tx[i].ctrl |= MAL_TX_CTRL_WRAP;
577 hw_p->tx_run[i] = -1;
579 printf ("TX_BUFF %d @ 0x%08lx\n", i,
580 (ulong) hw_p->tx[i].data_ptr);
584 for (i = 0; i < NUM_RX_BUFF; i++) {
585 hw_p->rx[i].ctrl = 0;
586 hw_p->rx[i].data_len = 0;
587 /* rx[i].data_ptr = (char *) &rx_buff[i]; */
588 hw_p->rx[i].data_ptr = (char *) NetRxPackets[i];
589 if ((NUM_RX_BUFF - 1) == i)
590 hw_p->rx[i].ctrl |= MAL_RX_CTRL_WRAP;
591 hw_p->rx[i].ctrl |= MAL_RX_CTRL_EMPTY | MAL_RX_CTRL_INTR;
592 hw_p->rx_ready[i] = -1;
594 printf ("RX_BUFF %d @ 0x%08lx\n", i, (ulong) rx[i].data_ptr);
600 reg |= dev->enetaddr[0]; /* set high address */
602 reg |= dev->enetaddr[1];
604 out32 (EMAC_IAH + hw_p->hw_addr, reg);
607 reg |= dev->enetaddr[2]; /* set low address */
609 reg |= dev->enetaddr[3];
611 reg |= dev->enetaddr[4];
613 reg |= dev->enetaddr[5];
615 out32 (EMAC_IAL + hw_p->hw_addr, reg);
619 /* setup MAL tx & rx channel pointers */
620 mtdcr (maltxbattr, 0x0);
621 mtdcr (maltxctp1r, hw_p->tx);
622 mtdcr (malrxbattr, 0x0);
623 mtdcr (malrxctp1r, hw_p->rx);
624 /* set RX buffer size */
625 mtdcr (malrcbs1, ENET_MAX_MTU_ALIGNED / 16);
627 #if defined (CONFIG_440_GX)
629 /* setup MAL tx & rx channel pointers */
630 mtdcr (maltxbattr, 0x0);
631 mtdcr (maltxctp2r, hw_p->tx);
632 mtdcr (malrxbattr, 0x0);
633 mtdcr (malrxctp2r, hw_p->rx);
634 /* set RX buffer size */
635 mtdcr (malrcbs2, ENET_MAX_MTU_ALIGNED / 16);
638 /* setup MAL tx & rx channel pointers */
639 mtdcr (maltxbattr, 0x0);
640 mtdcr (maltxctp3r, hw_p->tx);
641 mtdcr (malrxbattr, 0x0);
642 mtdcr (malrxctp3r, hw_p->rx);
643 /* set RX buffer size */
644 mtdcr (malrcbs3, ENET_MAX_MTU_ALIGNED / 16);
646 #endif /*CONFIG_440_GX */
649 /* setup MAL tx & rx channel pointers */
650 mtdcr (maltxbattr, 0x0);
651 mtdcr (maltxctp0r, hw_p->tx);
652 mtdcr (malrxbattr, 0x0);
653 mtdcr (malrxctp0r, hw_p->rx);
654 /* set RX buffer size */
655 mtdcr (malrcbs0, ENET_MAX_MTU_ALIGNED / 16);
659 /* Enable MAL transmit and receive channels */
660 mtdcr (maltxcasr, (MAL_TXRX_CASR >> hw_p->devnum));
661 mtdcr (malrxcasr, (MAL_TXRX_CASR >> hw_p->devnum));
663 /* set transmit enable & receive enable */
664 out32 (EMAC_M0 + hw_p->hw_addr, EMAC_M0_TXE | EMAC_M0_RXE);
666 /* set receive fifo to 4k and tx fifo to 2k */
667 mode_reg = in32 (EMAC_M1 + hw_p->hw_addr);
668 mode_reg |= EMAC_M1_RFS_4K | EMAC_M1_TX_FIFO_2K;
671 if (speed == _1000BASET)
672 mode_reg = mode_reg | EMAC_M1_MF_1000MBPS | EMAC_M1_IST;
673 else if (speed == _100BASET)
674 mode_reg = mode_reg | EMAC_M1_MF_100MBPS | EMAC_M1_IST;
676 mode_reg = mode_reg & ~0x00C00000; /* 10 MBPS */
678 mode_reg = mode_reg | 0x80000000 | EMAC_M1_IST;
680 out32 (EMAC_M1 + hw_p->hw_addr, mode_reg);
682 /* Enable broadcast and indvidual address */
683 /* TBS: enabling runts as some misbehaved nics will send runts */
684 out32 (EMAC_RXM + hw_p->hw_addr, EMAC_RMR_BAE | EMAC_RMR_IAE);
686 /* we probably need to set the tx mode1 reg? maybe at tx time */
688 /* set transmit request threshold register */
689 out32 (EMAC_TRTR + hw_p->hw_addr, 0x18000000); /* 256 byte threshold */
691 /* set receive low/high water mark register */
692 /* 440GP has a 64 byte burst length */
693 out32 (EMAC_RX_HI_LO_WMARK + hw_p->hw_addr, 0x80009000);
694 out32 (EMAC_TXM1 + hw_p->hw_addr, 0xf8640000);
696 /* Set fifo limit entry in tx mode 0 */
697 out32 (EMAC_TXM0 + hw_p->hw_addr, 0x00000003);
699 out32 (EMAC_I_FRAME_GAP_REG + hw_p->hw_addr, 0x00000008);
702 hw_p->emac_ier = EMAC_ISR_PTLE | EMAC_ISR_BFCS |
703 EMAC_ISR_PTLE | EMAC_ISR_ORE | EMAC_ISR_IRE;
704 if (speed == _100BASET)
705 hw_p->emac_ier = hw_p->emac_ier | EMAC_ISR_SYE;
707 out32 (EMAC_ISR + hw_p->hw_addr, 0xffffffff); /* clear pending interrupts */
708 out32 (EMAC_IER + hw_p->hw_addr, hw_p->emac_ier);
710 if (hw_p->first_init == 0) {
712 * Connect interrupt service routines
714 irq_install_handler (VECNUM_EWU0 + (hw_p->devnum * 2),
715 (interrupt_handler_t *) enetInt, dev);
716 irq_install_handler (VECNUM_ETH0 + (hw_p->devnum * 2),
717 (interrupt_handler_t *) enetInt, dev);
720 mtmsr (msr); /* enable interrupts again */
723 hw_p->first_init = 1;
729 static int ppc_440x_eth_send (struct eth_device *dev, volatile void *ptr,
732 struct enet_frame *ef_ptr;
733 ulong time_start, time_now;
734 unsigned long temp_txm0;
735 EMAC_440GX_HW_PST hw_p = dev->priv;
737 ef_ptr = (struct enet_frame *) ptr;
739 /*-----------------------------------------------------------------------+
740 * Copy in our address into the frame.
741 *-----------------------------------------------------------------------*/
742 (void) memcpy (ef_ptr->source_addr, dev->enetaddr, ENET_ADDR_LENGTH);
744 /*-----------------------------------------------------------------------+
745 * If frame is too long or too short, modify length.
746 *-----------------------------------------------------------------------*/
747 /* TBS: where does the fragment go???? */
748 if (len > ENET_MAX_MTU)
751 /* memcpy ((void *) &tx_buff[tx_slot], (const void *) ptr, len); */
752 memcpy ((void *) hw_p->txbuf_ptr, (const void *) ptr, len);
754 /*-----------------------------------------------------------------------+
755 * set TX Buffer busy, and send it
756 *-----------------------------------------------------------------------*/
757 hw_p->tx[hw_p->tx_slot].ctrl = (MAL_TX_CTRL_LAST |
758 EMAC_TX_CTRL_GFCS | EMAC_TX_CTRL_GP) &
759 ~(EMAC_TX_CTRL_ISA | EMAC_TX_CTRL_RSA);
760 if ((NUM_TX_BUFF - 1) == hw_p->tx_slot)
761 hw_p->tx[hw_p->tx_slot].ctrl |= MAL_TX_CTRL_WRAP;
763 hw_p->tx[hw_p->tx_slot].data_len = (short) len;
764 hw_p->tx[hw_p->tx_slot].ctrl |= MAL_TX_CTRL_READY;
766 __asm__ volatile ("eieio");
768 out32 (EMAC_TXM0 + hw_p->hw_addr,
769 in32 (EMAC_TXM0 + hw_p->hw_addr) | EMAC_TXM0_GNP0);
771 hw_p->stats.pkts_tx++;
774 /*-----------------------------------------------------------------------+
775 * poll unitl the packet is sent and then make sure it is OK
776 *-----------------------------------------------------------------------*/
777 time_start = get_timer (0);
779 temp_txm0 = in32 (EMAC_TXM0 + hw_p->hw_addr);
780 /* loop until either TINT turns on or 3 seconds elapse */
781 if ((temp_txm0 & EMAC_TXM0_GNP0) != 0) {
782 /* transmit is done, so now check for errors
783 * If there is an error, an interrupt should
784 * happen when we return
786 time_now = get_timer (0);
787 if ((time_now - time_start) > 3000) {
797 int enetInt (struct eth_device *dev)
800 int rc = -1; /* default to not us */
801 unsigned long mal_isr;
802 unsigned long emac_isr = 0;
803 unsigned long mal_rx_eob;
804 unsigned long my_uic0msr, my_uic1msr;
806 #if defined(CONFIG_440_GX)
807 unsigned long my_uic2msr;
809 EMAC_440GX_HW_PST hw_p;
812 * Because the mal is generic, we need to get the current
815 dev = eth_get_dev ();
820 /* enter loop that stays in interrupt code until nothing to service */
824 my_uic0msr = mfdcr (uic0msr);
825 my_uic1msr = mfdcr (uic1msr);
826 #if defined(CONFIG_440_GX)
827 my_uic2msr = mfdcr (uic2msr);
829 if (!(my_uic0msr & (UIC_MRE | UIC_MTE))
831 (UIC_ETH0 | UIC_ETH1 | UIC_MS | UIC_MTDE |
836 #if defined (CONFIG_440_GX)
837 if (!(my_uic0msr & (UIC_MRE | UIC_MTE))
838 && !(my_uic2msr & (UIC_ETH2 | UIC_ETH3))) {
843 /* get and clear controller status interrupts */
844 /* look at Mal and EMAC interrupts */
845 if ((my_uic0msr & (UIC_MRE | UIC_MTE))
846 || (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) {
847 /* we have a MAL interrupt */
848 mal_isr = mfdcr (malesr);
849 /* look for mal error */
850 if (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE)) {
851 mal_err (dev, mal_isr, my_uic0msr,
852 MAL_UIC_DEF, MAL_UIC_ERR);
858 /* port by port dispatch of emac interrupts */
859 if (hw_p->devnum == 0) {
860 if (UIC_ETH0 & my_uic1msr) { /* look for EMAC errors */
861 emac_isr = in32 (EMAC_ISR + hw_p->hw_addr);
862 if ((hw_p->emac_ier & emac_isr) != 0) {
863 emac_err (dev, emac_isr);
868 if ((hw_p->emac_ier & emac_isr)
869 || (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) {
870 mtdcr (uic0sr, UIC_MRE | UIC_MTE); /* Clear */
871 mtdcr (uic1sr, UIC_ETH0 | UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */
872 return (rc); /* we had errors so get out */
876 if (hw_p->devnum == 1) {
877 if (UIC_ETH1 & my_uic1msr) { /* look for EMAC errors */
878 emac_isr = in32 (EMAC_ISR + hw_p->hw_addr);
879 if ((hw_p->emac_ier & emac_isr) != 0) {
880 emac_err (dev, emac_isr);
885 if ((hw_p->emac_ier & emac_isr)
886 || (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) {
887 mtdcr (uic0sr, UIC_MRE | UIC_MTE); /* Clear */
888 mtdcr (uic1sr, UIC_ETH1 | UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */
889 return (rc); /* we had errors so get out */
892 #if defined (CONFIG_440_GX)
893 if (hw_p->devnum == 2) {
894 if (UIC_ETH2 & my_uic2msr) { /* look for EMAC errors */
895 emac_isr = in32 (EMAC_ISR + hw_p->hw_addr);
896 if ((hw_p->emac_ier & emac_isr) != 0) {
897 emac_err (dev, emac_isr);
902 if ((hw_p->emac_ier & emac_isr)
903 || (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) {
904 mtdcr (uic0sr, UIC_MRE | UIC_MTE); /* Clear */
905 mtdcr (uic1sr, UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */
906 mtdcr (uic2sr, UIC_ETH2);
907 return (rc); /* we had errors so get out */
911 if (hw_p->devnum == 3) {
912 if (UIC_ETH3 & my_uic2msr) { /* look for EMAC errors */
913 emac_isr = in32 (EMAC_ISR + hw_p->hw_addr);
914 if ((hw_p->emac_ier & emac_isr) != 0) {
915 emac_err (dev, emac_isr);
920 if ((hw_p->emac_ier & emac_isr)
921 || (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) {
922 mtdcr (uic0sr, UIC_MRE | UIC_MTE); /* Clear */
923 mtdcr (uic1sr, UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */
924 mtdcr (uic2sr, UIC_ETH3);
925 return (rc); /* we had errors so get out */
928 #endif /* CONFIG_440_GX */
929 /* handle MAX TX EOB interrupt from a tx */
930 if (my_uic0msr & UIC_MTE) {
931 mal_rx_eob = mfdcr (maltxeobisr);
932 mtdcr (maltxeobisr, mal_rx_eob);
933 mtdcr (uic0sr, UIC_MTE);
935 /* handle MAL RX EOB interupt from a receive */
936 /* check for EOB on valid channels */
937 if (my_uic0msr & UIC_MRE) {
938 mal_rx_eob = mfdcr (malrxeobisr);
939 if ((mal_rx_eob & (0x80000000 >> hw_p->devnum)) != 0) { /* call emac routine for channel x */
941 mtdcr(malrxeobisr, mal_rx_eob); */
942 enet_rcv (dev, emac_isr);
943 /* indicate that we serviced an interrupt */
948 mtdcr (uic0sr, UIC_MRE); /* Clear */
949 mtdcr (uic1sr, UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */
950 switch (hw_p->devnum) {
952 mtdcr (uic1sr, UIC_ETH0);
955 mtdcr (uic1sr, UIC_ETH1);
957 #if defined (CONFIG_440_GX)
959 mtdcr (uic2sr, UIC_ETH2);
962 mtdcr (uic2sr, UIC_ETH3);
964 #endif /* CONFIG_440_GX */
973 /*-----------------------------------------------------------------------------+
975 *-----------------------------------------------------------------------------*/
976 static void mal_err (struct eth_device *dev, unsigned long isr,
977 unsigned long uic, unsigned long maldef,
978 unsigned long mal_errr)
980 EMAC_440GX_HW_PST hw_p = dev->priv;
982 mtdcr (malesr, isr); /* clear interrupt */
984 /* clear DE interrupt */
985 mtdcr (maltxdeir, 0xC0000000);
986 mtdcr (malrxdeir, 0x80000000);
989 printf ("\nMAL error occured.... ISR = %lx UIC = = %lx MAL_DEF = %lx MAL_ERR= %lx \n", isr, uic, maldef, mal_errr);
992 eth_init (hw_p->bis); /* start again... */
995 /*-----------------------------------------------------------------------------+
997 *-----------------------------------------------------------------------------*/
998 static void emac_err (struct eth_device *dev, unsigned long isr)
1000 EMAC_440GX_HW_PST hw_p = dev->priv;
1002 printf ("EMAC%d error occured.... ISR = %lx\n", hw_p->devnum, isr);
1003 out32 (EMAC_ISR + hw_p->hw_addr, isr);
1006 /*-----------------------------------------------------------------------------+
1007 * enet_rcv() handles the ethernet receive data
1008 *-----------------------------------------------------------------------------*/
1009 static void enet_rcv (struct eth_device *dev, unsigned long malisr)
1011 struct enet_frame *ef_ptr;
1012 unsigned long data_len;
1013 unsigned long rx_eob_isr;
1014 EMAC_440GX_HW_PST hw_p = dev->priv;
1020 rx_eob_isr = mfdcr (malrxeobisr);
1021 if ((0x80000000 >> hw_p->devnum) & rx_eob_isr) {
1023 mtdcr (malrxeobisr, rx_eob_isr);
1026 while (1) { /* do all */
1029 if ((MAL_RX_CTRL_EMPTY & hw_p->rx[i].ctrl)
1030 || (loop_count >= NUM_RX_BUFF))
1034 if (NUM_RX_BUFF == hw_p->rx_slot)
1037 data_len = (unsigned long) hw_p->rx[i].data_len; /* Get len */
1039 if (data_len > ENET_MAX_MTU) /* Check len */
1042 if (EMAC_RX_ERRORS & hw_p->rx[i].ctrl) { /* Check Errors */
1044 hw_p->stats.rx_err_log[hw_p->
1047 hw_p->rx_err_index++;
1048 if (hw_p->rx_err_index ==
1050 hw_p->rx_err_index =
1053 } /* data_len < max mtu */
1055 if (!data_len) { /* no data */
1056 hw_p->rx[i].ctrl |= MAL_RX_CTRL_EMPTY; /* Free Recv Buffer */
1058 hw_p->stats.data_len_err++; /* Error at Rx */
1063 /* Check if user has already eaten buffer */
1064 /* if not => ERROR */
1065 else if (hw_p->rx_ready[hw_p->rx_i_index] != -1) {
1066 if (hw_p->is_receiving)
1067 printf ("ERROR : Receive buffers are full!\n");
1070 hw_p->stats.rx_frames++;
1071 hw_p->stats.rx += data_len;
1072 ef_ptr = (struct enet_frame *) hw_p->rx[i].
1074 #ifdef INFO_440_ENET
1075 hw_p->stats.pkts_rx++;
1080 hw_p->rx_ready[hw_p->rx_i_index] = i;
1082 if (NUM_RX_BUFF == hw_p->rx_i_index)
1083 hw_p->rx_i_index = 0;
1085 /* printf("X"); /|* test-only *|/ */
1088 * free receive buffer only when
1089 * buffer has been handled (eth_rx)
1090 rx[i].ctrl |= MAL_RX_CTRL_EMPTY;
1094 } /* if EMACK_RXCHL */
1098 static int ppc_440x_eth_rx (struct eth_device *dev)
1103 EMAC_440GX_HW_PST hw_p = dev->priv;
1105 hw_p->is_receiving = 1; /* tell driver */
1109 * use ring buffer and
1110 * get index from rx buffer desciptor queue
1112 user_index = hw_p->rx_ready[hw_p->rx_u_index];
1113 if (user_index == -1) {
1115 break; /* nothing received - leave for() loop */
1119 mtmsr (msr & ~(MSR_EE));
1121 length = hw_p->rx[user_index].data_len;
1123 /* Pass the packet up to the protocol layers. */
1124 /* NetReceive(NetRxPackets[rxIdx], length - 4); */
1125 /* NetReceive(NetRxPackets[i], length); */
1126 NetReceive (NetRxPackets[user_index], length - 4);
1127 /* Free Recv Buffer */
1128 hw_p->rx[user_index].ctrl |= MAL_RX_CTRL_EMPTY;
1129 /* Free rx buffer descriptor queue */
1130 hw_p->rx_ready[hw_p->rx_u_index] = -1;
1132 if (NUM_RX_BUFF == hw_p->rx_u_index)
1133 hw_p->rx_u_index = 0;
1135 #ifdef INFO_440_ENET
1136 hw_p->stats.pkts_handled++;
1139 mtmsr (msr); /* Enable IRQ's */
1142 hw_p->is_receiving = 0; /* tell driver */
1147 int ppc_440x_eth_initialize (bd_t * bis)
1149 static int virgin = 0;
1151 struct eth_device *dev;
1154 EMAC_440GX_HW_PST hw = NULL;
1156 mfsdr (sdr_pfc1, pfc1);
1157 pfc1 &= ~(0x01e00000);
1159 mtsdr (sdr_pfc1, pfc1);
1160 /* set phy num and mode */
1161 bis->bi_phynum[0] = CONFIG_PHY_ADDR;
1162 bis->bi_phynum[1] = CONFIG_PHY1_ADDR;
1163 bis->bi_phynum[2] = CONFIG_PHY2_ADDR;
1164 bis->bi_phynum[3] = CONFIG_PHY3_ADDR;
1165 bis->bi_phymode[0] = 0;
1166 bis->bi_phymode[1] = 0;
1167 bis->bi_phymode[2] = 2;
1168 bis->bi_phymode[3] = 2;
1170 for (eth_num = 0; eth_num < EMAC_NUM_DEV; eth_num++) {
1172 /* See if we can actually bring up the interface, otherwise, skip it */
1175 if (memcmp (bis->bi_enetaddr, "\0\0\0\0\0\0", 6) == 0) {
1176 bis->bi_phymode[eth_num] = BI_PHYMODE_NONE;
1181 if (memcmp (bis->bi_enet1addr, "\0\0\0\0\0\0", 6) == 0) {
1182 bis->bi_phymode[eth_num] = BI_PHYMODE_NONE;
1187 if (memcmp (bis->bi_enet2addr, "\0\0\0\0\0\0", 6) == 0) {
1188 bis->bi_phymode[eth_num] = BI_PHYMODE_NONE;
1193 if (memcmp (bis->bi_enet3addr, "\0\0\0\0\0\0", 6) == 0) {
1194 bis->bi_phymode[eth_num] = BI_PHYMODE_NONE;
1199 if (memcmp (bis->bi_enetaddr, "\0\0\0\0\0\0", 6) == 0) {
1200 bis->bi_phymode[eth_num] = BI_PHYMODE_NONE;
1206 /* Allocate device structure */
1207 dev = (struct eth_device *) malloc (sizeof (*dev));
1209 printf ("ppc_440x_eth_initialize: "
1210 "Cannot allocate eth_device %d\n", eth_num);
1214 /* Allocate our private use data */
1215 hw = (EMAC_440GX_HW_PST) malloc (sizeof (*hw));
1217 printf ("ppc_440x_eth_initialize: "
1218 "Cannot allocate private hw data for eth_device %d",
1227 memcpy (dev->enetaddr, bis->bi_enetaddr, 6);
1230 hw->hw_addr = 0x100;
1231 memcpy (dev->enetaddr, bis->bi_enet1addr, 6);
1234 hw->hw_addr = 0x400;
1235 memcpy (dev->enetaddr, bis->bi_enet2addr, 6);
1238 hw->hw_addr = 0x600;
1239 memcpy (dev->enetaddr, bis->bi_enet3addr, 6);
1243 memcpy (dev->enetaddr, bis->bi_enetaddr, 6);
1247 hw->devnum = eth_num;
1249 sprintf (dev->name, "ppc_440x_eth%d", eth_num);
1250 dev->priv = (void *) hw;
1251 dev->init = ppc_440x_eth_init;
1252 dev->halt = ppc_440x_eth_halt;
1253 dev->send = ppc_440x_eth_send;
1254 dev->recv = ppc_440x_eth_rx;
1257 /* set the MAL IER ??? names may change with new spec ??? */
1259 MAL_IER_DE | MAL_IER_NE | MAL_IER_TE |
1260 MAL_IER_OPBE | MAL_IER_PLBE;
1261 mtdcr (malesr, 0xffffffff); /* clear pending interrupts */
1262 mtdcr (maltxdeir, 0xffffffff); /* clear pending interrupts */
1263 mtdcr (malrxdeir, 0xffffffff); /* clear pending interrupts */
1264 mtdcr (malier, mal_ier);
1266 /* install MAL interrupt handler */
1267 irq_install_handler (VECNUM_MS,
1268 (interrupt_handler_t *) enetInt,
1270 irq_install_handler (VECNUM_MTE,
1271 (interrupt_handler_t *) enetInt,
1273 irq_install_handler (VECNUM_MRE,
1274 (interrupt_handler_t *) enetInt,
1276 irq_install_handler (VECNUM_TXDE,
1277 (interrupt_handler_t *) enetInt,
1279 irq_install_handler (VECNUM_RXDE,
1280 (interrupt_handler_t *) enetInt,
1287 } /* end for each supported device */
1290 #endif /* CONFIG_440 && CONFIG_NET_MULTI */