1 /*-----------------------------------------------------------------------------+
3 * This source code has been made available to you by IBM on an AS-IS
4 * basis. Anyone receiving this source is licensed under IBM
5 * copyrights to use it in any way he or she deems fit, including
6 * copying it, modifying it, compiling it, and redistributing it either
7 * with or without modifications. No license under IBM patents or
8 * patent applications is to be implied by the copyright license.
10 * Any user of this software should understand that IBM cannot provide
11 * technical support for this software and will not be responsible for
12 * any consequences resulting from the use of this software.
14 * Any person who transfers this source code or any derivative work
15 * must include the IBM copyright notice, this paragraph, and the
16 * preceding two paragraphs in the transferred software.
18 * COPYRIGHT I B M CORPORATION 1995
19 * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
20 *-----------------------------------------------------------------------------*/
21 /*-----------------------------------------------------------------------------+
23 * File Name: enetemac.c
25 * Function: Device driver for the ethernet EMAC3 macro on the 405GP.
31 * Date Description of Change BY
32 * --------- --------------------- ---
33 * 05-May-99 Created MKW
34 * 27-Jun-99 Clean up JWB
35 * 16-Jul-99 Added MAL error recovery and better IP packet handling MKW
36 * 29-Jul-99 Added Full duplex support MKW
37 * 06-Aug-99 Changed names for Mal CR reg MKW
38 * 23-Aug-99 Turned off SYE when running at 10Mbs MKW
39 * 24-Aug-99 Marked descriptor empty after call_xlc MKW
40 * 07-Sep-99 Set MAL RX buffer size reg to ENET_MAX_MTU_ALIGNED / 16 MCG
41 * to avoid chaining maximum sized packets. Push starting
42 * RX descriptor address up to the next cache line boundary.
43 * 16-Jan-00 Added support for booting with IP of 0x0 MKW
44 * 15-Mar-00 Updated enetInit() to enable broadcast addresses in the
45 * EMAC_RXM register. JWB
46 * 12-Mar-01 anne-sophie.harnois@nextream.fr
47 * - Variables are compatible with those already defined in
49 * - Receive buffer descriptor ring is used to send buffers
51 * - Info print about send/received/handled packet number if
52 * INFO_405_ENET is set
53 * 17-Apr-01 stefan.roese@esd-electronics.com
54 * - MAL reset in "eth_halt" included
55 * - Enet speed and duplex output now in one line
56 * 08-May-01 stefan.roese@esd-electronics.com
57 * - MAL error handling added (eth_init called again)
58 * 13-Nov-01 stefan.roese@esd-electronics.com
59 * - Set IST bit in EMAC_M1 reg upon 100MBit or full duplex
60 * 04-Jan-02 stefan.roese@esd-electronics.com
61 * - Wait for PHY auto negotiation to complete added
62 * 06-Feb-02 stefan.roese@esd-electronics.com
63 * - Bug fixed in waiting for auto negotiation to complete
64 * 26-Feb-02 stefan.roese@esd-electronics.com
65 * - rx and tx buffer descriptors now allocated (no fixed address
67 * 17-Jun-02 stefan.roese@esd-electronics.com
68 * - MAL error debug printf 'M' removed (rx de interrupt may
69 * occur upon many incoming packets with only 4 rx buffers).
70 * 21-Nov-03 pavel.bartusek@sysgo.com
71 * - set ZMII bridge speed on 440
73 *-----------------------------------------------------------------------------*/
76 #include <asm/processor.h>
79 #include <405gp_enet.h>
86 #if defined(CONFIG_405GP) || defined(CONFIG_405EP) || \
87 ( defined(CONFIG_440) && !defined(CONFIG_NET_MULTI))
89 #if !defined(CONFIG_NET_MULTI) || !defined(CONFIG_405EP)
90 /* 405GP, 440 with !CONFIG_NET_MULTI. For 440 only EMAC0 is supported */
91 #define EMAC_NUM_DEV 1
93 /* 440EP && CONFIG_NET_MULTI */
94 #define EMAC_NUM_DEV 2
97 #define EMAC_RESET_TIMEOUT 1000 /* 1000 ms reset timeout */
98 #define PHY_AUTONEGOTIATE_TIMEOUT 4000 /* 4000 ms autonegotiate timeout */
100 /* Ethernet Transmit and Receive Buffers */
102 * In the same way ENET_MAX_MTU and ENET_MAX_MTU_ALIGNED are set from
103 * PKTSIZE and PKTSIZE_ALIGN (include/net.h)
105 #define ENET_MAX_MTU PKTSIZE
106 #define ENET_MAX_MTU_ALIGNED PKTSIZE_ALIGN
108 /* define the number of channels implemented */
109 #define EMAC_RXCHL EMAC_NUM_DEV
110 #define EMAC_TXCHL EMAC_NUM_DEV
112 /*-----------------------------------------------------------------------------+
113 * Defines for MAL/EMAC interrupt conditions as reported in the UIC (Universal
114 * Interrupt Controller).
115 *-----------------------------------------------------------------------------*/
116 #define MAL_UIC_ERR ( UIC_MAL_SERR | UIC_MAL_TXDE | UIC_MAL_RXDE)
117 #define MAL_UIC_DEF (UIC_MAL_RXEOB | MAL_UIC_ERR)
118 #define EMAC_UIC_DEF UIC_ENET
119 #define EMAC_UIC_DEF1 UIC_ENET1
120 #define SEL_UIC_DEF(p) (p ? UIC_ENET1 : UIC_ENET )
123 /*-----------------------------------------------------------------------------+
124 * Global variables. TX and RX descriptors and buffers.
125 *-----------------------------------------------------------------------------*/
127 static uint32_t mal_ier;
129 #if !defined(CONFIG_NET_MULTI)
130 struct eth_device *emac0_dev;
133 /*-----------------------------------------------------------------------------+
134 * Prototypes and externals.
135 *-----------------------------------------------------------------------------*/
136 static void enet_rcv (struct eth_device *dev, unsigned long malisr);
138 int enetInt (struct eth_device *dev);
139 static void mal_err (struct eth_device *dev, unsigned long isr,
140 unsigned long uic, unsigned long maldef,
141 unsigned long mal_errr);
142 static void emac_err (struct eth_device *dev, unsigned long isr);
144 /*-----------------------------------------------------------------------------+
146 | Disable MAL channel, and EMACn
149 +-----------------------------------------------------------------------------*/
150 static void ppc_4xx_eth_halt (struct eth_device *dev)
152 EMAC_405_HW_PST hw_p = dev->priv;
153 uint32_t failsafe = 10000;
155 mtdcr (malier, 0x00000000); /* disable mal interrupts */
156 out32 (EMAC_IER + hw_p->hw_addr, 0x00000000); /* disable emac interrupts */
158 /* 1st reset MAL channel */
159 /* Note: writing a 0 to a channel has no effect */
160 mtdcr (maltxcarr, (MAL_CR_MMSR >> (hw_p->devnum * 2)));
161 mtdcr (malrxcarr, (MAL_CR_MMSR >> hw_p->devnum));
164 while (mfdcr (malrxcasr) & (MAL_CR_MMSR >> hw_p->devnum)) {
165 udelay (1000); /* Delay 1 MS so as not to hammer the register */
173 out32 (EMAC_M0 + hw_p->hw_addr, EMAC_M0_SRST);
175 hw_p->print_speed = 1; /* print speed message again next time */
180 static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
186 unsigned long duplex;
187 unsigned long failsafe;
189 unsigned short devnum;
190 unsigned short reg_short;
192 EMAC_405_HW_PST hw_p = dev->priv;
193 /* before doing anything, figure out if we have a MAC address */
195 if (memcmp (dev->enetaddr, "\0\0\0\0\0\0", 6) == 0)
199 mtmsr (msr & ~(MSR_EE)); /* disable interrupts */
201 devnum = hw_p->devnum;
206 * hw_p->stats.pkts_handled <= hw_p->stats.pkts_rx <= hw_p->stats.pkts_handled+PKTBUFSRX
207 * In the most cases hw_p->stats.pkts_handled = hw_p->stats.pkts_rx, but it
208 * is possible that new packets (without relationship with
209 * current transfer) have got the time to arrived before
210 * netloop calls eth_halt
212 printf ("About preceeding transfer (eth%d):\n"
213 "- Sent packet number %d\n"
214 "- Received packet number %d\n"
215 "- Handled packet number %d\n",
218 hw_p->stats.pkts_rx, hw_p->stats.pkts_handled);
220 hw_p->stats.pkts_tx = 0;
221 hw_p->stats.pkts_rx = 0;
222 hw_p->stats.pkts_handled = 0;
226 mtdcr (malmcr, MAL_CR_MMSR);
228 while (mfdcr (malmcr) & MAL_CR_MMSR) {
230 #if defined(CONFIG_440)
232 out32 (ZMII_FER, ZMII_RMII | ZMII_MDI0);
233 #endif /* CONFIG_440 */
235 /* MAL Channel RESET */
236 /* 1st reset MAL channel */
237 /* Note: writing a 0 to a channel has no effect */
238 mtdcr (maltxcarr, (MAL_TXRX_CASR >> (hw_p->devnum * 2)));
239 mtdcr (malrxcarr, (MAL_TXRX_CASR >> hw_p->devnum));
242 /* TBS: should have udelay and failsafe here */
245 while (mfdcr (malrxcasr) & (MAL_CR_MMSR >> hw_p->devnum)) {
246 udelay (1000); /* Delay 1 MS so as not to hammer the register */
253 hw_p->tx_err_index = 0; /* Transmit Error Index for tx_err_log */
254 hw_p->rx_err_index = 0; /* Receive Error Index for rx_err_log */
256 hw_p->rx_slot = 0; /* MAL Receive Slot */
257 hw_p->rx_i_index = 0; /* Receive Interrupt Queue Index */
258 hw_p->rx_u_index = 0; /* Receive User Queue Index */
260 hw_p->tx_slot = 0; /* MAL Transmit Slot */
261 hw_p->tx_i_index = 0; /* Transmit Interrupt Queue Index */
262 hw_p->tx_u_index = 0; /* Transmit User Queue Index */
264 __asm__ volatile ("eieio");
266 /* reset emac so we have access to the phy */
268 out32 (EMAC_M0 + hw_p->hw_addr, EMAC_M0_SRST);
269 __asm__ volatile ("eieio");
272 while ((in32 (EMAC_M0 + hw_p->hw_addr) & (EMAC_M0_SRST)) && failsafe) {
277 #if defined(CONFIG_NET_MULTI)
278 reg = hw_p->devnum ? CONFIG_PHY1_ADDR : CONFIG_PHY_ADDR;
280 reg = CONFIG_PHY_ADDR;
282 /* wait for PHY to complete auto negotiation */
284 #ifndef CONFIG_CS8952_PHY
285 miiphy_read (reg, PHY_BMSR, ®_short);
288 * Wait if PHY is capable of autonegotiation and autonegotiation is not complete
290 if ((reg_short & PHY_BMSR_AUTN_ABLE)
291 && !(reg_short & PHY_BMSR_AUTN_COMP)) {
292 puts ("Waiting for PHY auto negotiation to complete");
294 while (!(reg_short & PHY_BMSR_AUTN_COMP)) {
298 if (i > PHY_AUTONEGOTIATE_TIMEOUT) {
299 puts (" TIMEOUT !\n");
303 if ((i++ % 1000) == 0) {
306 udelay (1000); /* 1 ms */
307 miiphy_read (reg, PHY_BMSR, ®_short);
310 udelay (500000); /* another 500 ms (results in faster booting) */
313 speed = miiphy_speed (reg);
314 duplex = miiphy_duplex (reg);
316 if (hw_p->print_speed) {
317 hw_p->print_speed = 0;
318 printf ("ENET Speed is %d Mbps - %s duplex connection\n",
319 (int) speed, (duplex == HALF) ? "HALF" : "FULL");
322 #if defined(CONFIG_440)
323 /* Errata 1.12: MAL_1 -- Disable MAL bursting */
324 if( get_pvr() == PVR_440GP_RB)
325 mtdcr (malmcr, MAL_CR_OPBBL | MAL_CR_LEA | MAL_CR_PLBLT_DEFAULT);
328 mtdcr (malmcr, MAL_CR_PLBB | MAL_CR_OPBBL | MAL_CR_LEA | MAL_CR_PLBLT_DEFAULT);
331 /* Free "old" buffers */
332 if (hw_p->alloc_tx_buf)
333 free (hw_p->alloc_tx_buf);
334 if (hw_p->alloc_rx_buf)
335 free (hw_p->alloc_rx_buf);
338 * Malloc MAL buffer desciptors, make sure they are
339 * aligned on cache line boundary size
340 * (401/403/IOP480 = 16, 405 = 32)
341 * and doesn't cross cache block boundaries.
344 (mal_desc_t *) malloc ((sizeof (mal_desc_t) * NUM_TX_BUFF) +
345 ((2 * CFG_CACHELINE_SIZE) - 2));
346 if (((int) hw_p->alloc_tx_buf & CACHELINE_MASK) != 0) {
348 (mal_desc_t *) ((int) hw_p->alloc_tx_buf +
351 alloc_tx_buf & CACHELINE_MASK));
353 hw_p->tx = hw_p->alloc_tx_buf;
357 (mal_desc_t *) malloc ((sizeof (mal_desc_t) * NUM_RX_BUFF) +
358 ((2 * CFG_CACHELINE_SIZE) - 2));
359 if (((int) hw_p->alloc_rx_buf & CACHELINE_MASK) != 0) {
361 (mal_desc_t *) ((int) hw_p->alloc_rx_buf +
364 alloc_rx_buf & CACHELINE_MASK));
366 hw_p->rx = hw_p->alloc_rx_buf;
369 for (i = 0; i < NUM_TX_BUFF; i++) {
370 hw_p->tx[i].ctrl = 0;
371 hw_p->tx[i].data_len = 0;
372 if (hw_p->first_init == 0)
374 (char *) malloc (ENET_MAX_MTU_ALIGNED);
375 hw_p->tx[i].data_ptr = hw_p->txbuf_ptr;
376 if ((NUM_TX_BUFF - 1) == i)
377 hw_p->tx[i].ctrl |= MAL_TX_CTRL_WRAP;
378 hw_p->tx_run[i] = -1;
380 printf ("TX_BUFF %d @ 0x%08lx\n", i,
381 (ulong) hw_p->tx[i].data_ptr);
385 for (i = 0; i < NUM_RX_BUFF; i++) {
386 hw_p->rx[i].ctrl = 0;
387 hw_p->rx[i].data_len = 0;
388 /* rx[i].data_ptr = (char *) &rx_buff[i]; */
389 hw_p->rx[i].data_ptr = (char *) NetRxPackets[i];
390 if ((NUM_RX_BUFF - 1) == i)
391 hw_p->rx[i].ctrl |= MAL_RX_CTRL_WRAP;
392 hw_p->rx[i].ctrl |= MAL_RX_CTRL_EMPTY | MAL_RX_CTRL_INTR;
393 hw_p->rx_ready[i] = -1;
395 printf ("RX_BUFF %d @ 0x%08lx\n", i, (ulong) rx[i].data_ptr);
400 reg |= dev->enetaddr[0]; /* set high address */
402 reg |= dev->enetaddr[1];
404 out32 (EMAC_IAH + hw_p->hw_addr, reg);
407 reg |= dev->enetaddr[2]; /* set low address */
409 reg |= dev->enetaddr[3];
411 reg |= dev->enetaddr[4];
413 reg |= dev->enetaddr[5];
415 out32 (EMAC_IAL + hw_p->hw_addr, reg);
418 /* setup MAL tx & rx channel pointers */
419 /* For 405EP, the EMAC1 tx channel 0 is MAL tx channel 2 */
420 mtdcr (maltxctp2r, hw_p->tx);
421 mtdcr (malrxctp1r, hw_p->rx);
422 /* set RX buffer size */
423 mtdcr (malrcbs1, ENET_MAX_MTU_ALIGNED / 16);
427 /* setup MAL tx & rx channel pointers */
428 mtdcr (maltxctp0r, hw_p->tx);
429 mtdcr (malrxctp0r, hw_p->rx);
430 /* set RX buffer size */
431 mtdcr (malrcbs0, ENET_MAX_MTU_ALIGNED / 16);
435 /* Enable MAL transmit and receive channels */
436 mtdcr (maltxcasr, (MAL_TXRX_CASR >> (hw_p->devnum * 2)));
437 mtdcr (malrxcasr, (MAL_TXRX_CASR >> hw_p->devnum));
439 /* set transmit enable & receive enable */
440 out32 (EMAC_M0 + hw_p->hw_addr, EMAC_M0_TXE | EMAC_M0_RXE);
442 /* set receive fifo to 4k and tx fifo to 2k */
443 mode_reg = in32 (EMAC_M1 + hw_p->hw_addr);
444 mode_reg |= EMAC_M1_RFS_4K | EMAC_M1_TX_FIFO_2K;
447 if (speed == _100BASET)
448 mode_reg = mode_reg | EMAC_M1_MF_100MBPS | EMAC_M1_IST;
450 mode_reg = mode_reg & ~0x00C00000; /* 10 MBPS */
452 mode_reg = mode_reg | 0x80000000 | EMAC_M1_IST;
454 out32 (EMAC_M1 + hw_p->hw_addr, mode_reg);
456 #if defined(CONFIG_440)
457 /* set speed in the ZMII bridge */
458 if (speed == _100BASET)
459 out32(ZMII_SSR, in32(ZMII_SSR) | 0x10000000);
461 out32(ZMII_SSR, in32(ZMII_SSR) & ~0x10000000);
464 /* Enable broadcast and indvidual address */
465 /* TBS: enabling runts as some misbehaved nics will send runts */
466 out32 (EMAC_RXM + hw_p->hw_addr, EMAC_RMR_BAE | EMAC_RMR_IAE);
468 /* we probably need to set the tx mode1 reg? maybe at tx time */
470 /* set transmit request threshold register */
471 out32 (EMAC_TRTR + hw_p->hw_addr, 0x18000000); /* 256 byte threshold */
473 #if defined(CONFIG_440)
474 /* 440GP has a 64 byte burst length */
475 out32 (EMAC_RX_HI_LO_WMARK + hw_p->hw_addr, 0x0f002000);
476 out32 (EMAC_TXM1 + hw_p->hw_addr, 0xf8640000);
478 /* 405s have a 16 byte burst length */
479 out32 (EMAC_RX_HI_LO_WMARK + hw_p->hw_addr, 0x0f002000);
484 out32 (EMAC_I_FRAME_GAP_REG + hw_p->hw_addr, 0x00000008);
487 hw_p->emac_ier = EMAC_ISR_PTLE | EMAC_ISR_BFCS |
488 EMAC_ISR_ORE | EMAC_ISR_IRE;
489 if (speed == _100BASET)
490 hw_p->emac_ier = hw_p->emac_ier | EMAC_ISR_SYE;
492 out32 (EMAC_ISR + hw_p->hw_addr, 0xffffffff); /* clear pending interrupts */
493 out32 (EMAC_IER + hw_p->hw_addr, hw_p->emac_ier);
495 if (hw_p->first_init == 0) {
497 * Connect interrupt service routines
499 #if !defined(CONFIG_405EP)
500 /* 405EP has one EWU interrupt */
501 irq_install_handler (VECNUM_EWU0 + (hw_p->devnum * 2),
502 (interrupt_handler_t *) enetInt, dev);
504 irq_install_handler (VECNUM_ETH0 + (hw_p->devnum * 2),
505 (interrupt_handler_t *) enetInt, dev);
508 mtmsr (msr); /* enable interrupts again */
511 hw_p->first_init = 1;
517 static int ppc_4xx_eth_send (struct eth_device *dev, volatile void *ptr, int len)
519 struct enet_frame *ef_ptr;
520 ulong time_start, time_now;
521 unsigned long temp_txm0;
522 EMAC_405_HW_PST hw_p = dev->priv;
524 ef_ptr = (struct enet_frame *) ptr;
526 /*-----------------------------------------------------------------------+
527 * Copy in our address into the frame.
528 *-----------------------------------------------------------------------*/
529 (void) memcpy (ef_ptr->source_addr, dev->enetaddr, ENET_ADDR_LENGTH);
531 /*-----------------------------------------------------------------------+
532 * If frame is too long or too short, modify length.
533 *-----------------------------------------------------------------------*/
534 /* TBS: where does the fragment go???? */
535 if (len > ENET_MAX_MTU)
538 /* memcpy ((void *) &tx_buff[tx_slot], (const void *) ptr, len); */
539 memcpy ((void *) hw_p->txbuf_ptr, (const void *) ptr, len);
541 /*-----------------------------------------------------------------------+
542 * set TX Buffer busy, and send it
543 *-----------------------------------------------------------------------*/
544 hw_p->tx[hw_p->tx_slot].ctrl = (MAL_TX_CTRL_LAST |
545 EMAC_TX_CTRL_GFCS | EMAC_TX_CTRL_GP) &
546 ~(EMAC_TX_CTRL_ISA | EMAC_TX_CTRL_RSA);
547 if ((NUM_TX_BUFF - 1) == hw_p->tx_slot)
548 hw_p->tx[hw_p->tx_slot].ctrl |= MAL_TX_CTRL_WRAP;
550 hw_p->tx[hw_p->tx_slot].data_len = (short) len;
551 hw_p->tx[hw_p->tx_slot].ctrl |= MAL_TX_CTRL_READY;
553 __asm__ volatile ("eieio");
555 out32 (EMAC_TXM0 + hw_p->hw_addr,
556 in32 (EMAC_TXM0 + hw_p->hw_addr) | EMAC_TXM0_GNP0);
558 hw_p->stats.pkts_tx++;
561 /*-----------------------------------------------------------------------+
562 * poll unitl the packet is sent and then make sure it is OK
563 *-----------------------------------------------------------------------*/
564 time_start = get_timer (0);
566 temp_txm0 = in32 (EMAC_TXM0 + hw_p->hw_addr);
567 /* loop until either TINT turns on or 3 seconds elapse */
568 if ((temp_txm0 & EMAC_TXM0_GNP0) != 0) {
569 /* transmit is done, so now check for errors
570 * If there is an error, an interrupt should
571 * happen when we return
573 time_now = get_timer (0);
574 if ((time_now - time_start) > 3000) {
583 #if defined(CONFIG_440)
584 int enetInt (struct eth_device *dev)
587 int rc = -1; /* default to not us */
588 unsigned long mal_isr;
589 unsigned long emac_isr = 0;
590 unsigned long mal_rx_eob;
591 unsigned long my_uic0msr, my_uic1msr;
592 EMAC_405_HW_PST hw_p;
595 * Because the mal is generic, we need to get the current
598 #if defined(CONFIG_NET_MULTI)
605 /* enter loop that stays in interrupt code until nothing to service */
609 my_uic0msr = mfdcr (uic0msr);
610 my_uic1msr = mfdcr (uic1msr);
612 if (!(my_uic0msr & UIC_MRE)
613 && !(my_uic1msr & (UIC_ETH0 | UIC_MS | UIC_MTDE | UIC_MRDE))) {
618 /* get and clear controller status interrupts */
619 /* look at Mal and EMAC interrupts */
620 if ((my_uic0msr & UIC_MRE)
621 || (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) {
622 /* we have a MAL interrupt */
623 mal_isr = mfdcr (malesr);
624 /* look for mal error */
625 if (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE)) {
626 mal_err (dev, mal_isr, my_uic0msr, MAL_UIC_DEF, MAL_UIC_ERR);
631 if (UIC_ETH0 & my_uic1msr) { /* look for EMAC errors */
632 emac_isr = in32 (EMAC_ISR + hw_p->hw_addr);
633 if ((hw_p->emac_ier & emac_isr) != 0) {
634 emac_err (dev, emac_isr);
639 if ((hw_p->emac_ier & emac_isr)
640 || (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) {
641 mtdcr (uic0sr, UIC_MRE); /* Clear */
642 mtdcr (uic1sr, UIC_ETH0 | UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */
643 return (rc); /* we had errors so get out */
646 /* handle MAL RX EOB interupt from a receive */
647 /* check for EOB on valid channels */
648 if (my_uic0msr & UIC_MRE) {
649 mal_rx_eob = mfdcr (malrxeobisr);
650 if ((mal_rx_eob & (0x80000000 >> hw_p->devnum)) != 0) { /* call emac routine for channel 0 */
652 mtdcr(malrxeobisr, mal_rx_eob); */
653 enet_rcv (dev, emac_isr);
654 /* indicate that we serviced an interrupt */
659 mtdcr (uic0sr, UIC_MRE); /* Clear */
660 mtdcr (uic1sr, UIC_ETH0 | UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */
666 #else /* CONFIG_440 */
668 int enetInt (struct eth_device *dev)
671 int rc = -1; /* default to not us */
672 unsigned long mal_isr;
673 unsigned long emac_isr = 0;
674 unsigned long mal_rx_eob;
675 unsigned long my_uicmsr;
677 EMAC_405_HW_PST hw_p;
680 * Because the mal is generic, we need to get the current
683 #if defined(CONFIG_NET_MULTI)
691 /* enter loop that stays in interrupt code until nothing to service */
695 my_uicmsr = mfdcr (uicmsr);
697 if ((my_uicmsr & (MAL_UIC_DEF | EMAC_UIC_DEF)) == 0) { /* not for us */
700 /* get and clear controller status interrupts */
701 /* look at Mal and EMAC interrupts */
702 if ((MAL_UIC_DEF & my_uicmsr) != 0) { /* we have a MAL interrupt */
703 mal_isr = mfdcr (malesr);
704 /* look for mal error */
705 if ((my_uicmsr & MAL_UIC_ERR) != 0) {
706 mal_err (dev, mal_isr, my_uicmsr, MAL_UIC_DEF, MAL_UIC_ERR);
712 /* port by port dispatch of emac interrupts */
714 if ((SEL_UIC_DEF(hw_p->devnum) & my_uicmsr) != 0) { /* look for EMAC errors */
715 emac_isr = in32 (EMAC_ISR + hw_p->hw_addr);
716 if ((hw_p->emac_ier & emac_isr) != 0) {
717 emac_err (dev, emac_isr);
722 if (((hw_p->emac_ier & emac_isr) != 0) || ((MAL_UIC_ERR & my_uicmsr) != 0)) {
723 mtdcr (uicsr, MAL_UIC_DEF | SEL_UIC_DEF(hw_p->devnum)); /* Clear */
724 return (rc); /* we had errors so get out */
727 /* handle MAX TX EOB interrupt from a tx */
728 if (my_uicmsr & UIC_MAL_TXEOB) {
729 mal_rx_eob = mfdcr (maltxeobisr);
730 mtdcr (maltxeobisr, mal_rx_eob);
731 mtdcr (uicsr, UIC_MAL_TXEOB);
733 /* handle MAL RX EOB interupt from a receive */
734 /* check for EOB on valid channels */
735 if (my_uicmsr & UIC_MAL_RXEOB)
737 mal_rx_eob = mfdcr (malrxeobisr);
738 if ((mal_rx_eob & (0x80000000 >> hw_p->devnum)) != 0) { /* call emac routine for channel x */
740 mtdcr(malrxeobisr, mal_rx_eob); */
741 enet_rcv (dev, emac_isr);
742 /* indicate that we serviced an interrupt */
747 mtdcr (uicsr, MAL_UIC_DEF|EMAC_UIC_DEF|EMAC_UIC_DEF1); /* Clear */
754 /*-----------------------------------------------------------------------------+
756 *-----------------------------------------------------------------------------*/
757 static void mal_err (struct eth_device *dev, unsigned long isr,
758 unsigned long uic, unsigned long maldef,
759 unsigned long mal_errr)
761 EMAC_405_HW_PST hw_p = dev->priv;
763 mtdcr (malesr, isr); /* clear interrupt */
765 /* clear DE interrupt */
766 mtdcr (maltxdeir, 0xC0000000);
767 mtdcr (malrxdeir, 0x80000000);
770 printf ("\nMAL error occured.... ISR = %lx UIC = = %lx MAL_DEF = %lx MAL_ERR= %lx \n", isr, uic, maldef, mal_errr);
773 eth_init (hw_p->bis); /* start again... */
776 /*-----------------------------------------------------------------------------+
778 *-----------------------------------------------------------------------------*/
779 static void emac_err (struct eth_device *dev, unsigned long isr)
781 EMAC_405_HW_PST hw_p = dev->priv;
783 printf ("EMAC%d error occured.... ISR = %lx\n", hw_p->devnum, isr);
784 out32 (EMAC_ISR + hw_p->hw_addr, isr);
787 /*-----------------------------------------------------------------------------+
788 * enet_rcv() handles the ethernet receive data
789 *-----------------------------------------------------------------------------*/
790 static void enet_rcv (struct eth_device *dev, unsigned long malisr)
792 struct enet_frame *ef_ptr;
793 unsigned long data_len;
794 unsigned long rx_eob_isr;
795 EMAC_405_HW_PST hw_p = dev->priv;
801 rx_eob_isr = mfdcr (malrxeobisr);
802 if ((0x80000000 >> hw_p->devnum) & rx_eob_isr) {
804 mtdcr (malrxeobisr, rx_eob_isr);
807 while (1) { /* do all */
810 if ((MAL_RX_CTRL_EMPTY & hw_p->rx[i].ctrl)
811 || (loop_count >= NUM_RX_BUFF))
815 if (NUM_RX_BUFF == hw_p->rx_slot)
818 data_len = (unsigned long) hw_p->rx[i].data_len; /* Get len */
820 if (data_len > ENET_MAX_MTU) /* Check len */
823 if (EMAC_RX_ERRORS & hw_p->rx[i].ctrl) { /* Check Errors */
825 hw_p->stats.rx_err_log[hw_p->
828 hw_p->rx_err_index++;
829 if (hw_p->rx_err_index ==
834 } /* data_len < max mtu */
836 if (!data_len) { /* no data */
837 hw_p->rx[i].ctrl |= MAL_RX_CTRL_EMPTY; /* Free Recv Buffer */
839 hw_p->stats.data_len_err++; /* Error at Rx */
844 /* Check if user has already eaten buffer */
845 /* if not => ERROR */
846 else if (hw_p->rx_ready[hw_p->rx_i_index] != -1) {
847 if (hw_p->is_receiving)
848 printf ("ERROR : Receive buffers are full!\n");
851 hw_p->stats.rx_frames++;
852 hw_p->stats.rx += data_len;
853 ef_ptr = (struct enet_frame *) hw_p->rx[i].
856 hw_p->stats.pkts_rx++;
861 hw_p->rx_ready[hw_p->rx_i_index] = i;
863 if (NUM_RX_BUFF == hw_p->rx_i_index)
864 hw_p->rx_i_index = 0;
866 /* printf("X"); /|* test-only *|/ */
869 * free receive buffer only when
870 * buffer has been handled (eth_rx)
871 rx[i].ctrl |= MAL_RX_CTRL_EMPTY;
875 } /* if EMACK_RXCHL */
879 static int ppc_4xx_eth_rx (struct eth_device *dev)
884 EMAC_405_HW_PST hw_p = dev->priv;
886 hw_p->is_receiving = 1; /* tell driver */
890 * use ring buffer and
891 * get index from rx buffer desciptor queue
893 user_index = hw_p->rx_ready[hw_p->rx_u_index];
894 if (user_index == -1) {
896 break; /* nothing received - leave for() loop */
900 mtmsr (msr & ~(MSR_EE));
902 length = hw_p->rx[user_index].data_len;
904 /* Pass the packet up to the protocol layers. */
905 /* NetReceive(NetRxPackets[rxIdx], length - 4); */
906 /* NetReceive(NetRxPackets[i], length); */
907 NetReceive (NetRxPackets[user_index], length - 4);
908 /* Free Recv Buffer */
909 hw_p->rx[user_index].ctrl |= MAL_RX_CTRL_EMPTY;
910 /* Free rx buffer descriptor queue */
911 hw_p->rx_ready[hw_p->rx_u_index] = -1;
913 if (NUM_RX_BUFF == hw_p->rx_u_index)
914 hw_p->rx_u_index = 0;
917 hw_p->stats.pkts_handled++;
920 mtmsr (msr); /* Enable IRQ's */
923 hw_p->is_receiving = 0; /* tell driver */
928 static int virgin = 0;
929 int ppc_4xx_eth_initialize (bd_t * bis)
931 struct eth_device *dev;
934 EMAC_405_HW_PST hw = NULL;
936 for (eth_num = 0; eth_num < EMAC_NUM_DEV; eth_num++) {
938 /* Allocate device structure */
939 dev = (struct eth_device *) malloc (sizeof (*dev));
941 printf ("ppc_405x_eth_initialize: "
942 "Cannot allocate eth_device %d\n", eth_num);
945 /* Allocate our private use data */
946 hw = (EMAC_405_HW_PST) malloc (sizeof (*hw));
948 printf ("ppc_405x_eth_initialize: "
949 "Cannot allocate private hw data for eth_device %d",
958 memcpy (dev->enetaddr, bis->bi_enetaddr, 6);
960 #if defined(CONFIG_NET_MULTI)
963 memcpy (dev->enetaddr, bis->bi_enet1addr, 6);
968 memcpy (dev->enetaddr, bis->bi_enetaddr, 6);
972 hw->devnum = eth_num;
975 sprintf (dev->name, "ppc_405x_eth%d", eth_num);
976 dev->priv = (void *) hw;
977 dev->init = ppc_4xx_eth_init;
978 dev->halt = ppc_4xx_eth_halt;
979 dev->send = ppc_4xx_eth_send;
980 dev->recv = ppc_4xx_eth_rx;
983 /* set the MAL IER ??? names may change with new spec ??? */
985 MAL_IER_DE | MAL_IER_NE | MAL_IER_TE |
986 MAL_IER_OPBE | MAL_IER_PLBE;
987 mtdcr (malesr, 0xffffffff); /* clear pending interrupts */
988 mtdcr (maltxdeir, 0xffffffff); /* clear pending interrupts */
989 mtdcr (malrxdeir, 0xffffffff); /* clear pending interrupts */
990 mtdcr (malier, mal_ier);
992 #if defined(CONFIG_405EP)
993 /* 405EP has one EWU interrupt */
994 irq_install_handler (VECNUM_EWU0,
995 (interrupt_handler_t *) enetInt,
998 /* install MAL interrupt handler */
999 irq_install_handler (VECNUM_MS,
1000 (interrupt_handler_t *) enetInt,
1002 irq_install_handler (VECNUM_MTE,
1003 (interrupt_handler_t *) enetInt,
1005 irq_install_handler (VECNUM_MRE,
1006 (interrupt_handler_t *) enetInt,
1008 irq_install_handler (VECNUM_TXDE,
1009 (interrupt_handler_t *) enetInt,
1011 irq_install_handler (VECNUM_RXDE,
1012 (interrupt_handler_t *) enetInt,
1017 #if defined(CONFIG_NET_MULTI)
1023 } /* end for each supported device */
1028 #if !defined(CONFIG_NET_MULTI)
1029 void eth_halt (void) {
1031 ppc_4xx_eth_halt(emac0_dev);
1037 int eth_init (bd_t *bis)
1039 ppc_4xx_eth_initialize(bis);
1040 return(ppc_4xx_eth_init(emac0_dev, bis));
1043 int eth_send(volatile void *packet, int length)
1046 return (ppc_4xx_eth_send(emac0_dev, packet, length));
1051 return (ppc_4xx_eth_rx(emac0_dev));
1055 #endif /* CONFIG_405 */