2 * (C) Copyright 2004, Psyent Corporation <www.psyent.com>
3 * Scott McNutt <smcnutt@psyent.com>
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 /*************************************************************************
30 ************************************************************************/
36 /* ICACHE INIT -- only the icache line at the reset address
37 * is invalidated at reset. So the init must stay within
38 * the cache line size (8 words). If GERMS is used, we'll
39 * just be invalidating the cache a second time. If cache
40 * is not implemented initi behaves as nop.
42 movhi r4, %hi(CFG_ICACHELINE_SIZE)
43 ori r4, r4, %lo(CFG_ICACHELINE_SIZE)
44 movhi r5, %hi(CFG_ICACHE_SIZE)
45 ori r5, r5, %lo(CFG_ICACHE_SIZE)
51 /* INTERRUPTS -- for now, all interrupts masked and globally
54 wrctl status, r0 /* Disable interrupts */
55 wrctl ienable, r0 /* All disabled */
57 /* DCACHE INIT -- if dcache not implemented, initd behaves as
60 movhi r4, %hi(CFG_DCACHELINE_SIZE)
61 ori r4, r4, %lo(CFG_DCACHELINE_SIZE)
62 movhi r5, %hi(CFG_DCACHE_SIZE)
63 ori r5, r5, %lo(CFG_DCACHE_SIZE)
69 /* RELOCATE CODE, DATA & COMMAND TABLE -- the following code
70 * assumes code, data and the command table are all
71 * contiguous. This lets us relocate everything as a single
72 * block. Make sure the linker script matches this ;-)
75 _cur: movhi r5, %hi(_cur - _start)
76 ori r5, r5, %lo(_cur - _start)
77 sub r4, r4, r5 /* r4 <- cur _start */
80 ori r5, r5, %lo(_start) /* r5 <- linked _start */
84 ori r6, r6, %lo(_edata)
92 /* ZERO BSS/SBSS -- bss and sbss are assumed to be adjacent
93 * and between __bss_start and _end.
95 movhi r5, %hi(__bss_start)
96 ori r5, r5, %lo(__bss_start)
106 /* GLOBAL POINTER -- the global pointer is used to reference
107 * "small data" (see -G switch). The linker script must
108 * provide the gp address.
113 /* JUMP TO RELOC ADDR */
114 movhi r4, %hi(_reloc)
115 ori r4, r4, %lo(_reloc)
119 /* COPY EXCEPTION TRAMPOLINE -- copy the tramp to the
122 #if !defined(CONFIG_ROM_STUBS)
123 movhi r4, %hi(_except_start)
124 ori r4, r4, %lo(_except_start)
125 movhi r5, %hi(_except_end)
126 ori r5, r5, %lo(_except_end)
127 movhi r6, %hi(CFG_EXCEPTION_ADDR)
128 ori r6, r6, %lo(CFG_EXCEPTION_ADDR)
137 /* STACK INIT -- zero top two words for call back chain.
139 movhi sp, %hi(CFG_INIT_SP)
140 ori sp, sp, %lo(CFG_INIT_SP)
147 * Call board_init -- never returns
149 movhi r4, %hi(board_init@h)
150 ori r4, r4, %lo(board_init@h)
153 /* NEVER RETURNS -- but branch to the _start just
158 /* EXCEPTION TRAMPOLINE -- the following gets copied
159 * to the exception address.
162 movhi et, %hi(_exception)
163 ori et, et, %lo(_exception)
169 * dly_clks -- Nios2 (like Nios1) doesn't have a timebase in
170 * the core. For simple delay loops, we do our best by counting
171 * instruction cycles.
173 * Instruction performance varies based on the core. For cores
174 * with icache and static/dynamic branch prediction (II/f, II/s):
176 * Normal ALU (e.g. add, cmp, etc): 1 cycle
177 * Branch (correctly predicted, taken): 2 cycles
178 * Negative offset is predicted (II/s).
180 * For cores without icache and no branch prediction (II/e):
182 * Normal ALU (e.g. add, cmp, etc): 6 cycles
183 * Branch (no prediction): 6 cycles
185 * For simplicity, if an instruction cache is implemented we
186 * assume II/f or II/s. Otherwise, we use the II/e.
193 #if (CFG_ICACHE_SIZE > 0)
194 subi r4, r4, 3 /* 3 clocks/loop */
196 subi r4, r4, 12 /* 12 clocks/loop */
202 #if !defined(CONFIG_IDENT_STRING)
203 #define CONFIG_IDENT_STRING ""
206 .globl version_string
209 .ascii U_BOOT_VERSION
210 .ascii " (", __DATE__, " - ", __TIME__, ")"
211 .ascii CONFIG_IDENT_STRING, "\0"