2 * Copyright 2008 Freescale Semiconductor, Inc.
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * Version 2 as published by the Free Software Foundation.
10 #include <asm/fsl_ddr_sdram.h>
14 /* Board-specific functions defined in each board's ddr.c */
15 extern void fsl_ddr_board_options(memctl_options_t *popts,
17 unsigned int ctrl_num);
19 unsigned int populate_memctl_options(int all_DIMMs_registered,
20 memctl_options_t *popts,
22 unsigned int ctrl_num)
25 #if (CONFIG_NUM_DDR_CONTROLLERS > 1)
29 /* Chip select options. */
31 /* Pick chip-select local options. */
32 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
33 /* If not DDR2, odt_rd_cfg and odt_wr_cfg need to be 0. */
35 /* only for single CS? */
36 popts->cs_local_opts[i].odt_rd_cfg = 0;
38 popts->cs_local_opts[i].odt_wr_cfg = 1;
39 popts->cs_local_opts[i].auto_precharge = 0;
42 /* Pick interleaving mode. */
46 * 1 = interleaving between 2 controllers
48 popts->memctl_interleaving = 0;
54 * 3 = superbank (only if CS interleaving is enabled)
56 popts->memctl_interleaving_mode = 0;
59 * 0: cacheline: bit 30 of the 36-bit physical addr selects the memctl
60 * 1: page: bit to the left of the column bits selects the memctl
61 * 2: bank: bit to the left of the bank bits selects the memctl
62 * 3: superbank: bit to the left of the chip select selects the memctl
64 * NOTE: ba_intlv (rank interleaving) is independent of memory
65 * controller interleaving; it is only within a memory controller.
66 * Must use superbank interleaving if rank interleaving is used and
67 * memory controller interleaving is enabled.
74 * 0x60 = CS0,CS1 + CS2,CS3
75 * 0x04 = CS0,CS1,CS2,CS3
77 popts->ba_intlv_ctl = 0;
79 /* Memory Organization Parameters */
80 popts->registered_dimm_en = all_DIMMs_registered;
82 /* Operational Mode Paramters */
86 popts->ECC_mode = 1; /* 0 = disabled, 1 = enabled */
88 popts->ECC_mode = 0; /* 0 = disabled, 1 = enabled */
90 popts->ECC_init_using_memctl = 1; /* 0 = use DMA, 1 = use memctl */
97 #if defined(CONFIG_FSL_DDR1)
98 popts->DQS_config = 0;
99 #elif defined(CONFIG_FSL_DDR2) || defined(CONFIG_FSL_DDR3)
100 popts->DQS_config = 1;
103 /* Choose self-refresh during sleep. */
104 popts->self_refresh_in_sleep = 1;
106 /* Choose dynamic power management mode. */
107 popts->dynamic_power = 0;
109 /* 0 = 64-bit, 1 = 32-bit, 2 = 16-bit */
110 popts->data_bus_width = 0;
112 /* Choose burst length. */
113 #if defined(CONFIG_FSL_DDR3)
114 popts->OTF_burst_chop_en = 1; /* on-the-fly burst chop */
115 popts->burst_length = DDR_OTF; /* on-the-fly BC4 and BL8 */
117 popts->burst_length = DDR_BL4; /* has to be 4 for DDR2 */
120 /* Choose ddr controller address mirror mode */
121 #if defined(CONFIG_FSL_DDR3)
122 popts->mirrored_dimm = pdimm[0].mirrored_dimm;
125 /* Global Timing Parameters. */
126 debug("mclk_ps = %u ps\n", get_memory_clk_period_ps());
128 /* Pick a caslat override. */
129 popts->cas_latency_override = 0;
130 popts->cas_latency_override_value = 3;
131 if (popts->cas_latency_override) {
132 debug("using caslat override value = %u\n",
133 popts->cas_latency_override_value);
136 /* Decide whether to use the computed derated latency */
137 popts->use_derated_caslat = 0;
139 /* Choose an additive latency. */
140 popts->additive_latency_override = 0;
141 popts->additive_latency_override_value = 3;
142 if (popts->additive_latency_override) {
143 debug("using additive latency override value = %u\n",
144 popts->additive_latency_override_value);
150 * Factors to consider for 2T_EN:
151 * - number of DIMMs installed
152 * - number of components, number of active ranks
153 * - how much time you want to spend playing around
156 popts->threeT_en = 0;
159 * BSTTOPRE precharge interval
161 * Set this to 0 for global auto precharge
163 * FIXME: Should this be configured in picoseconds?
164 * Why it should be in ps: better understanding of this
165 * relative to actual DRAM timing parameters such as tRAS.
166 * e.g. tRAS(min) = 40 ns
168 popts->bstopre = 0x100;
170 /* Minimum CKE pulse width -- tCKE(MIN) */
171 popts->tCKE_clock_pulse_width_ps
172 = mclk_to_picos(FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR);
175 * Window for four activates -- tFAW
177 * FIXME: UM: applies only to DDR2/DDR3 with eight logical banks only
178 * FIXME: varies depending upon number of column addresses or data
179 * FIXME: width, was considering looking at pdimm->primary_sdram_width
181 #if defined(CONFIG_FSL_DDR1)
182 popts->tFAW_window_four_activates_ps = mclk_to_picos(1);
184 #elif defined(CONFIG_FSL_DDR2)
186 * x4/x8; some datasheets have 35000
187 * x16 wide columns only? Use 50000?
189 popts->tFAW_window_four_activates_ps = 37500;
191 #elif defined(CONFIG_FSL_DDR3)
192 popts->tFAW_window_four_activates_ps = pdimm[0].tFAW_ps;
196 #if defined(CONFIG_FSL_DDR3)
198 * due to ddr3 dimm is fly-by topology
199 * we suggest to enable write leveling to
200 * meet the tQDSS under different loading.
206 * Check interleaving configuration from environment.
207 * Please refer to doc/README.fsl-ddr for the detail.
209 * If memory controller interleaving is enabled, then the data
210 * bus widths must be programmed identically for the 2 memory
213 * XXX: Attempt to set both controllers to the same chip select
214 * interleaving mode. It will do a best effort to get the
215 * requested ranks interleaved together such that the result
216 * should be a subset of the requested configuration.
218 #if (CONFIG_NUM_DDR_CONTROLLERS > 1)
219 if ((p = getenv("memctl_intlv_ctl")) != NULL) {
220 if (pdimm[0].n_ranks == 0) {
221 printf("There is no rank on CS0. Because only rank on "
222 "CS0 and ranks chip-select interleaved with CS0"
223 " are controller interleaved, force non memory "
224 "controller interleaving\n");
225 popts->memctl_interleaving = 0;
227 popts->memctl_interleaving = 1;
228 if (strcmp(p, "cacheline") == 0)
229 popts->memctl_interleaving_mode =
230 FSL_DDR_CACHE_LINE_INTERLEAVING;
231 else if (strcmp(p, "page") == 0)
232 popts->memctl_interleaving_mode =
233 FSL_DDR_PAGE_INTERLEAVING;
234 else if (strcmp(p, "bank") == 0)
235 popts->memctl_interleaving_mode =
236 FSL_DDR_BANK_INTERLEAVING;
237 else if (strcmp(p, "superbank") == 0)
238 popts->memctl_interleaving_mode =
239 FSL_DDR_SUPERBANK_INTERLEAVING;
241 popts->memctl_interleaving_mode =
242 simple_strtoul(p, NULL, 0);
246 if( (p = getenv("ba_intlv_ctl")) != NULL) {
247 if (strcmp(p, "cs0_cs1") == 0)
248 popts->ba_intlv_ctl = FSL_DDR_CS0_CS1;
249 else if (strcmp(p, "cs2_cs3") == 0)
250 popts->ba_intlv_ctl = FSL_DDR_CS2_CS3;
251 else if (strcmp(p, "cs0_cs1_and_cs2_cs3") == 0)
252 popts->ba_intlv_ctl = FSL_DDR_CS0_CS1_AND_CS2_CS3;
253 else if (strcmp(p, "cs0_cs1_cs2_cs3") == 0)
254 popts->ba_intlv_ctl = FSL_DDR_CS0_CS1_CS2_CS3;
256 popts->ba_intlv_ctl = simple_strtoul(p, NULL, 0);
258 switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) {
259 case FSL_DDR_CS0_CS1_CS2_CS3:
260 case FSL_DDR_CS0_CS1:
261 if (pdimm[0].n_ranks != 2) {
262 popts->ba_intlv_ctl = 0;
263 printf("Not enough bank(chip-select) for "
264 "CS0+CS1, force non-interleaving!\n");
267 case FSL_DDR_CS2_CS3:
268 if (pdimm[1].n_ranks !=2){
269 popts->ba_intlv_ctl = 0;
270 printf("Not enough bank(CS) for CS2+CS3, "
271 "force non-interleaving!\n");
274 case FSL_DDR_CS0_CS1_AND_CS2_CS3:
275 if ((pdimm[0].n_ranks != 2)||(pdimm[1].n_ranks != 2)) {
276 popts->ba_intlv_ctl = 0;
277 printf("Not enough bank(CS) for CS0+CS1 or "
278 "CS2+CS3, force non-interleaving!\n");
282 popts->ba_intlv_ctl = 0;
288 fsl_ddr_board_options(popts, pdimm, ctrl_num);