2 * Copyright 2008 Freescale Semiconductor, Inc.
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * Version 2 as published by the Free Software Foundation.
10 * Generic driver for Freescale DDR/DDR2/DDR3 memory controller.
11 * Based on code from spd_sdram.c
12 * Author: James Yang [at freescale.com]
16 #include <asm/fsl_ddr_sdram.h>
20 extern void fsl_ddr_set_lawbar(
21 const common_timing_params_t *memctl_common_params,
22 unsigned int memctl_interleaved,
23 unsigned int ctrl_num);
25 /* processor specific function */
26 extern void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
27 unsigned int ctrl_num);
29 /* Board-specific functions defined in each board's ddr.c */
30 extern void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd,
31 unsigned int ctrl_num);
35 * - Same number of CONFIG_DIMM_SLOTS_PER_CTLR on each controller
36 * - Same memory data bus width on all controllers
40 * The memory controller and associated documentation use confusing
41 * terminology when referring to the orgranization of DRAM.
43 * Here is a terminology translation table:
45 * memory controller/documention |industry |this code |signals
46 * -------------------------------|-----------|-----------|-----------------
47 * physical bank/bank |rank |rank |chip select (CS)
48 * logical bank/sub-bank |bank |bank |bank address (BA)
49 * page/row |row |page |row address
50 * ??? |column |column |column address
52 * The naming confusion is further exacerbated by the descriptions of the
53 * memory controller interleaving feature, where accesses are interleaved
54 * _BETWEEN_ two seperate memory controllers. This is configured only in
55 * CS0_CONFIG[INTLV_CTL] of each memory controller.
57 * memory controller documentation | number of chip selects
58 * | per memory controller supported
59 * --------------------------------|-----------------------------------------
60 * cache line interleaving | 1 (CS0 only)
61 * page interleaving | 1 (CS0 only)
62 * bank interleaving | 1 (CS0 only)
63 * superbank interleraving | depends on bank (chip select)
64 * | interleraving [rank interleaving]
65 * | mode used on every memory controller
67 * Even further confusing is the existence of the interleaving feature
68 * _WITHIN_ each memory controller. The feature is referred to in
69 * documentation as chip select interleaving or bank interleaving,
70 * although it is configured in the DDR_SDRAM_CFG field.
72 * Name of field | documentation name | this code
73 * -----------------------------|-----------------------|------------------
74 * DDR_SDRAM_CFG[BA_INTLV_CTL] | Bank (chip select) | rank interleaving
79 const char *step_string_tbl[] = {
81 "STEP_COMPUTE_DIMM_PARMS",
82 "STEP_COMPUTE_COMMON_PARMS",
84 "STEP_ASSIGN_ADDRESSES",
90 const char * step_to_string(unsigned int step) {
92 unsigned int s = __ilog2(step);
95 return step_string_tbl[7];
97 return step_string_tbl[s];
101 int step_assign_addresses(fsl_ddr_info_t *pinfo,
102 unsigned int dbw_cap_adj[],
103 unsigned int *memctl_interleaving,
104 unsigned int *rank_interleaving)
109 * If a reduced data width is requested, but the SPD
110 * specifies a physically wider device, adjust the
111 * computed dimm capacities accordingly before
112 * assigning addresses.
114 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
115 unsigned int found = 0;
117 switch (pinfo->memctl_opts[i].data_bus_width) {
120 printf("can't handle 16-bit mode yet\n");
125 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
127 dw = pinfo->dimm_params[i][j].data_width;
128 if (pinfo->dimm_params[i][j].n_ranks
129 && (dw == 72 || dw == 64)) {
131 * FIXME: can't really do it
132 * like this because this just
133 * further reduces the memory
149 printf("unexpected data bus width "
150 "specified controller %u\n", i);
156 * Check if all controllers are configured for memory
157 * controller interleaving.
160 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
161 if (pinfo->memctl_opts[i].memctl_interleaving) {
166 *memctl_interleaving = 1;
168 printf("\nMemory controller interleaving enabled: ");
170 switch (pinfo->memctl_opts[0].memctl_interleaving_mode) {
171 case FSL_DDR_CACHE_LINE_INTERLEAVING:
172 printf("Cache-line interleaving!\n");
174 case FSL_DDR_PAGE_INTERLEAVING:
175 printf("Page interleaving!\n");
177 case FSL_DDR_BANK_INTERLEAVING:
178 printf("Bank interleaving!\n");
180 case FSL_DDR_SUPERBANK_INTERLEAVING:
181 printf("Super bank interleaving\n");
187 /* Check that all controllers are rank interleaving. */
189 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
190 if (pinfo->memctl_opts[i].ba_intlv_ctl) {
195 *rank_interleaving = 1;
197 printf("Bank(chip-select) interleaving enabled: ");
199 switch (pinfo->memctl_opts[0].ba_intlv_ctl &
200 FSL_DDR_CS0_CS1_CS2_CS3) {
201 case FSL_DDR_CS0_CS1_CS2_CS3:
202 printf("CS0+CS1+CS2+CS3\n");
204 case FSL_DDR_CS0_CS1:
207 case FSL_DDR_CS2_CS3:
210 case FSL_DDR_CS0_CS1_AND_CS2_CS3:
211 printf("CS0+CS1 and CS2+CS3\n");
217 if (*memctl_interleaving) {
219 phys_size_t total_mem_per_ctlr = 0;
222 * If interleaving between memory controllers,
223 * make each controller start at a base address
226 * Also, if bank interleaving (chip select
227 * interleaving) is enabled on each memory
228 * controller, CS0 needs to be programmed to
229 * cover the entire memory range on that memory
232 * Bank interleaving also implies that each
233 * addressed chip select is identical in size.
236 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
238 pinfo->common_timing_params[i].base_address =
240 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
241 unsigned long long cap
242 = pinfo->dimm_params[i][j].capacity;
244 pinfo->dimm_params[i][j].base_address = addr;
245 addr += (phys_addr_t)(cap >> dbw_cap_adj[i]);
246 total_mem_per_ctlr += cap >> dbw_cap_adj[i];
249 pinfo->common_timing_params[0].total_mem = total_mem_per_ctlr;
252 * Simple linear assignment if memory
253 * controllers are not interleaved.
255 phys_size_t cur_memsize = 0;
256 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
257 phys_size_t total_mem_per_ctlr = 0;
258 pinfo->common_timing_params[i].base_address =
259 (phys_addr_t)cur_memsize;
260 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
261 /* Compute DIMM base addresses. */
262 unsigned long long cap =
263 pinfo->dimm_params[i][j].capacity;
265 pinfo->dimm_params[i][j].base_address =
266 (phys_addr_t)cur_memsize;
267 cur_memsize += cap >> dbw_cap_adj[i];
268 total_mem_per_ctlr += cap >> dbw_cap_adj[i];
270 pinfo->common_timing_params[i].total_mem =
279 fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step)
282 unsigned int all_controllers_memctl_interleaving = 0;
283 unsigned int all_controllers_rank_interleaving = 0;
284 phys_size_t total_mem = 0;
286 fsl_ddr_cfg_regs_t *ddr_reg = pinfo->fsl_ddr_config_reg;
287 common_timing_params_t *timing_params = pinfo->common_timing_params;
289 /* data bus width capacity adjust shift amount */
290 unsigned int dbw_capacity_adjust[CONFIG_NUM_DDR_CONTROLLERS];
292 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
293 dbw_capacity_adjust[i] = 0;
296 debug("starting at step %u (%s)\n",
297 start_step, step_to_string(start_step));
299 switch (start_step) {
301 /* STEP 1: Gather all DIMM SPD data */
302 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
303 fsl_ddr_get_spd(pinfo->spd_installed_dimms[i], i);
306 case STEP_COMPUTE_DIMM_PARMS:
307 /* STEP 2: Compute DIMM parameters from SPD data */
309 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
310 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
312 generic_spd_eeprom_t *spd =
313 &(pinfo->spd_installed_dimms[i][j]);
314 dimm_params_t *pdimm =
315 &(pinfo->dimm_params[i][j]);
317 retval = compute_dimm_parameters(spd, pdimm, i);
319 printf("Error: compute_dimm_parameters"
320 " non-zero returned FATAL value "
321 "for memctl=%u dimm=%u\n", i, j);
325 debug("Warning: compute_dimm_parameters"
326 " non-zero return value for memctl=%u "
332 case STEP_COMPUTE_COMMON_PARMS:
334 * STEP 3: Compute a common set of timing parameters
335 * suitable for all of the DIMMs on each memory controller
337 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
338 debug("Computing lowest common DIMM"
339 " parameters for memctl=%u\n", i);
340 compute_lowest_common_dimm_parameters(
341 pinfo->dimm_params[i],
343 CONFIG_DIMM_SLOTS_PER_CTLR);
346 case STEP_GATHER_OPTS:
347 /* STEP 4: Gather configuration requirements from user */
348 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
349 debug("Reloading memory controller "
350 "configuration options for memctl=%u\n", i);
352 * This "reloads" the memory controller options
353 * to defaults. If the user "edits" an option,
354 * next_step points to the step after this,
355 * which is currently STEP_ASSIGN_ADDRESSES.
357 populate_memctl_options(
358 timing_params[i].all_DIMMs_registered,
359 &pinfo->memctl_opts[i],
360 pinfo->dimm_params[i], i);
363 case STEP_ASSIGN_ADDRESSES:
364 /* STEP 5: Assign addresses to chip selects */
365 step_assign_addresses(pinfo,
367 &all_controllers_memctl_interleaving,
368 &all_controllers_rank_interleaving);
370 case STEP_COMPUTE_REGS:
371 /* STEP 6: compute controller register values */
372 debug("FSL Memory ctrl cg register computation\n");
373 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
374 if (timing_params[i].ndimms_present == 0) {
375 memset(&ddr_reg[i], 0,
376 sizeof(fsl_ddr_cfg_regs_t));
380 compute_fsl_memctl_config_regs(
381 &pinfo->memctl_opts[i],
382 &ddr_reg[i], &timing_params[i],
383 pinfo->dimm_params[i],
384 dbw_capacity_adjust[i]);
391 /* Compute the total amount of memory. */
394 * If bank interleaving but NOT memory controller interleaving
395 * CS_BNDS describe the quantity of memory on each memory
396 * controller, so the total is the sum across.
398 if (!all_controllers_memctl_interleaving
399 && all_controllers_rank_interleaving) {
401 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
402 total_mem += timing_params[i].total_mem;
407 * Compute the amount of memory available just by
408 * looking for the highest valid CSn_BNDS value.
409 * This allows us to also experiment with using
410 * only CS0 when using dual-rank DIMMs.
412 unsigned int max_end = 0;
414 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
415 for (j = 0; j < CONFIG_CHIP_SELECTS_PER_CTRL; j++) {
416 fsl_ddr_cfg_regs_t *reg = &ddr_reg[i];
417 if (reg->cs[j].config & 0x80000000) {
419 end = reg->cs[j].bnds & 0xFFF;
427 #if !defined(CONFIG_PHYS_64BIT)
428 /* Check for 4G or more with a 32-bit phys_addr_t. Bad. */
429 if (max_end >= 0xff) {
430 printf("This U-Boot only supports < 4G of DDR\n");
431 printf("You could rebuild it with CONFIG_PHYS_64BIT\n");
432 return CONFIG_MAX_MEM_MAPPED;
436 total_mem = 1 + (((unsigned long long)max_end << 24ULL)
444 * fsl_ddr_sdram() -- this is the main function to be called by
445 * initdram() in the board file.
447 * It returns amount of memory configured in bytes.
449 phys_size_t fsl_ddr_sdram(void)
452 unsigned int memctl_interleaved;
453 phys_size_t total_memory;
456 /* Reset info structure. */
457 memset(&info, 0, sizeof(fsl_ddr_info_t));
459 /* Compute it once normally. */
460 total_memory = fsl_ddr_compute(&info, STEP_GET_SPD);
462 /* Check for memory controller interleaving. */
463 memctl_interleaved = 0;
464 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
465 memctl_interleaved +=
466 info.memctl_opts[i].memctl_interleaving;
469 if (memctl_interleaved) {
470 if (memctl_interleaved == CONFIG_NUM_DDR_CONTROLLERS) {
471 debug("memctl interleaving\n");
473 * Change the meaning of memctl_interleaved
476 memctl_interleaved = 1;
478 printf("Warning: memctl interleaving not "
479 "properly configured on all controllers\n");
480 memctl_interleaved = 0;
481 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++)
482 info.memctl_opts[i].memctl_interleaving = 0;
483 debug("Recomputing with memctl_interleaving off.\n");
484 total_memory = fsl_ddr_compute(&info,
485 STEP_ASSIGN_ADDRESSES);
489 /* Program configuration registers. */
490 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
491 debug("Programming controller %u\n", i);
492 if (info.common_timing_params[i].ndimms_present == 0) {
493 debug("No dimms present on controller %u; "
494 "skipping programming\n", i);
498 fsl_ddr_set_memctl_regs(&(info.fsl_ddr_config_reg[i]), i);
501 if (memctl_interleaved) {
502 const unsigned int ctrl_num = 0;
504 /* Only set LAWBAR1 if memory controller interleaving is on. */
505 fsl_ddr_set_lawbar(&info.common_timing_params[0],
506 memctl_interleaved, ctrl_num);
509 * Memory controller interleaving is NOT on;
510 * set each lawbar individually.
512 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
513 fsl_ddr_set_lawbar(&info.common_timing_params[i],
518 debug("total_memory = %llu\n", (u64)total_memory);