2 * Copyright 2008 Freescale Semiconductor, Inc.
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * Version 2 as published by the Free Software Foundation.
10 * Generic driver for Freescale DDR/DDR2/DDR3 memory controller.
11 * Based on code from spd_sdram.c
12 * Author: James Yang [at freescale.com]
16 #include <asm/fsl_ddr_sdram.h>
20 extern void fsl_ddr_set_lawbar(
21 const common_timing_params_t *memctl_common_params,
22 unsigned int memctl_interleaved,
23 unsigned int ctrl_num);
25 /* processor specific function */
26 extern void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
27 unsigned int ctrl_num);
29 /* Board-specific functions defined in each board's ddr.c */
30 extern void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd,
31 unsigned int ctrl_num);
35 * - Same number of CONFIG_DIMM_SLOTS_PER_CTLR on each controller
36 * - Same memory data bus width on all controllers
40 * The memory controller and associated documentation use confusing
41 * terminology when referring to the orgranization of DRAM.
43 * Here is a terminology translation table:
45 * memory controller/documention |industry |this code |signals
46 * -------------------------------|-----------|-----------|-----------------
47 * physical bank/bank |rank |rank |chip select (CS)
48 * logical bank/sub-bank |bank |bank |bank address (BA)
49 * page/row |row |page |row address
50 * ??? |column |column |column address
52 * The naming confusion is further exacerbated by the descriptions of the
53 * memory controller interleaving feature, where accesses are interleaved
54 * _BETWEEN_ two seperate memory controllers. This is configured only in
55 * CS0_CONFIG[INTLV_CTL] of each memory controller.
57 * memory controller documentation | number of chip selects
58 * | per memory controller supported
59 * --------------------------------|-----------------------------------------
60 * cache line interleaving | 1 (CS0 only)
61 * page interleaving | 1 (CS0 only)
62 * bank interleaving | 1 (CS0 only)
63 * superbank interleraving | depends on bank (chip select)
64 * | interleraving [rank interleaving]
65 * | mode used on every memory controller
67 * Even further confusing is the existence of the interleaving feature
68 * _WITHIN_ each memory controller. The feature is referred to in
69 * documentation as chip select interleaving or bank interleaving,
70 * although it is configured in the DDR_SDRAM_CFG field.
72 * Name of field | documentation name | this code
73 * -----------------------------|-----------------------|------------------
74 * DDR_SDRAM_CFG[BA_INTLV_CTL] | Bank (chip select) | rank interleaving
79 const char *step_string_tbl[] = {
81 "STEP_COMPUTE_DIMM_PARMS",
82 "STEP_COMPUTE_COMMON_PARMS",
84 "STEP_ASSIGN_ADDRESSES",
90 const char * step_to_string(unsigned int step) {
92 unsigned int s = __ilog2(step);
95 return step_string_tbl[7];
97 return step_string_tbl[s];
101 int step_assign_addresses(fsl_ddr_info_t *pinfo,
102 unsigned int dbw_cap_adj[],
103 unsigned int *memctl_interleaving,
104 unsigned int *rank_interleaving)
109 * If a reduced data width is requested, but the SPD
110 * specifies a physically wider device, adjust the
111 * computed dimm capacities accordingly before
112 * assigning addresses.
114 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
115 unsigned int found = 0;
117 switch (pinfo->memctl_opts[i].data_bus_width) {
120 printf("can't handle 16-bit mode yet\n");
125 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
127 dw = pinfo->dimm_params[i][j].data_width;
128 if (pinfo->dimm_params[i][j].n_ranks
129 && (dw == 72 || dw == 64)) {
131 * FIXME: can't really do it
132 * like this because this just
133 * further reduces the memory
149 printf("unexpected data bus width "
150 "specified controller %u\n", i);
156 * Check if all controllers are configured for memory
157 * controller interleaving.
160 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
161 if (pinfo->memctl_opts[i].memctl_interleaving) {
166 *memctl_interleaving = 1;
168 printf("\nMemory controller interleaving enabled: ");
170 switch (pinfo->memctl_opts[0].memctl_interleaving_mode) {
171 case FSL_DDR_CACHE_LINE_INTERLEAVING:
172 printf("Cache-line interleaving!\n");
174 case FSL_DDR_PAGE_INTERLEAVING:
175 printf("Page interleaving!\n");
177 case FSL_DDR_BANK_INTERLEAVING:
178 printf("Bank interleaving!\n");
180 case FSL_DDR_SUPERBANK_INTERLEAVING:
181 printf("Super bank interleaving\n");
187 /* Check that all controllers are rank interleaving. */
189 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
190 if (pinfo->memctl_opts[i].ba_intlv_ctl) {
195 *rank_interleaving = 1;
197 printf("Bank(chip-select) interleaving enabled: ");
199 switch (pinfo->memctl_opts[0].ba_intlv_ctl &
200 FSL_DDR_CS0_CS1_CS2_CS3) {
201 case FSL_DDR_CS0_CS1_CS2_CS3:
202 printf("CS0+CS1+CS2+CS3\n");
204 case FSL_DDR_CS0_CS1:
207 case FSL_DDR_CS2_CS3:
210 case FSL_DDR_CS0_CS1_AND_CS2_CS3:
211 printf("CS0+CS1 and CS2+CS3\n");
217 if (*memctl_interleaving) {
218 unsigned long long addr, total_mem_per_ctlr = 0;
220 * If interleaving between memory controllers,
221 * make each controller start at a base address
224 * Also, if bank interleaving (chip select
225 * interleaving) is enabled on each memory
226 * controller, CS0 needs to be programmed to
227 * cover the entire memory range on that memory
230 * Bank interleaving also implies that each
231 * addressed chip select is identical in size.
234 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
236 pinfo->common_timing_params[i].base_address = 0ull;
237 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
238 unsigned long long cap
239 = pinfo->dimm_params[i][j].capacity;
241 pinfo->dimm_params[i][j].base_address = addr;
242 addr += cap >> dbw_cap_adj[i];
243 total_mem_per_ctlr += cap >> dbw_cap_adj[i];
246 pinfo->common_timing_params[0].total_mem = total_mem_per_ctlr;
249 * Simple linear assignment if memory
250 * controllers are not interleaved.
252 unsigned long long cur_memsize = 0;
253 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
254 u64 total_mem_per_ctlr = 0;
255 pinfo->common_timing_params[i].base_address =
257 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
258 /* Compute DIMM base addresses. */
259 unsigned long long cap =
260 pinfo->dimm_params[i][j].capacity;
261 pinfo->dimm_params[i][j].base_address =
263 cur_memsize += cap >> dbw_cap_adj[i];
264 total_mem_per_ctlr += cap >> dbw_cap_adj[i];
266 pinfo->common_timing_params[i].total_mem =
275 fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step)
278 unsigned int all_controllers_memctl_interleaving = 0;
279 unsigned int all_controllers_rank_interleaving = 0;
280 unsigned long long total_mem = 0;
282 fsl_ddr_cfg_regs_t *ddr_reg = pinfo->fsl_ddr_config_reg;
283 common_timing_params_t *timing_params = pinfo->common_timing_params;
285 /* data bus width capacity adjust shift amount */
286 unsigned int dbw_capacity_adjust[CONFIG_NUM_DDR_CONTROLLERS];
288 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
289 dbw_capacity_adjust[i] = 0;
292 debug("starting at step %u (%s)\n",
293 start_step, step_to_string(start_step));
295 switch (start_step) {
297 /* STEP 1: Gather all DIMM SPD data */
298 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
299 fsl_ddr_get_spd(pinfo->spd_installed_dimms[i], i);
302 case STEP_COMPUTE_DIMM_PARMS:
303 /* STEP 2: Compute DIMM parameters from SPD data */
305 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
306 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
308 generic_spd_eeprom_t *spd =
309 &(pinfo->spd_installed_dimms[i][j]);
310 dimm_params_t *pdimm =
311 &(pinfo->dimm_params[i][j]);
313 retval = compute_dimm_parameters(spd, pdimm, i);
315 printf("Error: compute_dimm_parameters"
316 " non-zero returned FATAL value "
317 "for memctl=%u dimm=%u\n", i, j);
321 debug("Warning: compute_dimm_parameters"
322 " non-zero return value for memctl=%u "
328 case STEP_COMPUTE_COMMON_PARMS:
330 * STEP 3: Compute a common set of timing parameters
331 * suitable for all of the DIMMs on each memory controller
333 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
334 debug("Computing lowest common DIMM"
335 " parameters for memctl=%u\n", i);
336 compute_lowest_common_dimm_parameters(
337 pinfo->dimm_params[i],
339 CONFIG_DIMM_SLOTS_PER_CTLR);
342 case STEP_GATHER_OPTS:
343 /* STEP 4: Gather configuration requirements from user */
344 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
345 debug("Reloading memory controller "
346 "configuration options for memctl=%u\n", i);
348 * This "reloads" the memory controller options
349 * to defaults. If the user "edits" an option,
350 * next_step points to the step after this,
351 * which is currently STEP_ASSIGN_ADDRESSES.
353 populate_memctl_options(
354 timing_params[i].all_DIMMs_registered,
355 &pinfo->memctl_opts[i],
356 pinfo->dimm_params[i], i);
359 case STEP_ASSIGN_ADDRESSES:
360 /* STEP 5: Assign addresses to chip selects */
361 step_assign_addresses(pinfo,
363 &all_controllers_memctl_interleaving,
364 &all_controllers_rank_interleaving);
366 case STEP_COMPUTE_REGS:
367 /* STEP 6: compute controller register values */
368 debug("FSL Memory ctrl cg register computation\n");
369 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
370 if (timing_params[i].ndimms_present == 0) {
371 memset(&ddr_reg[i], 0,
372 sizeof(fsl_ddr_cfg_regs_t));
376 compute_fsl_memctl_config_regs(
377 &pinfo->memctl_opts[i],
378 &ddr_reg[i], &timing_params[i],
379 pinfo->dimm_params[i],
380 dbw_capacity_adjust[i]);
387 /* Compute the total amount of memory. */
390 * If bank interleaving but NOT memory controller interleaving
391 * CS_BNDS describe the quantity of memory on each memory
392 * controller, so the total is the sum across.
394 if (!all_controllers_memctl_interleaving
395 && all_controllers_rank_interleaving) {
397 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
398 total_mem += timing_params[i].total_mem;
403 * Compute the amount of memory available just by
404 * looking for the highest valid CSn_BNDS value.
405 * This allows us to also experiment with using
406 * only CS0 when using dual-rank DIMMs.
408 unsigned int max_end = 0;
410 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
411 for (j = 0; j < CONFIG_CHIP_SELECTS_PER_CTRL; j++) {
412 fsl_ddr_cfg_regs_t *reg = &ddr_reg[i];
413 if (reg->cs[j].config & 0x80000000) {
415 end = reg->cs[j].bnds & 0xFFF;
423 total_mem = 1 + (((unsigned long long)max_end << 24ULL)
431 * fsl_ddr_sdram() -- this is the main function to be called by
432 * initdram() in the board file.
434 * It returns amount of memory configured in bytes.
436 phys_size_t fsl_ddr_sdram(void)
439 unsigned int memctl_interleaved;
440 unsigned long long total_memory;
443 /* Reset info structure. */
444 memset(&info, 0, sizeof(fsl_ddr_info_t));
446 /* Compute it once normally. */
447 total_memory = fsl_ddr_compute(&info, STEP_GET_SPD);
449 /* Check for memory controller interleaving. */
450 memctl_interleaved = 0;
451 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
452 memctl_interleaved +=
453 info.memctl_opts[i].memctl_interleaving;
456 if (memctl_interleaved) {
457 if (memctl_interleaved == CONFIG_NUM_DDR_CONTROLLERS) {
458 debug("memctl interleaving\n");
460 * Change the meaning of memctl_interleaved
463 memctl_interleaved = 1;
465 printf("Warning: memctl interleaving not "
466 "properly configured on all controllers\n");
467 memctl_interleaved = 0;
468 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++)
469 info.memctl_opts[i].memctl_interleaving = 0;
470 debug("Recomputing with memctl_interleaving off.\n");
471 total_memory = fsl_ddr_compute(&info,
472 STEP_ASSIGN_ADDRESSES);
476 /* Program configuration registers. */
477 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
478 debug("Programming controller %u\n", i);
479 if (info.common_timing_params[i].ndimms_present == 0) {
480 debug("No dimms present on controller %u; "
481 "skipping programming\n", i);
485 fsl_ddr_set_memctl_regs(&(info.fsl_ddr_config_reg[i]), i);
488 if (memctl_interleaved) {
489 const unsigned int ctrl_num = 0;
491 /* Only set LAWBAR1 if memory controller interleaving is on. */
492 fsl_ddr_set_lawbar(&info.common_timing_params[0],
493 memctl_interleaved, ctrl_num);
496 * Memory controller interleaving is NOT on;
497 * set each lawbar individually.
499 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
500 fsl_ddr_set_lawbar(&info.common_timing_params[i],
505 debug("total_memory = %llu\n", total_memory);
507 #if !defined(CONFIG_PHYS_64BIT)
508 /* Check for 4G or more. Bad. */
509 if (total_memory >= (1ull << 32)) {
510 printf("Detected %lld MB of memory\n", total_memory >> 20);
511 printf("This U-Boot only supports < 4G of DDR\n");
512 printf("You could rebuild it with CONFIG_PHYS_64BIT\n");
513 total_memory = CONFIG_MAX_MEM_MAPPED;