2 * Copyright 2008 Freescale Semiconductor, Inc.
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * Version 2 as published by the Free Software Foundation.
10 * Generic driver for Freescale DDR/DDR2/DDR3 memory controller.
11 * Based on code from spd_sdram.c
12 * Author: James Yang [at freescale.com]
16 #include <asm/fsl_ddr_sdram.h>
20 extern unsigned int picos_to_mclk(unsigned int picos);
22 * Determine Rtt value.
24 * This should likely be either board or controller specific.
26 * Rtt(nominal) - DDR2:
31 * Rtt(nominal) - DDR3:
39 * FIXME: Apparently 8641 needs a value of 2
40 * FIXME: Old code seys if 667 MHz or higher, use 3 on 8572
42 * FIXME: There was some effort down this line earlier:
45 * for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL/2; i++) {
46 * if (popts->dimmslot[i].num_valid_cs
47 * && (popts->cs_local_opts[2*i].odt_rd_cfg
48 * || popts->cs_local_opts[2*i].odt_wr_cfg)) {
54 static inline int fsl_ddr_get_rtt(void)
58 #if defined(CONFIG_FSL_DDR1)
60 #elif defined(CONFIG_FSL_DDR2)
70 * compute the CAS write latency according to DDR3 spec
71 * CWL = 5 if tCK >= 2.5ns
72 * 6 if 2.5ns > tCK >= 1.875ns
73 * 7 if 1.875ns > tCK >= 1.5ns
74 * 8 if 1.5ns > tCK >= 1.25ns
76 static inline unsigned int compute_cas_write_latency(void)
79 const unsigned int mclk_ps = get_memory_clk_period_ps();
83 else if (mclk_ps >= 1875)
85 else if (mclk_ps >= 1500)
87 else if (mclk_ps >= 1250)
94 /* Chip Select Configuration (CSn_CONFIG) */
95 static void set_csn_config(int i, fsl_ddr_cfg_regs_t *ddr,
96 const memctl_options_t *popts,
97 const dimm_params_t *dimm_params)
99 unsigned int cs_n_en = 0; /* Chip Select enable */
100 unsigned int intlv_en = 0; /* Memory controller interleave enable */
101 unsigned int intlv_ctl = 0; /* Interleaving control */
102 unsigned int ap_n_en = 0; /* Chip select n auto-precharge enable */
103 unsigned int odt_rd_cfg = 0; /* ODT for reads configuration */
104 unsigned int odt_wr_cfg = 0; /* ODT for writes configuration */
105 unsigned int ba_bits_cs_n = 0; /* Num of bank bits for SDRAM on CSn */
106 unsigned int row_bits_cs_n = 0; /* Num of row bits for SDRAM on CSn */
107 unsigned int col_bits_cs_n = 0; /* Num of ocl bits for SDRAM on CSn */
109 /* Compute CS_CONFIG only for existing ranks of each DIMM. */
111 && (dimm_params[i/2].n_ranks == 1))
112 || (dimm_params[i/2].n_ranks == 2)) {
113 unsigned int n_banks_per_sdram_device;
116 /* These fields only available in CS0_CONFIG */
117 intlv_en = popts->memctl_interleaving;
118 intlv_ctl = popts->memctl_interleaving_mode;
120 ap_n_en = popts->cs_local_opts[i].auto_precharge;
121 odt_rd_cfg = popts->cs_local_opts[i].odt_rd_cfg;
122 odt_wr_cfg = popts->cs_local_opts[i].odt_wr_cfg;
123 n_banks_per_sdram_device
124 = dimm_params[i/2].n_banks_per_sdram_device;
125 ba_bits_cs_n = __ilog2(n_banks_per_sdram_device) - 2;
126 row_bits_cs_n = dimm_params[i/2].n_row_addr - 12;
127 col_bits_cs_n = dimm_params[i/2].n_col_addr - 8;
130 ddr->cs[i].config = (0
131 | ((cs_n_en & 0x1) << 31)
132 | ((intlv_en & 0x3) << 29)
133 | ((intlv_ctl & 0xf) << 24)
134 | ((ap_n_en & 0x1) << 23)
136 /* XXX: some implementation only have 1 bit starting at left */
137 | ((odt_rd_cfg & 0x7) << 20)
139 /* XXX: Some implementation only have 1 bit starting at left */
140 | ((odt_wr_cfg & 0x7) << 16)
142 | ((ba_bits_cs_n & 0x3) << 14)
143 | ((row_bits_cs_n & 0x7) << 8)
144 | ((col_bits_cs_n & 0x7) << 0)
146 debug("FSLDDR: cs[%d]_config = 0x%08x\n", i,ddr->cs[i].config);
149 /* Chip Select Configuration 2 (CSn_CONFIG_2) */
151 static void set_csn_config_2(int i, fsl_ddr_cfg_regs_t *ddr)
153 unsigned int pasr_cfg = 0; /* Partial array self refresh config */
155 ddr->cs[i].config_2 = ((pasr_cfg & 7) << 24);
156 debug("FSLDDR: cs[%d]_config_2 = 0x%08x\n", i, ddr->cs[i].config_2);
159 /* -3E = 667 CL5, -25 = CL6 800, -25E = CL5 800 */
161 #if !defined(CONFIG_FSL_DDR1)
163 * DDR SDRAM Timing Configuration 0 (TIMING_CFG_0)
165 * Avoid writing for DDR I. The new PQ38 DDR controller
166 * dreams up non-zero default values to be backwards compatible.
168 static void set_timing_cfg_0(fsl_ddr_cfg_regs_t *ddr)
170 unsigned char trwt_mclk = 0; /* Read-to-write turnaround */
171 unsigned char twrt_mclk = 0; /* Write-to-read turnaround */
172 /* 7.5 ns on -3E; 0 means WL - CL + BL/2 + 1 */
173 unsigned char trrt_mclk = 0; /* Read-to-read turnaround */
174 unsigned char twwt_mclk = 0; /* Write-to-write turnaround */
176 /* Active powerdown exit timing (tXARD and tXARDS). */
177 unsigned char act_pd_exit_mclk;
178 /* Precharge powerdown exit timing (tXP). */
179 unsigned char pre_pd_exit_mclk;
180 /* Precharge powerdown exit timing (tAXPD). */
181 unsigned char taxpd_mclk;
182 /* Mode register set cycle time (tMRD). */
183 unsigned char tmrd_mclk;
185 #if defined(CONFIG_FSL_DDR3)
187 * (tXARD and tXARDS). Empirical?
188 * The DDR3 spec has not tXARD,
189 * we use the tXP instead of it.
190 * tXP=max(3nCK, 7.5ns) for DDR3.
192 * spec has not the tAXPD, we use
193 * tAXPD=8, need design to confirm.
195 act_pd_exit_mclk = 6;
196 pre_pd_exit_mclk = 6;
199 #else /* CONFIG_FSL_DDR2 */
201 * (tXARD and tXARDS). Empirical?
206 act_pd_exit_mclk = 2;
207 pre_pd_exit_mclk = 2;
212 ddr->timing_cfg_0 = (0
213 | ((trwt_mclk & 0x3) << 30) /* RWT */
214 | ((twrt_mclk & 0x3) << 28) /* WRT */
215 | ((trrt_mclk & 0x3) << 26) /* RRT */
216 | ((twwt_mclk & 0x3) << 24) /* WWT */
217 | ((act_pd_exit_mclk & 0x7) << 20) /* ACT_PD_EXIT */
218 | ((pre_pd_exit_mclk & 0xF) << 16) /* PRE_PD_EXIT */
219 | ((taxpd_mclk & 0xf) << 8) /* ODT_PD_EXIT */
220 | ((tmrd_mclk & 0xf) << 0) /* MRS_CYC */
222 debug("FSLDDR: timing_cfg_0 = 0x%08x\n", ddr->timing_cfg_0);
224 #endif /* defined(CONFIG_FSL_DDR2) */
226 /* DDR SDRAM Timing Configuration 3 (TIMING_CFG_3) */
227 static void set_timing_cfg_3(fsl_ddr_cfg_regs_t *ddr,
228 const common_timing_params_t *common_dimm,
229 unsigned int cas_latency)
231 /* Extended Activate to precharge interval (tRAS) */
232 unsigned int ext_acttopre = 0;
233 unsigned int ext_refrec; /* Extended refresh recovery time (tRFC) */
234 unsigned int ext_caslat = 0; /* Extended MCAS latency from READ cmd */
235 unsigned int cntl_adj = 0; /* Control Adjust */
237 /* If the tRAS > 19 MCLK, we use the ext mode */
238 if (picos_to_mclk(common_dimm->tRAS_ps) > 0x13)
241 ext_refrec = (picos_to_mclk(common_dimm->tRFC_ps) - 8) >> 4;
243 /* If the CAS latency more than 8, use the ext mode */
247 ddr->timing_cfg_3 = (0
248 | ((ext_acttopre & 0x1) << 24)
249 | ((ext_refrec & 0xF) << 16)
250 | ((ext_caslat & 0x1) << 12)
251 | ((cntl_adj & 0x7) << 0)
253 debug("FSLDDR: timing_cfg_3 = 0x%08x\n", ddr->timing_cfg_3);
256 /* DDR SDRAM Timing Configuration 1 (TIMING_CFG_1) */
257 static void set_timing_cfg_1(fsl_ddr_cfg_regs_t *ddr,
258 const memctl_options_t *popts,
259 const common_timing_params_t *common_dimm,
260 unsigned int cas_latency)
262 /* Precharge-to-activate interval (tRP) */
263 unsigned char pretoact_mclk;
264 /* Activate to precharge interval (tRAS) */
265 unsigned char acttopre_mclk;
266 /* Activate to read/write interval (tRCD) */
267 unsigned char acttorw_mclk;
269 unsigned char caslat_ctrl;
270 /* Refresh recovery time (tRFC) ; trfc_low */
271 unsigned char refrec_ctrl;
272 /* Last data to precharge minimum interval (tWR) */
273 unsigned char wrrec_mclk;
274 /* Activate-to-activate interval (tRRD) */
275 unsigned char acttoact_mclk;
276 /* Last write data pair to read command issue interval (tWTR) */
277 unsigned char wrtord_mclk;
279 pretoact_mclk = picos_to_mclk(common_dimm->tRP_ps);
280 acttopre_mclk = picos_to_mclk(common_dimm->tRAS_ps);
281 acttorw_mclk = picos_to_mclk(common_dimm->tRCD_ps);
284 * Translate CAS Latency to a DDR controller field value:
286 * CAS Lat DDR I DDR II Ctrl
287 * Clocks SPD Bit SPD Bit Value
288 * ------- ------- ------- -----
299 #if defined(CONFIG_FSL_DDR1)
300 caslat_ctrl = (cas_latency + 1) & 0x07;
301 #elif defined(CONFIG_FSL_DDR2)
302 caslat_ctrl = 2 * cas_latency - 1;
305 * if the CAS latency more than 8 cycle,
306 * we need set extend bit for it at
307 * TIMING_CFG_3[EXT_CASLAT]
311 caslat_ctrl = 2 * cas_latency - 1;
314 refrec_ctrl = picos_to_mclk(common_dimm->tRFC_ps) - 8;
315 wrrec_mclk = picos_to_mclk(common_dimm->tWR_ps);
316 if (popts->OTF_burst_chop_en)
319 acttoact_mclk = picos_to_mclk(common_dimm->tRRD_ps);
321 * JEDEC has min requirement for tRRD
323 #if defined(CONFIG_FSL_DDR3)
324 if (acttoact_mclk < 4)
327 wrtord_mclk = picos_to_mclk(common_dimm->tWTR_ps);
329 * JEDEC has some min requirements for tWTR
331 #if defined(CONFIG_FSL_DDR2)
334 #elif defined(CONFIG_FSL_DDR3)
338 if (popts->OTF_burst_chop_en)
341 ddr->timing_cfg_1 = (0
342 | ((pretoact_mclk & 0x0F) << 28)
343 | ((acttopre_mclk & 0x0F) << 24)
344 | ((acttorw_mclk & 0xF) << 20)
345 | ((caslat_ctrl & 0xF) << 16)
346 | ((refrec_ctrl & 0xF) << 12)
347 | ((wrrec_mclk & 0x0F) << 8)
348 | ((acttoact_mclk & 0x07) << 4)
349 | ((wrtord_mclk & 0x07) << 0)
351 debug("FSLDDR: timing_cfg_1 = 0x%08x\n", ddr->timing_cfg_1);
354 /* DDR SDRAM Timing Configuration 2 (TIMING_CFG_2) */
355 static void set_timing_cfg_2(fsl_ddr_cfg_regs_t *ddr,
356 const memctl_options_t *popts,
357 const common_timing_params_t *common_dimm,
358 unsigned int cas_latency,
359 unsigned int additive_latency)
361 /* Additive latency */
362 unsigned char add_lat_mclk;
363 /* CAS-to-preamble override */
366 unsigned char wr_lat;
367 /* Read to precharge (tRTP) */
368 unsigned char rd_to_pre;
369 /* Write command to write data strobe timing adjustment */
370 unsigned char wr_data_delay;
371 /* Minimum CKE pulse width (tCKE) */
372 unsigned char cke_pls;
373 /* Window for four activates (tFAW) */
374 unsigned short four_act;
376 /* FIXME add check that this must be less than acttorw_mclk */
377 add_lat_mclk = additive_latency;
378 cpo = popts->cpo_override;
380 #if defined(CONFIG_FSL_DDR1)
382 * This is a lie. It should really be 1, but if it is
383 * set to 1, bits overlap into the old controller's
384 * otherwise unused ACSM field. If we leave it 0, then
385 * the HW will magically treat it as 1 for DDR 1. Oh Yea.
388 #elif defined(CONFIG_FSL_DDR2)
389 wr_lat = cas_latency - 1;
391 wr_lat = compute_cas_write_latency();
394 rd_to_pre = picos_to_mclk(common_dimm->tRTP_ps);
396 * JEDEC has some min requirements for tRTP
398 #if defined(CONFIG_FSL_DDR2)
401 #elif defined(CONFIG_FSL_DDR3)
405 if (additive_latency)
406 rd_to_pre += additive_latency;
407 if (popts->OTF_burst_chop_en)
408 rd_to_pre += 2; /* according to UM */
410 wr_data_delay = popts->write_data_delay;
411 cke_pls = picos_to_mclk(popts->tCKE_clock_pulse_width_ps);
412 four_act = picos_to_mclk(popts->tFAW_window_four_activates_ps);
414 ddr->timing_cfg_2 = (0
415 | ((add_lat_mclk & 0xf) << 28)
416 | ((cpo & 0x1f) << 23)
417 | ((wr_lat & 0xf) << 19)
418 | ((rd_to_pre & RD_TO_PRE_MASK) << RD_TO_PRE_SHIFT)
419 | ((wr_data_delay & WR_DATA_DELAY_MASK) << WR_DATA_DELAY_SHIFT)
420 | ((cke_pls & 0x7) << 6)
421 | ((four_act & 0x3f) << 0)
423 debug("FSLDDR: timing_cfg_2 = 0x%08x\n", ddr->timing_cfg_2);
426 /* DDR SDRAM control configuration (DDR_SDRAM_CFG) */
427 static void set_ddr_sdram_cfg(fsl_ddr_cfg_regs_t *ddr,
428 const memctl_options_t *popts,
429 const common_timing_params_t *common_dimm)
431 unsigned int mem_en; /* DDR SDRAM interface logic enable */
432 unsigned int sren; /* Self refresh enable (during sleep) */
433 unsigned int ecc_en; /* ECC enable. */
434 unsigned int rd_en; /* Registered DIMM enable */
435 unsigned int sdram_type; /* Type of SDRAM */
436 unsigned int dyn_pwr; /* Dynamic power management mode */
437 unsigned int dbw; /* DRAM dta bus width */
438 unsigned int eight_be = 0; /* 8-beat burst enable, DDR2 is zero */
439 unsigned int ncap = 0; /* Non-concurrent auto-precharge */
440 unsigned int threeT_en; /* Enable 3T timing */
441 unsigned int twoT_en; /* Enable 2T timing */
442 unsigned int ba_intlv_ctl; /* Bank (CS) interleaving control */
443 unsigned int x32_en = 0; /* x32 enable */
444 unsigned int pchb8 = 0; /* precharge bit 8 enable */
445 unsigned int hse; /* Global half strength override */
446 unsigned int mem_halt = 0; /* memory controller halt */
447 unsigned int bi = 0; /* Bypass initialization */
450 sren = popts->self_refresh_in_sleep;
451 if (common_dimm->all_DIMMs_ECC_capable) {
452 /* Allow setting of ECC only if all DIMMs are ECC. */
453 ecc_en = popts->ECC_mode;
458 rd_en = (common_dimm->all_DIMMs_registered
459 && !common_dimm->all_DIMMs_unbuffered);
461 sdram_type = CONFIG_FSL_SDRAM_TYPE;
463 dyn_pwr = popts->dynamic_power;
464 dbw = popts->data_bus_width;
465 /* 8-beat burst enable DDR-III case
466 * we must clear it when use the on-the-fly mode,
467 * must set it when use the 32-bits bus mode.
469 if (sdram_type == SDRAM_TYPE_DDR3) {
470 if (popts->burst_length == DDR_BL8)
472 if (popts->burst_length == DDR_OTF)
478 threeT_en = popts->threeT_en;
479 twoT_en = popts->twoT_en;
480 ba_intlv_ctl = popts->ba_intlv_ctl;
481 hse = popts->half_strength_driver_enable;
483 ddr->ddr_sdram_cfg = (0
484 | ((mem_en & 0x1) << 31)
485 | ((sren & 0x1) << 30)
486 | ((ecc_en & 0x1) << 29)
487 | ((rd_en & 0x1) << 28)
488 | ((sdram_type & 0x7) << 24)
489 | ((dyn_pwr & 0x1) << 21)
490 | ((dbw & 0x3) << 19)
491 | ((eight_be & 0x1) << 18)
492 | ((ncap & 0x1) << 17)
493 | ((threeT_en & 0x1) << 16)
494 | ((twoT_en & 0x1) << 15)
495 | ((ba_intlv_ctl & 0x7F) << 8)
496 | ((x32_en & 0x1) << 5)
497 | ((pchb8 & 0x1) << 4)
499 | ((mem_halt & 0x1) << 1)
502 debug("FSLDDR: ddr_sdram_cfg = 0x%08x\n", ddr->ddr_sdram_cfg);
505 /* DDR SDRAM control configuration 2 (DDR_SDRAM_CFG_2) */
506 static void set_ddr_sdram_cfg_2(fsl_ddr_cfg_regs_t *ddr,
507 const memctl_options_t *popts)
509 unsigned int frc_sr = 0; /* Force self refresh */
510 unsigned int sr_ie = 0; /* Self-refresh interrupt enable */
511 unsigned int dll_rst_dis; /* DLL reset disable */
512 unsigned int dqs_cfg; /* DQS configuration */
513 unsigned int odt_cfg; /* ODT configuration */
514 unsigned int num_pr; /* Number of posted refreshes */
515 unsigned int obc_cfg; /* On-The-Fly Burst Chop Cfg */
516 unsigned int ap_en; /* Address Parity Enable */
517 unsigned int d_init; /* DRAM data initialization */
518 unsigned int rcw_en = 0; /* Register Control Word Enable */
519 unsigned int md_en = 0; /* Mirrored DIMM Enable */
521 dll_rst_dis = 1; /* Make this configurable */
522 dqs_cfg = popts->DQS_config;
523 if (popts->cs_local_opts[0].odt_rd_cfg
524 || popts->cs_local_opts[0].odt_wr_cfg) {
531 num_pr = 1; /* Make this configurable */
535 * {TIMING_CFG_1[PRETOACT]
536 * + [DDR_SDRAM_CFG_2[NUM_PR]
537 * * ({EXT_REFREC || REFREC} + 8 + 2)]}
538 * << DDR_SDRAM_INTERVAL[REFINT]
540 #if defined(CONFIG_FSL_DDR3)
541 obc_cfg = popts->OTF_burst_chop_en;
546 ap_en = 0; /* Make this configurable? */
548 #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
549 /* Use the DDR controller to auto initialize memory. */
551 ddr->ddr_data_init = CONFIG_MEM_INIT_VALUE;
552 debug("DDR: ddr_data_init = 0x%08x\n", ddr->ddr_data_init);
554 /* Memory will be initialized via DMA, or not at all. */
558 #if defined(CONFIG_FSL_DDR3)
559 md_en = popts->mirrored_dimm;
561 ddr->ddr_sdram_cfg_2 = (0
562 | ((frc_sr & 0x1) << 31)
563 | ((sr_ie & 0x1) << 30)
564 | ((dll_rst_dis & 0x1) << 29)
565 | ((dqs_cfg & 0x3) << 26)
566 | ((odt_cfg & 0x3) << 21)
567 | ((num_pr & 0xf) << 12)
568 | ((obc_cfg & 0x1) << 6)
569 | ((ap_en & 0x1) << 5)
570 | ((d_init & 0x1) << 4)
571 | ((rcw_en & 0x1) << 2)
572 | ((md_en & 0x1) << 0)
574 debug("FSLDDR: ddr_sdram_cfg_2 = 0x%08x\n", ddr->ddr_sdram_cfg_2);
577 /* DDR SDRAM Mode configuration 2 (DDR_SDRAM_MODE_2) */
578 static void set_ddr_sdram_mode_2(fsl_ddr_cfg_regs_t *ddr)
580 unsigned short esdmode2 = 0; /* Extended SDRAM mode 2 */
581 unsigned short esdmode3 = 0; /* Extended SDRAM mode 3 */
583 #if defined(CONFIG_FSL_DDR3)
584 unsigned int rtt_wr = 2; /* 120 ohm Rtt_WR */
585 unsigned int srt = 0; /* self-refresh temerature, normal range */
586 unsigned int asr = 0; /* auto self-refresh disable */
587 unsigned int cwl = compute_cas_write_latency() - 5;
588 unsigned int pasr = 0; /* partial array self refresh disable */
591 | ((rtt_wr & 0x3) << 9)
595 | ((pasr & 0x7) << 0));
597 ddr->ddr_sdram_mode_2 = (0
598 | ((esdmode2 & 0xFFFF) << 16)
599 | ((esdmode3 & 0xFFFF) << 0)
601 debug("FSLDDR: ddr_sdram_mode_2 = 0x%08x\n", ddr->ddr_sdram_mode_2);
604 /* DDR SDRAM Interval Configuration (DDR_SDRAM_INTERVAL) */
605 static void set_ddr_sdram_interval(fsl_ddr_cfg_regs_t *ddr,
606 const memctl_options_t *popts,
607 const common_timing_params_t *common_dimm)
609 unsigned int refint; /* Refresh interval */
610 unsigned int bstopre; /* Precharge interval */
612 refint = picos_to_mclk(common_dimm->refresh_rate_ps);
614 bstopre = popts->bstopre;
616 /* refint field used 0x3FFF in earlier controllers */
617 ddr->ddr_sdram_interval = (0
618 | ((refint & 0xFFFF) << 16)
619 | ((bstopre & 0x3FFF) << 0)
621 debug("FSLDDR: ddr_sdram_interval = 0x%08x\n", ddr->ddr_sdram_interval);
624 #if defined(CONFIG_FSL_DDR3)
625 /* DDR SDRAM Mode configuration set (DDR_SDRAM_MODE) */
626 static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr,
627 const memctl_options_t *popts,
628 const common_timing_params_t *common_dimm,
629 unsigned int cas_latency,
630 unsigned int additive_latency)
632 unsigned short esdmode; /* Extended SDRAM mode */
633 unsigned short sdmode; /* SDRAM mode */
635 /* Mode Register - MR1 */
636 unsigned int qoff = 0; /* Output buffer enable 0=yes, 1=no */
637 unsigned int tdqs_en = 0; /* TDQS Enable: 0=no, 1=yes */
639 unsigned int wrlvl_en = 0; /* Write level enable: 0=no, 1=yes */
640 unsigned int al = 0; /* Posted CAS# additive latency (AL) */
641 unsigned int dic = 1; /* Output driver impedance, 34ohm */
642 unsigned int dll_en = 0; /* DLL Enable 0=Enable (Normal),
643 1=Disable (Test/Debug) */
645 /* Mode Register - MR0 */
646 unsigned int dll_on; /* DLL control for precharge PD, 0=off, 1=on */
647 unsigned int wr; /* Write Recovery */
648 unsigned int dll_rst; /* DLL Reset */
649 unsigned int mode; /* Normal=0 or Test=1 */
650 unsigned int caslat = 4;/* CAS# latency, default set as 6 cycles */
651 /* BT: Burst Type (0=Nibble Sequential, 1=Interleaved) */
653 unsigned int bl; /* BL: Burst Length */
655 unsigned int wr_mclk;
657 const unsigned int mclk_ps = get_memory_clk_period_ps();
659 rtt = fsl_ddr_get_rtt();
660 if (popts->rtt_override)
661 rtt = popts->rtt_override_value;
663 if (additive_latency == (cas_latency - 1))
665 if (additive_latency == (cas_latency - 2))
669 * The esdmode value will also be used for writing
670 * MR1 during write leveling for DDR3, although the
671 * bits specifically related to the write leveling
672 * scheme will be handled automatically by the DDR
673 * controller. so we set the wrlvl_en = 0 here.
676 | ((qoff & 0x1) << 12)
677 | ((tdqs_en & 0x1) << 11)
678 | ((rtt & 0x4) << 9) /* rtt field is split */
679 | ((wrlvl_en & 0x1) << 7)
680 | ((rtt & 0x2) << 6) /* rtt field is split */
681 | ((dic & 0x2) << 5) /* DIC field is split */
683 | ((rtt & 0x1) << 2) /* rtt field is split */
684 | ((dic & 0x1) << 1) /* DIC field is split */
685 | ((dll_en & 0x1) << 0)
689 * DLL control for precharge PD
690 * 0=slow exit DLL off (tXPDLL)
691 * 1=fast exit DLL on (tXP)
694 wr_mclk = (common_dimm->tWR_ps + mclk_ps - 1) / mclk_ps;
697 else if (wr_mclk >= 9)
701 dll_rst = 0; /* dll no reset */
702 mode = 0; /* normal mode */
704 /* look up table to get the cas latency bits */
705 if (cas_latency >= 5 && cas_latency <= 11) {
706 unsigned char cas_latency_table[7] = {
715 caslat = cas_latency_table[cas_latency - 5];
717 bt = 0; /* Nibble sequential */
719 switch (popts->burst_length) {
730 printf("Error: invalid burst length of %u specified. "
731 " Defaulting to on-the-fly BC4 or BL8 beats.\n",
732 popts->burst_length);
738 | ((dll_on & 0x1) << 12)
740 | ((dll_rst & 0x1) << 8)
741 | ((mode & 0x1) << 7)
742 | (((caslat >> 1) & 0x7) << 4)
747 ddr->ddr_sdram_mode = (0
748 | ((esdmode & 0xFFFF) << 16)
749 | ((sdmode & 0xFFFF) << 0)
752 debug("FSLDDR: ddr_sdram_mode = 0x%08x\n", ddr->ddr_sdram_mode);
755 #else /* !CONFIG_FSL_DDR3 */
757 /* DDR SDRAM Mode configuration set (DDR_SDRAM_MODE) */
758 static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr,
759 const memctl_options_t *popts,
760 const common_timing_params_t *common_dimm,
761 unsigned int cas_latency,
762 unsigned int additive_latency)
764 unsigned short esdmode; /* Extended SDRAM mode */
765 unsigned short sdmode; /* SDRAM mode */
768 * FIXME: This ought to be pre-calculated in a
769 * technology-specific routine,
770 * e.g. compute_DDR2_mode_register(), and then the
771 * sdmode and esdmode passed in as part of common_dimm.
774 /* Extended Mode Register */
775 unsigned int mrs = 0; /* Mode Register Set */
776 unsigned int outputs = 0; /* 0=Enabled, 1=Disabled */
777 unsigned int rdqs_en = 0; /* RDQS Enable: 0=no, 1=yes */
778 unsigned int dqs_en = 0; /* DQS# Enable: 0=enable, 1=disable */
779 unsigned int ocd = 0; /* 0x0=OCD not supported,
780 0x7=OCD default state */
782 unsigned int al; /* Posted CAS# additive latency (AL) */
783 unsigned int ods = 0; /* Output Drive Strength:
784 0 = Full strength (18ohm)
785 1 = Reduced strength (4ohm) */
786 unsigned int dll_en = 0; /* DLL Enable 0=Enable (Normal),
787 1=Disable (Test/Debug) */
789 /* Mode Register (MR) */
790 unsigned int mr; /* Mode Register Definition */
791 unsigned int pd; /* Power-Down Mode */
792 unsigned int wr; /* Write Recovery */
793 unsigned int dll_res; /* DLL Reset */
794 unsigned int mode; /* Normal=0 or Test=1 */
795 unsigned int caslat = 0;/* CAS# latency */
796 /* BT: Burst Type (0=Sequential, 1=Interleaved) */
798 unsigned int bl; /* BL: Burst Length */
800 #if defined(CONFIG_FSL_DDR2)
801 const unsigned int mclk_ps = get_memory_clk_period_ps();
804 rtt = fsl_ddr_get_rtt();
806 al = additive_latency;
809 | ((mrs & 0x3) << 14)
810 | ((outputs & 0x1) << 12)
811 | ((rdqs_en & 0x1) << 11)
812 | ((dqs_en & 0x1) << 10)
814 | ((rtt & 0x2) << 5) /* rtt field is split */
816 | ((rtt & 0x1) << 2) /* rtt field is split */
818 | ((dll_en & 0x1) << 0)
821 mr = 0; /* FIXME: CHECKME */
824 * 0 = Fast Exit (Normal)
825 * 1 = Slow Exit (Low Power)
829 #if defined(CONFIG_FSL_DDR1)
830 wr = 0; /* Historical */
831 #elif defined(CONFIG_FSL_DDR2)
832 wr = (common_dimm->tWR_ps + mclk_ps - 1) / mclk_ps - 1;
837 #if defined(CONFIG_FSL_DDR1)
838 if (1 <= cas_latency && cas_latency <= 4) {
839 unsigned char mode_caslat_table[4] = {
840 0x5, /* 1.5 clocks */
841 0x2, /* 2.0 clocks */
842 0x6, /* 2.5 clocks */
845 caslat = mode_caslat_table[cas_latency - 1];
847 printf("Warning: unknown cas_latency %d\n", cas_latency);
849 #elif defined(CONFIG_FSL_DDR2)
850 caslat = cas_latency;
854 switch (popts->burst_length) {
862 printf("Error: invalid burst length of %u specified. "
863 " Defaulting to 4 beats.\n",
864 popts->burst_length);
873 | ((dll_res & 0x1) << 8)
874 | ((mode & 0x1) << 7)
875 | ((caslat & 0x7) << 4)
880 ddr->ddr_sdram_mode = (0
881 | ((esdmode & 0xFFFF) << 16)
882 | ((sdmode & 0xFFFF) << 0)
884 debug("FSLDDR: ddr_sdram_mode = 0x%08x\n", ddr->ddr_sdram_mode);
888 /* DDR SDRAM Data Initialization (DDR_DATA_INIT) */
889 static void set_ddr_data_init(fsl_ddr_cfg_regs_t *ddr)
891 unsigned int init_value; /* Initialization value */
893 init_value = 0xDEADBEEF;
894 ddr->ddr_data_init = init_value;
898 * DDR SDRAM Clock Control (DDR_SDRAM_CLK_CNTL)
899 * The old controller on the 8540/60 doesn't have this register.
900 * Hope it's OK to set it (to 0) anyway.
902 static void set_ddr_sdram_clk_cntl(fsl_ddr_cfg_regs_t *ddr,
903 const memctl_options_t *popts)
905 unsigned int clk_adjust; /* Clock adjust */
907 clk_adjust = popts->clk_adjust;
908 ddr->ddr_sdram_clk_cntl = (clk_adjust & 0xF) << 23;
911 /* DDR Initialization Address (DDR_INIT_ADDR) */
912 static void set_ddr_init_addr(fsl_ddr_cfg_regs_t *ddr)
914 unsigned int init_addr = 0; /* Initialization address */
916 ddr->ddr_init_addr = init_addr;
919 /* DDR Initialization Address (DDR_INIT_EXT_ADDR) */
920 static void set_ddr_init_ext_addr(fsl_ddr_cfg_regs_t *ddr)
922 unsigned int uia = 0; /* Use initialization address */
923 unsigned int init_ext_addr = 0; /* Initialization address */
925 ddr->ddr_init_ext_addr = (0
926 | ((uia & 0x1) << 31)
927 | (init_ext_addr & 0xF)
931 /* DDR SDRAM Timing Configuration 4 (TIMING_CFG_4) */
932 static void set_timing_cfg_4(fsl_ddr_cfg_regs_t *ddr)
934 unsigned int rwt = 0; /* Read-to-write turnaround for same CS */
935 unsigned int wrt = 0; /* Write-to-read turnaround for same CS */
936 unsigned int rrt = 0; /* Read-to-read turnaround for same CS */
937 unsigned int wwt = 0; /* Write-to-write turnaround for same CS */
938 unsigned int dll_lock = 0; /* DDR SDRAM DLL Lock Time */
940 #if defined(CONFIG_FSL_DDR3)
941 /* We need set BL/2 + 4 for BC4 or OTF */
942 rrt = 4; /* BL/2 + 4 clocks */
943 wwt = 4; /* BL/2 + 4 clocks */
944 dll_lock = 1; /* tDLLK = 512 clocks from spec */
946 ddr->timing_cfg_4 = (0
947 | ((rwt & 0xf) << 28)
948 | ((wrt & 0xf) << 24)
949 | ((rrt & 0xf) << 20)
950 | ((wwt & 0xf) << 16)
953 debug("FSLDDR: timing_cfg_4 = 0x%08x\n", ddr->timing_cfg_4);
956 /* DDR SDRAM Timing Configuration 5 (TIMING_CFG_5) */
957 static void set_timing_cfg_5(fsl_ddr_cfg_regs_t *ddr)
959 unsigned int rodt_on = 0; /* Read to ODT on */
960 unsigned int rodt_off = 0; /* Read to ODT off */
961 unsigned int wodt_on = 0; /* Write to ODT on */
962 unsigned int wodt_off = 0; /* Write to ODT off */
964 #if defined(CONFIG_FSL_DDR3)
965 rodt_on = 3; /* 2 clocks */
966 rodt_off = 4; /* 4 clocks */
967 wodt_on = 2; /* 1 clocks */
968 wodt_off = 4; /* 4 clocks */
971 ddr->timing_cfg_5 = (0
972 | ((rodt_on & 0x1f) << 24)
973 | ((rodt_off & 0x7) << 20)
974 | ((wodt_on & 0x1f) << 12)
975 | ((wodt_off & 0x7) << 8)
977 debug("FSLDDR: timing_cfg_5 = 0x%08x\n", ddr->timing_cfg_5);
980 /* DDR ZQ Calibration Control (DDR_ZQ_CNTL) */
981 static void set_ddr_zq_cntl(fsl_ddr_cfg_regs_t *ddr, unsigned int zq_en)
983 unsigned int zqinit = 0;/* POR ZQ Calibration Time (tZQinit) */
984 /* Normal Operation Full Calibration Time (tZQoper) */
985 unsigned int zqoper = 0;
986 /* Normal Operation Short Calibration Time (tZQCS) */
987 unsigned int zqcs = 0;
990 zqinit = 9; /* 512 clocks */
991 zqoper = 8; /* 256 clocks */
992 zqcs = 6; /* 64 clocks */
995 ddr->ddr_zq_cntl = (0
996 | ((zq_en & 0x1) << 31)
997 | ((zqinit & 0xF) << 24)
998 | ((zqoper & 0xF) << 16)
999 | ((zqcs & 0xF) << 8)
1003 /* DDR Write Leveling Control (DDR_WRLVL_CNTL) */
1004 static void set_ddr_wrlvl_cntl(fsl_ddr_cfg_regs_t *ddr,
1005 unsigned int wrlvl_en)
1008 * First DQS pulse rising edge after margining mode
1009 * is programmed (tWL_MRD)
1011 unsigned int wrlvl_mrd = 0;
1012 /* ODT delay after margining mode is programmed (tWL_ODTEN) */
1013 unsigned int wrlvl_odten = 0;
1014 /* DQS/DQS_ delay after margining mode is programmed (tWL_DQSEN) */
1015 unsigned int wrlvl_dqsen = 0;
1016 /* WRLVL_SMPL: Write leveling sample time */
1017 unsigned int wrlvl_smpl = 0;
1018 /* WRLVL_WLR: Write leveling repeition time */
1019 unsigned int wrlvl_wlr = 0;
1020 /* WRLVL_START: Write leveling start time */
1021 unsigned int wrlvl_start = 0;
1023 /* suggest enable write leveling for DDR3 due to fly-by topology */
1025 /* tWL_MRD min = 40 nCK, we set it 64 */
1029 /* tWL_DQSEN min = 25 nCK, we set it 32 */
1032 * Write leveling sample time at least need 14 clocks
1033 * due to tWLO = 9, we set it 15 clocks
1037 * Write leveling repetition time
1038 * at least tWLO + 6 clocks clocks
1043 * Write leveling start time
1044 * The value use for the DQS_ADJUST for the first sample
1045 * when write leveling is enabled.
1046 * we set it 1 clock delay
1051 ddr->ddr_wrlvl_cntl = (0
1052 | ((wrlvl_en & 0x1) << 31)
1053 | ((wrlvl_mrd & 0x7) << 24)
1054 | ((wrlvl_odten & 0x7) << 20)
1055 | ((wrlvl_dqsen & 0x7) << 16)
1056 | ((wrlvl_smpl & 0xf) << 12)
1057 | ((wrlvl_wlr & 0x7) << 8)
1058 | ((wrlvl_start & 0x1F) << 0)
1062 /* DDR Self Refresh Counter (DDR_SR_CNTR) */
1063 static void set_ddr_sr_cntr(fsl_ddr_cfg_regs_t *ddr, unsigned int sr_it)
1065 /* Self Refresh Idle Threshold */
1066 ddr->ddr_sr_cntr = (sr_it & 0xF) << 16;
1069 /* DDR Pre-Drive Conditioning Control (DDR_PD_CNTL) */
1070 static void set_ddr_pd_cntl(fsl_ddr_cfg_regs_t *ddr)
1072 /* Termination value during pre-drive conditioning */
1073 unsigned int tvpd = 0;
1074 unsigned int pd_en = 0; /* Pre-Drive Conditioning Enable */
1075 unsigned int pdar = 0; /* Pre-Drive After Read */
1076 unsigned int pdaw = 0; /* Pre-Drive After Write */
1077 unsigned int pd_on = 0; /* Pre-Drive Conditioning On */
1078 unsigned int pd_off = 0; /* Pre-Drive Conditioning Off */
1080 ddr->ddr_pd_cntl = (0
1081 | ((pd_en & 0x1) << 31)
1082 | ((tvpd & 0x7) << 28)
1083 | ((pdar & 0x7F) << 20)
1084 | ((pdaw & 0x7F) << 12)
1085 | ((pd_on & 0x1F) << 6)
1086 | ((pd_off & 0x1F) << 0)
1091 /* DDR SDRAM Register Control Word 1 (DDR_SDRAM_RCW_1) */
1092 static void set_ddr_sdram_rcw_1(fsl_ddr_cfg_regs_t *ddr)
1094 unsigned int rcw0 = 0; /* RCW0: Register Control Word 0 */
1095 unsigned int rcw1 = 0; /* RCW1: Register Control Word 1 */
1096 unsigned int rcw2 = 0; /* RCW2: Register Control Word 2 */
1097 unsigned int rcw3 = 0; /* RCW3: Register Control Word 3 */
1098 unsigned int rcw4 = 0; /* RCW4: Register Control Word 4 */
1099 unsigned int rcw5 = 0; /* RCW5: Register Control Word 5 */
1100 unsigned int rcw6 = 0; /* RCW6: Register Control Word 6 */
1101 unsigned int rcw7 = 0; /* RCW7: Register Control Word 7 */
1103 ddr->ddr_sdram_rcw_1 = (0
1104 | ((rcw0 & 0xF) << 28)
1105 | ((rcw1 & 0xF) << 24)
1106 | ((rcw2 & 0xF) << 20)
1107 | ((rcw3 & 0xF) << 16)
1108 | ((rcw4 & 0xF) << 12)
1109 | ((rcw5 & 0xF) << 8)
1110 | ((rcw6 & 0xF) << 4)
1111 | ((rcw7 & 0xF) << 0)
1115 /* DDR SDRAM Register Control Word 2 (DDR_SDRAM_RCW_2) */
1116 static void set_ddr_sdram_rcw_2(fsl_ddr_cfg_regs_t *ddr)
1118 unsigned int rcw8 = 0; /* RCW0: Register Control Word 8 */
1119 unsigned int rcw9 = 0; /* RCW1: Register Control Word 9 */
1120 unsigned int rcw10 = 0; /* RCW2: Register Control Word 10 */
1121 unsigned int rcw11 = 0; /* RCW3: Register Control Word 11 */
1122 unsigned int rcw12 = 0; /* RCW4: Register Control Word 12 */
1123 unsigned int rcw13 = 0; /* RCW5: Register Control Word 13 */
1124 unsigned int rcw14 = 0; /* RCW6: Register Control Word 14 */
1125 unsigned int rcw15 = 0; /* RCW7: Register Control Word 15 */
1127 ddr->ddr_sdram_rcw_2 = (0
1128 | ((rcw8 & 0xF) << 28)
1129 | ((rcw9 & 0xF) << 24)
1130 | ((rcw10 & 0xF) << 20)
1131 | ((rcw11 & 0xF) << 16)
1132 | ((rcw12 & 0xF) << 12)
1133 | ((rcw13 & 0xF) << 8)
1134 | ((rcw14 & 0xF) << 4)
1135 | ((rcw15 & 0xF) << 0)
1140 check_fsl_memctl_config_regs(const fsl_ddr_cfg_regs_t *ddr)
1142 unsigned int res = 0;
1145 * Check that DDR_SDRAM_CFG[RD_EN] and DDR_SDRAM_CFG[2T_EN] are
1146 * not set at the same time.
1148 if (ddr->ddr_sdram_cfg & 0x10000000
1149 && ddr->ddr_sdram_cfg & 0x00008000) {
1150 printf("Error: DDR_SDRAM_CFG[RD_EN] and DDR_SDRAM_CFG[2T_EN] "
1151 " should not be set at the same time.\n");
1159 compute_fsl_memctl_config_regs(const memctl_options_t *popts,
1160 fsl_ddr_cfg_regs_t *ddr,
1161 const common_timing_params_t *common_dimm,
1162 const dimm_params_t *dimm_params,
1163 unsigned int dbw_cap_adj)
1166 unsigned int cas_latency;
1167 unsigned int additive_latency;
1170 unsigned int wrlvl_en;
1172 memset(ddr, 0, sizeof(fsl_ddr_cfg_regs_t));
1174 if (common_dimm == NULL) {
1175 printf("Error: subset DIMM params struct null pointer\n");
1180 * Process overrides first.
1182 * FIXME: somehow add dereated caslat to this
1184 cas_latency = (popts->cas_latency_override)
1185 ? popts->cas_latency_override_value
1186 : common_dimm->lowest_common_SPD_caslat;
1188 additive_latency = (popts->additive_latency_override)
1189 ? popts->additive_latency_override_value
1190 : common_dimm->additive_latency;
1192 sr_it = (popts->auto_self_refresh_en)
1195 /* ZQ calibration */
1196 zq_en = (popts->zq_en) ? 1 : 0;
1197 /* write leveling */
1198 wrlvl_en = (popts->wrlvl_en) ? 1 : 0;
1200 /* Chip Select Memory Bounds (CSn_BNDS) */
1201 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
1202 unsigned long long ea = 0, sa = 0;
1204 if (popts->ba_intlv_ctl && (i > 0) &&
1205 ((popts->ba_intlv_ctl & 0x60) != FSL_DDR_CS2_CS3 )) {
1206 /* Don't set up boundaries for other CS
1207 * other than CS0, if bank interleaving
1208 * is enabled and not CS2+CS3 interleaved.
1213 if (dimm_params[i/2].n_ranks == 0) {
1214 debug("Skipping setup of CS%u "
1215 "because n_ranks on DIMM %u is 0\n", i, i/2);
1218 if (popts->memctl_interleaving && popts->ba_intlv_ctl) {
1220 * This works superbank 2CS
1221 * There are 2 memory controllers configured
1222 * identically, memory is interleaved between them,
1223 * and each controller uses rank interleaving within
1224 * itself. Therefore the starting and ending address
1225 * on each controller is twice the amount present on
1228 unsigned long long rank_density
1229 = dimm_params[0].capacity;
1230 ea = (2 * (rank_density >> dbw_cap_adj)) - 1;
1232 else if (!popts->memctl_interleaving && popts->ba_intlv_ctl) {
1234 * If memory interleaving between controllers is NOT
1235 * enabled, the starting address for each memory
1236 * controller is distinct. However, because rank
1237 * interleaving is enabled, the starting and ending
1238 * addresses of the total memory on that memory
1239 * controller needs to be programmed into its
1240 * respective CS0_BNDS.
1242 unsigned long long rank_density
1243 = dimm_params[i/2].rank_density;
1244 switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) {
1245 case FSL_DDR_CS0_CS1_CS2_CS3:
1246 /* CS0+CS1+CS2+CS3 interleaving, only CS0_CNDS
1249 sa = common_dimm->base_address;
1250 ea = sa + (4 * (rank_density >> dbw_cap_adj))-1;
1252 case FSL_DDR_CS0_CS1_AND_CS2_CS3:
1253 /* CS0+CS1 and CS2+CS3 interleaving, CS0_CNDS
1254 * and CS2_CNDS need to be set.
1257 sa = dimm_params[i/2].base_address;
1258 ea = sa + (i * (rank_density >>
1262 case FSL_DDR_CS0_CS1:
1263 /* CS0+CS1 interleaving, CS0_CNDS needs
1266 sa = common_dimm->base_address;
1267 ea = sa + (2 * (rank_density >> dbw_cap_adj))-1;
1269 case FSL_DDR_CS2_CS3:
1270 /* CS2+CS3 interleaving*/
1272 sa = dimm_params[i/2].base_address;
1273 ea = sa + (2 * (rank_density >>
1277 default: /* No bank(chip-select) interleaving */
1281 else if (popts->memctl_interleaving && !popts->ba_intlv_ctl) {
1283 * Only the rank on CS0 of each memory controller may
1284 * be used if memory controller interleaving is used
1285 * without rank interleaving within each memory
1286 * controller. However, the ending address programmed
1287 * into each CS0 must be the sum of the amount of
1288 * memory in the two CS0 ranks.
1291 unsigned long long rank_density
1292 = dimm_params[0].rank_density;
1293 ea = (2 * (rank_density >> dbw_cap_adj)) - 1;
1297 else if (!popts->memctl_interleaving && !popts->ba_intlv_ctl) {
1299 * No rank interleaving and no memory controller
1302 unsigned long long rank_density
1303 = dimm_params[i/2].rank_density;
1304 sa = dimm_params[i/2].base_address;
1305 ea = sa + (rank_density >> dbw_cap_adj) - 1;
1307 if ((dimm_params[i/2].n_ranks == 1)) {
1308 /* Odd chip select, single-rank dimm */
1312 /* Odd chip select, dual-rank DIMM */
1313 sa += rank_density >> dbw_cap_adj;
1314 ea += rank_density >> dbw_cap_adj;
1322 ddr->cs[i].bnds = (0
1323 | ((sa & 0xFFF) << 16) /* starting address MSB */
1324 | ((ea & 0xFFF) << 0) /* ending address MSB */
1327 debug("FSLDDR: cs[%d]_bnds = 0x%08x\n", i, ddr->cs[i].bnds);
1328 set_csn_config(i, ddr, popts, dimm_params);
1329 set_csn_config_2(i, ddr);
1332 #if !defined(CONFIG_FSL_DDR1)
1333 set_timing_cfg_0(ddr);
1336 set_timing_cfg_3(ddr, common_dimm, cas_latency);
1337 set_timing_cfg_1(ddr, popts, common_dimm, cas_latency);
1338 set_timing_cfg_2(ddr, popts, common_dimm,
1339 cas_latency, additive_latency);
1341 set_ddr_sdram_cfg(ddr, popts, common_dimm);
1343 set_ddr_sdram_cfg_2(ddr, popts);
1344 set_ddr_sdram_mode(ddr, popts, common_dimm,
1345 cas_latency, additive_latency);
1346 set_ddr_sdram_mode_2(ddr);
1347 set_ddr_sdram_interval(ddr, popts, common_dimm);
1348 set_ddr_data_init(ddr);
1349 set_ddr_sdram_clk_cntl(ddr, popts);
1350 set_ddr_init_addr(ddr);
1351 set_ddr_init_ext_addr(ddr);
1352 set_timing_cfg_4(ddr);
1353 set_timing_cfg_5(ddr);
1355 set_ddr_zq_cntl(ddr, zq_en);
1356 set_ddr_wrlvl_cntl(ddr, wrlvl_en);
1358 set_ddr_pd_cntl(ddr);
1359 set_ddr_sr_cntr(ddr, sr_it);
1361 set_ddr_sdram_rcw_1(ddr);
1362 set_ddr_sdram_rcw_2(ddr);
1364 return check_fsl_memctl_config_regs(ddr);