2 * (C) Copyright 2000-2004
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <asm/processor.h>
28 #ifndef CONFIG_TQM866M
32 /* pitc values to time for 58/8192 seconds (about 70.8 milliseconds) */
33 #define SPEED_PIT_COUNTS 58
34 #define SPEED_PITC ((SPEED_PIT_COUNTS - 1) << PITC_SHIFT)
35 #define SPEED_PITC_INIT ((SPEED_PIT_COUNTS + 1) << PITC_SHIFT)
37 /* Access functions for the Machine State Register */
38 static __inline__ unsigned long get_msr(void)
42 asm volatile("mfmsr %0" : "=r" (msr) :);
46 static __inline__ void set_msr(unsigned long msr)
48 asm volatile("mtmsr %0" : : "r" (msr));
51 /* ------------------------------------------------------------------------- */
54 * Measure CPU clock speed (core clock GCLK1, GCLK2),
55 * also determine bus clock speed (checking bus divider factor)
57 * (Approx. GCLK frequency in Hz)
59 * Initializes timer 2 and PIT, but disables them before return.
60 * [Use timer 2, because MPC823 CPUs mask 0.x do not have timers 3 and 4]
62 * When measuring the CPU clock against the PIT, we count cpu clocks
63 * for 58/8192 seconds with a prescale divide by 177 for the cpu clock.
64 * These strange values for the timing interval and prescaling are used
65 * because the formula for the CPU clock is:
67 * CPU clock = count * (177 * (8192 / 58))
69 * = count * 24999.7241
71 * which is very close to
75 * Since the count gives the CPU clock divided by 25000, we can get
76 * the CPU clock rounded to the nearest 0.1 MHz by
78 * CPU clock = ((count + 2) / 4) * 100000;
80 * The rounding is important since the measurement is sometimes going
81 * to be high or low by 0.025 MHz, depending on exactly how the clocks
82 * and counters interact. By rounding we get the exact answer for any
83 * CPU clock that is an even multiple of 0.1 MHz.
86 unsigned long measure_gclk(void)
88 volatile immap_t *immr = (immap_t *) CFG_IMMR;
89 volatile cpmtimer8xx_t *timerp = &immr->im_cpmtimer;
93 #ifdef CONFIG_MPC866_et_al
94 /* dont use OSCM, only use EXTCLK/512 */
95 immr->im_clkrst.car_sccr |= SCCR_RTSEL | SCCR_RTDIV;
97 immr->im_clkrst.car_sccr &= ~(SCCR_RTSEL | SCCR_RTDIV);
100 /* Reset + Stop Timer 2, no cascading
102 timerp->cpmt_tgcr &= ~(TGCR_CAS2 | TGCR_RST2);
104 /* Keep stopped, halt in debug mode
106 timerp->cpmt_tgcr |= (TGCR_FRZ2 | TGCR_STP2);
109 * Output ref. interrupt disable, int. clock
110 * Prescale by 177. Note that prescaler divides by value + 1
111 * so we must subtract 1 here.
113 timerp->cpmt_tmr2 = ((177 - 1) << TMR_PS_SHIFT) | TMR_ICLK_IN_GEN;
115 timerp->cpmt_tcn2 = 0; /* reset state */
116 timerp->cpmt_tgcr |= TGCR_RST2; /* enable timer 2 */
121 * We want to time for SPEED_PITC_COUNTS counts (of 8192 Hz),
122 * so the count value would be SPEED_PITC_COUNTS - 1.
123 * But there would be an uncertainty in the start time of 1/4
124 * count since when we enable the PIT the count is not
125 * synchronized to the 32768 Hz oscillator. The trick here is
126 * to start the count higher and wait until the PIT count
127 * changes to the required value before starting timer 2.
129 * One count high should be enough, but occasionally the start
130 * is off by 1 or 2 counts of 32768 Hz. With the start value
131 * set two counts high it seems very reliable.
134 immr->im_sitk.sitk_pitck = KAPWR_KEY; /* PIT initialization */
135 immr->im_sit.sit_pitc = SPEED_PITC_INIT;
137 immr->im_sitk.sitk_piscrk = KAPWR_KEY;
138 immr->im_sit.sit_piscr = CFG_PISCR;
141 * Start measurement - disable interrupts, just in case
143 msr_val = get_msr ();
144 set_msr (msr_val & ~MSR_EE);
146 immr->im_sit.sit_piscr |= PISCR_PTE;
148 /* spin until get exact count when we want to start */
149 while (immr->im_sit.sit_pitr > SPEED_PITC);
151 timerp->cpmt_tgcr &= ~TGCR_STP2; /* Start Timer 2 */
152 while ((immr->im_sit.sit_piscr & PISCR_PS) == 0);
153 timerp->cpmt_tgcr |= TGCR_STP2; /* Stop Timer 2 */
155 /* re-enable external interrupts if they were on */
158 /* Disable timer and PIT
160 timer2_val = timerp->cpmt_tcn2; /* save before reset timer */
162 timerp->cpmt_tgcr &= ~(TGCR_RST2 | TGCR_FRZ2 | TGCR_STP2);
163 immr->im_sit.sit_piscr &= ~PISCR_PTE;
165 #if defined(CONFIG_MPC866_et_al)
166 /* not using OSCM, using XIN, so scale appropriately */
167 return (((timer2_val + 2) / 4) * (CFG_8XX_XIN/512))/8192 * 100000L;
169 return ((timer2_val + 2) / 4) * 100000L; /* convert to Hz */
174 * get_clocks() fills in gd->cpu_clock depending on CONFIG_8xx_GCLK_FREQ
175 * or (if it is not defined) measure_gclk() (which uses the ref clock)
178 int get_clocks (void)
180 DECLARE_GLOBAL_DATA_PTR;
182 volatile immap_t *immr = (immap_t *) CFG_IMMR;
183 #ifndef CONFIG_8xx_GCLK_FREQ
184 gd->cpu_clk = measure_gclk();
185 #else /* CONFIG_8xx_GCLK_FREQ */
187 * If for some reason measuring the gclk frequency won't
188 * work, we return the hardwired value.
189 * (For example, the cogent CMA286-60 CPU module has no
190 * separate oscillator for PITRTCLK)
193 gd->cpu_clk = CONFIG_8xx_GCLK_FREQ;
195 #endif /* CONFIG_8xx_GCLK_FREQ */
197 if ((immr->im_clkrst.car_sccr & SCCR_EBDF11) == 0) {
198 /* No Bus Divider active */
199 gd->bus_clk = gd->cpu_clk;
201 /* The MPC8xx has only one BDF: half clock speed */
202 gd->bus_clk = gd->cpu_clk / 2;
208 #else /* CONFIG_MPC866_et_al */
210 static long init_pll_866 (long clk);
212 /* This function sets up PLL (init_pll_866() is called) and
213 * fills gd->cpu_clk and gd->bus_clk according to the environment
214 * variable 'cpuclk' or to CFG_866_CPUCLK_DEFAULT (if 'cpuclk'
215 * contains invalid value).
216 * This functions requires an MPC866 series CPU.
218 int get_clocks_866 (void)
220 DECLARE_GLOBAL_DATA_PTR;
222 volatile immap_t *immr = (immap_t *) CFG_IMMR;
226 if (getenv_r ("cpuclk", tmp, sizeof (tmp)) > 0)
227 cpuclk = simple_strtoul (tmp, NULL, 10) * 1000000;
229 if ((CFG_866_CPUCLK_MIN > cpuclk) || (CFG_866_CPUCLK_MAX < cpuclk))
230 cpuclk = CFG_866_CPUCLK_DEFAULT;
232 gd->cpu_clk = init_pll_866 (cpuclk);
234 if ((immr->im_clkrst.car_sccr & SCCR_EBDF11) == 0)
235 gd->bus_clk = gd->cpu_clk;
237 gd->bus_clk = gd->cpu_clk / 2;
242 /* Adjust sdram refresh rate to actual CPU clock.
244 int sdram_adjust_866 (void)
246 DECLARE_GLOBAL_DATA_PTR;
248 volatile immap_t *immr = (immap_t *) CFG_IMMR;
251 mamr = immr->im_memctl.memc_mamr;
252 mamr &= ~MAMR_PTA_MSK;
253 mamr |= ((gd->cpu_clk / CFG_866_PTA_PER_CLK) << MAMR_PTA_SHIFT);
254 immr->im_memctl.memc_mamr = mamr;
259 /* Configure PLL for MPC866/859 CPU series
260 * PLL multiplication factor is set to the value nearest to the desired clk,
261 * assuming a oscclk of 10 MHz.
263 static long init_pll_866 (long clk)
265 extern void plprcr_write_866 (long);
267 volatile immap_t *immr = (immap_t *) CFG_IMMR;
269 char mfi, mfn, mfd, s, pdf;
270 long step_mfi, step_mfn;
273 if (clk < 80000000) {
275 step_mfi = CFG_866_OSCCLK / 2;
277 step_mfn = CFG_866_OSCCLK / 30;
280 step_mfi = CFG_866_OSCCLK;
282 step_mfn = CFG_866_OSCCLK / 30;
285 /* Calculate integer part of multiplication factor
290 /* Calculate numerator of fractional part of multiplication factor
292 n = clk - (n * step_mfi);
293 mfn = (char)(n / step_mfn);
295 /* Calculate effective clk
297 n = (mfi * step_mfi) + (mfn * step_mfn);
299 immr->im_clkrstk.cark_plprcrk = KAPWR_KEY;
301 plprcr = (immr->im_clkrst.car_plprcr & ~(PLPRCR_MFN_MSK
302 | PLPRCR_MFD_MSK | PLPRCR_S_MSK
303 | PLPRCR_MFI_MSK | PLPRCR_DBRMO))
304 | (mfn << PLPRCR_MFN_SHIFT)
305 | (mfd << PLPRCR_MFD_SHIFT)
306 | (s << PLPRCR_S_SHIFT)
307 | (mfi << PLPRCR_MFI_SHIFT)
308 | (pdf << PLPRCR_PDF_SHIFT);
310 if( (mfn > 0) && ((mfd / mfn) > 10) )
311 plprcr |= PLPRCR_DBRMO;
313 plprcr_write_866 (plprcr); /* set value using SIU4/9 workaround */
314 immr->im_clkrstk.cark_plprcrk = 0x00000000;
319 #endif /* CONFIG_MPC866_et_al */
321 /* ------------------------------------------------------------------------- */