3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
30 #if !defined(CONFIG_8xx_CONS_NONE) /* No Console at all */
32 #if defined(CONFIG_8xx_CONS_SMC1) /* Console on SMC1 */
34 #define PROFF_SMC PROFF_SMC1
35 #define CPM_CR_CH_SMC CPM_CR_CH_SMC1
37 #elif defined(CONFIG_8xx_CONS_SMC2) /* Console on SMC2 */
39 #define PROFF_SMC PROFF_SMC2
40 #define CPM_CR_CH_SMC CPM_CR_CH_SMC2
42 #endif /* CONFIG_8xx_CONS_SMCx */
44 #if defined(CONFIG_8xx_CONS_SCC1) /* Console on SCC1 */
46 #define PROFF_SCC PROFF_SCC1
47 #define CPM_CR_CH_SCC CPM_CR_CH_SCC1
49 #elif defined(CONFIG_8xx_CONS_SCC2) /* Console on SCC2 */
51 #define PROFF_SCC PROFF_SCC2
52 #define CPM_CR_CH_SCC CPM_CR_CH_SCC2
54 #elif defined(CONFIG_8xx_CONS_SCC3) /* Console on SCC3 */
56 #define PROFF_SCC PROFF_SCC3
57 #define CPM_CR_CH_SCC CPM_CR_CH_SCC3
59 #elif defined(CONFIG_8xx_CONS_SCC4) /* Console on SCC4 */
61 #define PROFF_SCC PROFF_SCC4
62 #define CPM_CR_CH_SCC CPM_CR_CH_SCC4
64 #endif /* CONFIG_8xx_CONS_SCCx */
66 static void serial_setdivisor(volatile cpm8xx_t *cp)
68 DECLARE_GLOBAL_DATA_PTR;
69 int divisor=(gd->cpu_clk + 8*gd->baudrate)/16/gd->baudrate;
71 if(divisor/16>0x1000) {
72 /* bad divisor, assume 50Mhz clock and 9600 baud */
73 divisor=(50*1000*1000 + 8*9600)/16/9600;
76 #ifdef CFG_BRGCLK_PRESCALE
77 divisor /= CFG_BRGCLK_PRESCALE;
81 cp->cp_brgc1=((divisor-1)<<1) | CPM_BRG_EN;
83 cp->cp_brgc1=((divisor/16-1)<<1) | CPM_BRG_EN | CPM_BRG_DIV16;
87 #if (defined (CONFIG_8xx_CONS_SMC1) || defined (CONFIG_8xx_CONS_SMC2))
90 * Minimal serial functions needed to use one of the SMC ports
91 * as serial console interface.
94 static void smc_setbrg (void)
96 volatile immap_t *im = (immap_t *)CFG_IMMR;
97 volatile cpm8xx_t *cp = &(im->im_cpm);
99 /* Set up the baud rate generator.
100 * See 8xx_io/commproc.c for details.
105 cp->cp_simode = 0x00000000;
107 serial_setdivisor(cp);
110 static int smc_init (void)
112 volatile immap_t *im = (immap_t *)CFG_IMMR;
114 volatile smc_uart_t *up;
115 volatile cbd_t *tbdf, *rbdf;
116 volatile cpm8xx_t *cp = &(im->im_cpm);
117 #if (!defined(CONFIG_8xx_CONS_SMC1)) && (defined(CONFIG_MPC823) || defined(CONFIG_MPC850))
118 volatile iop8xx_t *ip = (iop8xx_t *)&(im->im_ioport);
122 /* initialize pointers to SMC */
124 sp = (smc_t *) &(cp->cp_smc[SMC_INDEX]);
125 up = (smc_uart_t *) &cp->cp_dparam[PROFF_SMC];
127 /* Disable transmitter/receiver.
129 sp->smc_smcmr &= ~(SMCMR_REN | SMCMR_TEN);
133 im->im_siu_conf.sc_sdcr = 1;
135 /* clear error conditions */
137 im->im_sdma.sdma_sdsr = CFG_SDSR;
139 im->im_sdma.sdma_sdsr = 0x83;
142 /* clear SDMA interrupt mask */
144 im->im_sdma.sdma_sdmr = CFG_SDMR;
146 im->im_sdma.sdma_sdmr = 0x00;
149 #if defined(CONFIG_8xx_CONS_SMC1)
150 /* Use Port B for SMC1 instead of other functions.
152 cp->cp_pbpar |= 0x000000c0;
153 cp->cp_pbdir &= ~0x000000c0;
154 cp->cp_pbodr &= ~0x000000c0;
155 #else /* CONFIG_8xx_CONS_SMC2 */
156 # if defined(CONFIG_MPC823) || defined(CONFIG_MPC850)
157 /* Use Port A for SMC2 instead of other functions.
159 ip->iop_papar |= 0x00c0;
160 ip->iop_padir &= ~0x00c0;
161 ip->iop_paodr &= ~0x00c0;
162 # else /* must be a 860 then */
163 /* Use Port B for SMC2 instead of other functions.
165 cp->cp_pbpar |= 0x00000c00;
166 cp->cp_pbdir &= ~0x00000c00;
167 cp->cp_pbodr &= ~0x00000c00;
171 #if defined(CONFIG_FADS) || defined(CONFIG_ADS)
173 #if defined(CONFIG_8xx_CONS_SMC1)
174 *((uint *) BCSR1) &= ~BCSR1_RS232EN_1;
176 *((uint *) BCSR1) &= ~BCSR1_RS232EN_2;
178 #endif /* CONFIG_FADS */
180 #if defined(CONFIG_RPXLITE) || defined(CONFIG_RPXCLASSIC)
181 /* Enable Monitor Port Transceiver */
182 *((uchar *) BCSR0) |= BCSR0_ENMONXCVR ;
183 #endif /* CONFIG_RPXLITE */
185 /* Set the physical address of the host memory buffers in
186 * the buffer descriptors.
189 #ifdef CFG_ALLOC_DPRAM
190 dpaddr = dpram_alloc_align (sizeof(cbd_t)*2 + 2, 8) ;
192 dpaddr = CPM_SERIAL_BASE ;
195 /* Allocate space for two buffer descriptors in the DP ram.
196 * For now, this address seems OK, but it may have to
197 * change with newer versions of the firmware.
198 * damm: allocating space after the two buffers for rx/tx data
201 rbdf = (cbd_t *)&cp->cp_dpmem[dpaddr];
202 rbdf->cbd_bufaddr = (uint) (rbdf+2);
205 tbdf->cbd_bufaddr = ((uint) (rbdf+2)) + 1;
208 /* Set up the uart parameters in the parameter ram.
210 up->smc_rbase = dpaddr;
211 up->smc_tbase = dpaddr+sizeof(cbd_t);
212 up->smc_rfcr = SMC_EB;
213 up->smc_tfcr = SMC_EB;
215 #if defined(CONFIG_MBX)
217 #endif /* CONFIG_MBX */
219 /* Set UART mode, 8 bit, no parity, one stop.
220 * Enable receive and transmit.
222 sp->smc_smcmr = smcr_mk_clen(9) | SMCMR_SM_UART;
224 /* Mask all interrupts and remove anything pending.
229 /* Set up the baud rate generator.
233 /* Make the first buffer the only buffer.
235 tbdf->cbd_sc |= BD_SC_WRAP;
236 rbdf->cbd_sc |= BD_SC_EMPTY | BD_SC_WRAP;
238 /* Single character receive.
243 /* Initialize Tx/Rx parameters.
246 while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */
249 cp->cp_cpcr = mk_cr_cmd(CPM_CR_CH_SMC, CPM_CR_INIT_TRX) | CPM_CR_FLG;
251 while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */
254 /* Enable transmitter/receiver.
256 sp->smc_smcmr |= SMCMR_REN | SMCMR_TEN;
262 smc_putc(const char c)
264 volatile cbd_t *tbdf;
266 volatile smc_uart_t *up;
267 volatile immap_t *im = (immap_t *)CFG_IMMR;
268 volatile cpm8xx_t *cpmp = &(im->im_cpm);
270 #ifdef CONFIG_MODEM_SUPPORT
271 DECLARE_GLOBAL_DATA_PTR;
280 up = (smc_uart_t *)&cpmp->cp_dparam[PROFF_SMC];
282 tbdf = (cbd_t *)&cpmp->cp_dpmem[up->smc_tbase];
284 /* Wait for last character to go.
287 buf = (char *)tbdf->cbd_bufaddr;
290 tbdf->cbd_datlen = 1;
291 tbdf->cbd_sc |= BD_SC_READY;
294 while (tbdf->cbd_sc & BD_SC_READY) {
301 smc_puts (const char *s)
311 volatile cbd_t *rbdf;
312 volatile unsigned char *buf;
313 volatile smc_uart_t *up;
314 volatile immap_t *im = (immap_t *)CFG_IMMR;
315 volatile cpm8xx_t *cpmp = &(im->im_cpm);
318 up = (smc_uart_t *)&cpmp->cp_dparam[PROFF_SMC];
320 rbdf = (cbd_t *)&cpmp->cp_dpmem[up->smc_rbase];
322 /* Wait for character to show up.
324 buf = (unsigned char *)rbdf->cbd_bufaddr;
326 while (rbdf->cbd_sc & BD_SC_EMPTY)
330 rbdf->cbd_sc |= BD_SC_EMPTY;
338 volatile cbd_t *rbdf;
339 volatile smc_uart_t *up;
340 volatile immap_t *im = (immap_t *)CFG_IMMR;
341 volatile cpm8xx_t *cpmp = &(im->im_cpm);
343 up = (smc_uart_t *)&cpmp->cp_dparam[PROFF_SMC];
345 rbdf = (cbd_t *)&cpmp->cp_dpmem[up->smc_rbase];
347 return(!(rbdf->cbd_sc & BD_SC_EMPTY));
350 struct serial_device serial_smc_device =
362 #endif /* CONFIG_8xx_CONS_SMC1 || CONFIG_8xx_CONS_SMC2 */
364 #if defined(CONFIG_8xx_CONS_SCC1) || defined(CONFIG_8xx_CONS_SCC2) || \
365 defined(CONFIG_8xx_CONS_SCC3) || defined(CONFIG_8xx_CONS_SCC4)
370 volatile immap_t *im = (immap_t *)CFG_IMMR;
371 volatile cpm8xx_t *cp = &(im->im_cpm);
373 /* Set up the baud rate generator.
374 * See 8xx_io/commproc.c for details.
379 cp->cp_sicr &= ~(0x000000FF << (8 * SCC_INDEX));
381 serial_setdivisor(cp);
384 static int scc_init (void)
386 volatile immap_t *im = (immap_t *)CFG_IMMR;
388 volatile scc_uart_t *up;
389 volatile cbd_t *tbdf, *rbdf;
390 volatile cpm8xx_t *cp = &(im->im_cpm);
392 #if (SCC_INDEX != 2) || !defined(CONFIG_MPC850)
393 volatile iop8xx_t *ip = (iop8xx_t *)&(im->im_ioport);
396 /* initialize pointers to SCC */
398 sp = (scc_t *) &(cp->cp_scc[SCC_INDEX]);
399 up = (scc_uart_t *) &cp->cp_dparam[PROFF_SCC];
401 #if defined(CONFIG_LWMON) && defined(CONFIG_8xx_CONS_SCC2)
402 { /* Disable Ethernet, enable Serial */
406 c &= ~0x40; /* enable COM3 */
407 c |= 0x80; /* disable Ethernet */
411 cp->cp_pbpar |= 0x2000;
412 cp->cp_pbdat |= 0x2000;
413 cp->cp_pbdir |= 0x2000;
415 #endif /* CONFIG_LWMON */
417 /* Disable transmitter/receiver.
419 sp->scc_gsmrl &= ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
421 #if (SCC_INDEX == 2) && defined(CONFIG_MPC850)
423 * The MPC850 has SCC3 on Port B
425 cp->cp_pbpar |= 0x06;
426 cp->cp_pbdir &= ~0x06;
427 cp->cp_pbodr &= ~0x06;
429 #elif (SCC_INDEX < 2) || !defined(CONFIG_IP860)
431 * Standard configuration for SCC's is on Part A
433 ip->iop_papar |= ((3 << (2 * SCC_INDEX)));
434 ip->iop_padir &= ~((3 << (2 * SCC_INDEX)));
435 ip->iop_paodr &= ~((3 << (2 * SCC_INDEX)));
438 * The IP860 has SCC3 and SCC4 on Port D
440 ip->iop_pdpar |= ((3 << (2 * SCC_INDEX)));
443 /* Allocate space for two buffer descriptors in the DP ram.
446 #ifdef CFG_ALLOC_DPRAM
447 dpaddr = dpram_alloc_align (sizeof(cbd_t)*2 + 2, 8) ;
449 dpaddr = CPM_SERIAL2_BASE ;
454 im->im_siu_conf.sc_sdcr = 0x0001;
456 /* Set the physical address of the host memory buffers in
457 * the buffer descriptors.
460 rbdf = (cbd_t *)&cp->cp_dpmem[dpaddr];
461 rbdf->cbd_bufaddr = (uint) (rbdf+2);
464 tbdf->cbd_bufaddr = ((uint) (rbdf+2)) + 1;
467 /* Set up the baud rate generator.
471 /* Set up the uart parameters in the parameter ram.
473 up->scc_genscc.scc_rbase = dpaddr;
474 up->scc_genscc.scc_tbase = dpaddr+sizeof(cbd_t);
476 /* Initialize Tx/Rx parameters.
478 while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */
480 cp->cp_cpcr = mk_cr_cmd(CPM_CR_CH_SCC, CPM_CR_INIT_TRX) | CPM_CR_FLG;
482 while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */
485 up->scc_genscc.scc_rfcr = SCC_EB | 0x05;
486 up->scc_genscc.scc_tfcr = SCC_EB | 0x05;
488 up->scc_genscc.scc_mrblr = 1; /* Single character receive */
489 up->scc_maxidl = 0; /* disable max idle */
490 up->scc_brkcr = 1; /* send one break character on stop TX */
498 up->scc_char1 = 0x8000;
499 up->scc_char2 = 0x8000;
500 up->scc_char3 = 0x8000;
501 up->scc_char4 = 0x8000;
502 up->scc_char5 = 0x8000;
503 up->scc_char6 = 0x8000;
504 up->scc_char7 = 0x8000;
505 up->scc_char8 = 0x8000;
506 up->scc_rccm = 0xc0ff;
508 /* Set low latency / small fifo.
510 sp->scc_gsmrh = SCC_GSMRH_RFW;
512 /* Set SCC(x) clock mode to 16x
513 * See 8xx_io/commproc.c for details.
518 /* Set UART mode, clock divider 16 on Tx and Rx
520 sp->scc_gsmrl &= ~0xF;
522 (SCC_GSMRL_MODE_UART | SCC_GSMRL_TDCR_16 | SCC_GSMRL_RDCR_16);
525 sp->scc_psmr |= SCU_PSMR_CL;
527 /* Mask all interrupts and remove anything pending.
530 sp->scc_scce = 0xffff;
531 sp->scc_dsr = 0x7e7e;
532 sp->scc_psmr = 0x3000;
534 /* Make the first buffer the only buffer.
536 tbdf->cbd_sc |= BD_SC_WRAP;
537 rbdf->cbd_sc |= BD_SC_EMPTY | BD_SC_WRAP;
539 /* Enable transmitter/receiver.
541 sp->scc_gsmrl |= (SCC_GSMRL_ENR | SCC_GSMRL_ENT);
547 scc_putc(const char c)
549 volatile cbd_t *tbdf;
551 volatile scc_uart_t *up;
552 volatile immap_t *im = (immap_t *)CFG_IMMR;
553 volatile cpm8xx_t *cpmp = &(im->im_cpm);
555 #ifdef CONFIG_MODEM_SUPPORT
556 DECLARE_GLOBAL_DATA_PTR;
565 up = (scc_uart_t *)&cpmp->cp_dparam[PROFF_SCC];
567 tbdf = (cbd_t *)&cpmp->cp_dpmem[up->scc_genscc.scc_tbase];
569 /* Wait for last character to go.
572 buf = (char *)tbdf->cbd_bufaddr;
575 tbdf->cbd_datlen = 1;
576 tbdf->cbd_sc |= BD_SC_READY;
579 while (tbdf->cbd_sc & BD_SC_READY) {
586 scc_puts (const char *s)
596 volatile cbd_t *rbdf;
597 volatile unsigned char *buf;
598 volatile scc_uart_t *up;
599 volatile immap_t *im = (immap_t *)CFG_IMMR;
600 volatile cpm8xx_t *cpmp = &(im->im_cpm);
603 up = (scc_uart_t *)&cpmp->cp_dparam[PROFF_SCC];
605 rbdf = (cbd_t *)&cpmp->cp_dpmem[up->scc_genscc.scc_rbase];
607 /* Wait for character to show up.
609 buf = (unsigned char *)rbdf->cbd_bufaddr;
611 while (rbdf->cbd_sc & BD_SC_EMPTY)
615 rbdf->cbd_sc |= BD_SC_EMPTY;
623 volatile cbd_t *rbdf;
624 volatile scc_uart_t *up;
625 volatile immap_t *im = (immap_t *)CFG_IMMR;
626 volatile cpm8xx_t *cpmp = &(im->im_cpm);
628 up = (scc_uart_t *)&cpmp->cp_dparam[PROFF_SCC];
630 rbdf = (cbd_t *)&cpmp->cp_dpmem[up->scc_genscc.scc_rbase];
632 return(!(rbdf->cbd_sc & BD_SC_EMPTY));
635 struct serial_device serial_scc_device =
647 #endif /* CONFIG_8xx_CONS_SCCx */
649 #ifdef CONFIG_MODEM_SUPPORT
650 void disable_putc(void)
652 DECLARE_GLOBAL_DATA_PTR;
656 void enable_putc(void)
658 DECLARE_GLOBAL_DATA_PTR;
663 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
666 kgdb_serial_init(void)
670 if (strcmp(default_serial_console()->ctlr, "SMC") == 0)
672 #if defined(CONFIG_8xx_CONS_SMC1)
674 #elif defined(CONFIG_8xx_CONS_SMC2)
678 else if (strcmp(default_serial_console()->ctlr, "SMC") == 0)
680 #if defined(CONFIG_8xx_CONS_SCC1)
682 #elif defined(CONFIG_8xx_CONS_SCC2)
684 #elif defined(CONFIG_8xx_CONS_SCC3)
686 #elif defined(CONFIG_8xx_CONS_SCC4)
693 serial_printf("[on %s%d] ", default_serial_console()->ctlr, i);
704 putDebugStr (const char *str)
712 return serial_getc();
716 kgdb_interruptible (int yes)
720 #endif /* CFG_CMD_KGDB */
722 #endif /* CONFIG_8xx_CONS_NONE */