3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29 #if !defined(CONFIG_8xx_CONS_NONE) /* No Console at all */
31 #if defined(CONFIG_8xx_CONS_SMC1) /* Console on SMC1 */
34 #define PROFF_SMC PROFF_SMC1
35 #define CPM_CR_CH_SMC CPM_CR_CH_SMC1
37 #elif defined(CONFIG_8xx_CONS_SMC2) /* Console on SMC2 */
40 #define PROFF_SMC PROFF_SMC2
41 #define CPM_CR_CH_SMC CPM_CR_CH_SMC2
43 #elif defined(CONFIG_8xx_CONS_SCC1) /* Console on SCC1 */
46 #define PROFF_SCC PROFF_SCC1
47 #define CPM_CR_CH_SCC CPM_CR_CH_SCC1
49 #elif defined(CONFIG_8xx_CONS_SCC2) /* Console on SCC2 */
52 #define PROFF_SCC PROFF_SCC2
53 #define CPM_CR_CH_SCC CPM_CR_CH_SCC2
55 #elif defined(CONFIG_8xx_CONS_SCC3) /* Console on SCC3 */
58 #define PROFF_SCC PROFF_SCC3
59 #define CPM_CR_CH_SCC CPM_CR_CH_SCC3
61 #elif defined(CONFIG_8xx_CONS_SCC4) /* Console on SCC4 */
64 #define PROFF_SCC PROFF_SCC4
65 #define CPM_CR_CH_SCC CPM_CR_CH_SCC4
67 #else /* CONFIG_8xx_CONS_? */
68 #error "console not correctly defined"
71 static void serial_setdivisor(volatile cpm8xx_t *cp)
73 DECLARE_GLOBAL_DATA_PTR;
74 int divisor=gd->cpu_clk/16/gd->baudrate;
76 if(divisor/16>0x1000) {
77 /* bad divisor, assume 50Mhz clock and 9600 baud */
78 divisor=(50*1000*1000)/16/9600;
81 #ifdef CFG_BRGCLK_PRESCALE
82 divisor /= CFG_BRGCLK_PRESCALE;
86 cp->cp_brgc1=((divisor-1)<<1) | CPM_BRG_EN;
88 cp->cp_brgc1=((divisor/16-1)<<1) | CPM_BRG_EN | CPM_BRG_DIV16;
92 #if (defined (CONFIG_8xx_CONS_SMC1) || defined (CONFIG_8xx_CONS_SMC2))
95 * Minimal serial functions needed to use one of the SMC ports
96 * as serial console interface.
99 int serial_init (void)
101 volatile immap_t *im = (immap_t *)CFG_IMMR;
103 volatile smc_uart_t *up;
104 volatile cbd_t *tbdf, *rbdf;
105 volatile cpm8xx_t *cp = &(im->im_cpm);
106 #if (!defined(CONFIG_8xx_CONS_SMC1)) && (defined(CONFIG_MPC823) || defined(CONFIG_MPC850))
107 volatile iop8xx_t *ip = (iop8xx_t *)&(im->im_ioport);
111 /* initialize pointers to SMC */
113 sp = (smc_t *) &(cp->cp_smc[SMC_INDEX]);
114 up = (smc_uart_t *) &cp->cp_dparam[PROFF_SMC];
116 /* Disable transmitter/receiver.
118 sp->smc_smcmr &= ~(SMCMR_REN | SMCMR_TEN);
122 im->im_siu_conf.sc_sdcr = 1;
124 /* clear error conditions */
126 im->im_sdma.sdma_sdsr = CFG_SDSR;
128 im->im_sdma.sdma_sdsr = 0x83;
131 /* clear SDMA interrupt mask */
133 im->im_sdma.sdma_sdmr = CFG_SDMR;
135 im->im_sdma.sdma_sdmr = 0x00;
138 #if defined(CONFIG_8xx_CONS_SMC1)
139 /* Use Port B for SMC1 instead of other functions.
141 cp->cp_pbpar |= 0x000000c0;
142 cp->cp_pbdir &= ~0x000000c0;
143 cp->cp_pbodr &= ~0x000000c0;
144 #else /* CONFIG_8xx_CONS_SMC2 */
145 # if defined(CONFIG_MPC823) || defined(CONFIG_MPC850)
146 /* Use Port A for SMC2 instead of other functions.
148 ip->iop_papar |= 0x00c0;
149 ip->iop_padir &= ~0x00c0;
150 ip->iop_paodr &= ~0x00c0;
151 # else /* must be a 860 then */
152 /* Use Port B for SMC2 instead of other functions.
154 cp->cp_pbpar |= 0x00000c00;
155 cp->cp_pbdir &= ~0x00000c00;
156 cp->cp_pbodr &= ~0x00000c00;
160 #if defined(CONFIG_FADS) || defined(CONFIG_ADS)
162 #if defined(CONFIG_8xx_CONS_SMC1)
163 *((uint *) BCSR1) &= ~BCSR1_RS232EN_1;
165 *((uint *) BCSR1) &= ~BCSR1_RS232EN_2;
167 #endif /* CONFIG_FADS */
169 #if defined(CONFIG_RPXLITE) || defined(CONFIG_RPXCLASSIC)
170 /* Enable Monitor Port Transceiver */
171 *((uchar *) BCSR0) |= BCSR0_ENMONXCVR ;
172 #endif /* CONFIG_RPXLITE */
174 /* Set the physical address of the host memory buffers in
175 * the buffer descriptors.
178 #ifdef CFG_ALLOC_DPRAM
179 dpaddr = dpram_alloc_align (sizeof(cbd_t)*2 + 2, 8) ;
181 dpaddr = CPM_SERIAL_BASE ;
184 /* Allocate space for two buffer descriptors in the DP ram.
185 * For now, this address seems OK, but it may have to
186 * change with newer versions of the firmware.
187 * damm: allocating space after the two buffers for rx/tx data
190 rbdf = (cbd_t *)&cp->cp_dpmem[dpaddr];
191 rbdf->cbd_bufaddr = (uint) (rbdf+2);
194 tbdf->cbd_bufaddr = ((uint) (rbdf+2)) + 1;
197 /* Set up the uart parameters in the parameter ram.
199 up->smc_rbase = dpaddr;
200 up->smc_tbase = dpaddr+sizeof(cbd_t);
201 up->smc_rfcr = SMC_EB;
202 up->smc_tfcr = SMC_EB;
204 #if defined(CONFIG_MBX)
206 #endif /* CONFIG_MBX */
208 /* Set UART mode, 8 bit, no parity, one stop.
209 * Enable receive and transmit.
211 sp->smc_smcmr = smcr_mk_clen(9) | SMCMR_SM_UART;
213 /* Mask all interrupts and remove anything pending.
218 /* Set up the baud rate generator.
222 /* Make the first buffer the only buffer.
224 tbdf->cbd_sc |= BD_SC_WRAP;
225 rbdf->cbd_sc |= BD_SC_EMPTY | BD_SC_WRAP;
227 /* Single character receive.
232 /* Initialize Tx/Rx parameters.
235 while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */
238 cp->cp_cpcr = mk_cr_cmd(CPM_CR_CH_SMC, CPM_CR_INIT_TRX) | CPM_CR_FLG;
240 while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */
243 /* Enable transmitter/receiver.
245 sp->smc_smcmr |= SMCMR_REN | SMCMR_TEN;
253 volatile immap_t *im = (immap_t *)CFG_IMMR;
254 volatile cpm8xx_t *cp = &(im->im_cpm);
256 /* Set up the baud rate generator.
257 * See 8xx_io/commproc.c for details.
262 cp->cp_simode = 0x00000000;
264 serial_setdivisor(cp);
267 #ifdef CONFIG_MODEM_SUPPORT
268 void disable_putc(void)
270 DECLARE_GLOBAL_DATA_PTR;
274 void enable_putc(void)
276 DECLARE_GLOBAL_DATA_PTR;
282 serial_putc(const char c)
284 volatile cbd_t *tbdf;
286 volatile smc_uart_t *up;
287 volatile immap_t *im = (immap_t *)CFG_IMMR;
288 volatile cpm8xx_t *cpmp = &(im->im_cpm);
290 #ifdef CONFIG_MODEM_SUPPORT
291 DECLARE_GLOBAL_DATA_PTR;
300 up = (smc_uart_t *)&cpmp->cp_dparam[PROFF_SMC];
302 tbdf = (cbd_t *)&cpmp->cp_dpmem[up->smc_tbase];
304 /* Wait for last character to go.
307 buf = (char *)tbdf->cbd_bufaddr;
310 tbdf->cbd_datlen = 1;
311 tbdf->cbd_sc |= BD_SC_READY;
314 while (tbdf->cbd_sc & BD_SC_READY) {
323 volatile cbd_t *rbdf;
324 volatile unsigned char *buf;
325 volatile smc_uart_t *up;
326 volatile immap_t *im = (immap_t *)CFG_IMMR;
327 volatile cpm8xx_t *cpmp = &(im->im_cpm);
330 up = (smc_uart_t *)&cpmp->cp_dparam[PROFF_SMC];
332 rbdf = (cbd_t *)&cpmp->cp_dpmem[up->smc_rbase];
334 /* Wait for character to show up.
336 buf = (unsigned char *)rbdf->cbd_bufaddr;
338 while (rbdf->cbd_sc & BD_SC_EMPTY)
342 rbdf->cbd_sc |= BD_SC_EMPTY;
350 volatile cbd_t *rbdf;
351 volatile smc_uart_t *up;
352 volatile immap_t *im = (immap_t *)CFG_IMMR;
353 volatile cpm8xx_t *cpmp = &(im->im_cpm);
355 up = (smc_uart_t *)&cpmp->cp_dparam[PROFF_SMC];
357 rbdf = (cbd_t *)&cpmp->cp_dpmem[up->smc_rbase];
359 return(!(rbdf->cbd_sc & BD_SC_EMPTY));
362 #else /* ! CONFIG_8xx_CONS_SMC1, CONFIG_8xx_CONS_SMC2 */
364 int serial_init (void)
366 volatile immap_t *im = (immap_t *)CFG_IMMR;
368 volatile scc_uart_t *up;
369 volatile cbd_t *tbdf, *rbdf;
370 volatile cpm8xx_t *cp = &(im->im_cpm);
372 #if (SCC_INDEX != 2) || !defined(CONFIG_MPC850)
373 volatile iop8xx_t *ip = (iop8xx_t *)&(im->im_ioport);
376 /* initialize pointers to SCC */
378 sp = (scc_t *) &(cp->cp_scc[SCC_INDEX]);
379 up = (scc_uart_t *) &cp->cp_dparam[PROFF_SCC];
381 #if defined(CONFIG_LWMON) && defined(CONFIG_8xx_CONS_SCC2)
382 { /* Disable Ethernet, enable Serial */
386 c &= ~0x40; /* enable COM3 */
387 c |= 0x80; /* disable Ethernet */
391 cp->cp_pbpar |= 0x2000;
392 cp->cp_pbdat |= 0x2000;
393 cp->cp_pbdir |= 0x2000;
395 #endif /* CONFIG_LWMON */
397 /* Disable transmitter/receiver.
399 sp->scc_gsmrl &= ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
401 #if (SCC_INDEX == 2) && defined(CONFIG_MPC850)
403 * The MPC850 has SCC3 on Port B
405 cp->cp_pbpar |= 0x06;
406 cp->cp_pbdir &= ~0x06;
407 cp->cp_pbodr &= ~0x06;
409 #elif (SCC_INDEX < 2) || !defined(CONFIG_IP860)
411 * Standard configuration for SCC's is on Part A
413 ip->iop_papar |= ((3 << (2 * SCC_INDEX)));
414 ip->iop_padir &= ~((3 << (2 * SCC_INDEX)));
415 ip->iop_paodr &= ~((3 << (2 * SCC_INDEX)));
418 * The IP860 has SCC3 and SCC4 on Port D
420 ip->iop_pdpar |= ((3 << (2 * SCC_INDEX)));
423 /* Allocate space for two buffer descriptors in the DP ram.
426 #ifdef CFG_ALLOC_DPRAM
427 dpaddr = dpram_alloc_align (sizeof(cbd_t)*2 + 2, 8) ;
429 dpaddr = CPM_SERIAL_BASE ;
434 im->im_siu_conf.sc_sdcr = 0x0001;
436 /* Set the physical address of the host memory buffers in
437 * the buffer descriptors.
440 rbdf = (cbd_t *)&cp->cp_dpmem[dpaddr];
441 rbdf->cbd_bufaddr = (uint) (rbdf+2);
444 tbdf->cbd_bufaddr = ((uint) (rbdf+2)) + 1;
447 /* Set up the baud rate generator.
451 /* Set up the uart parameters in the parameter ram.
453 up->scc_genscc.scc_rbase = dpaddr;
454 up->scc_genscc.scc_tbase = dpaddr+sizeof(cbd_t);
456 /* Initialize Tx/Rx parameters.
458 while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */
460 cp->cp_cpcr = mk_cr_cmd(CPM_CR_CH_SCC, CPM_CR_INIT_TRX) | CPM_CR_FLG;
462 while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */
465 up->scc_genscc.scc_rfcr = SCC_EB | 0x05;
466 up->scc_genscc.scc_tfcr = SCC_EB | 0x05;
468 up->scc_genscc.scc_mrblr = 1; /* Single character receive */
469 up->scc_maxidl = 0; /* disable max idle */
470 up->scc_brkcr = 1; /* send one break character on stop TX */
478 up->scc_char1 = 0x8000;
479 up->scc_char2 = 0x8000;
480 up->scc_char3 = 0x8000;
481 up->scc_char4 = 0x8000;
482 up->scc_char5 = 0x8000;
483 up->scc_char6 = 0x8000;
484 up->scc_char7 = 0x8000;
485 up->scc_char8 = 0x8000;
486 up->scc_rccm = 0xc0ff;
488 /* Set low latency / small fifo.
490 sp->scc_gsmrh = SCC_GSMRH_RFW;
492 /* Set SCC(x) clock mode to 16x
493 * See 8xx_io/commproc.c for details.
498 /* Set UART mode, clock divider 16 on Tx and Rx
501 (SCC_GSMRL_MODE_UART | SCC_GSMRL_TDCR_16 | SCC_GSMRL_RDCR_16);
503 sp->scc_psmr |= SCU_PSMR_CL;
505 /* Mask all interrupts and remove anything pending.
508 sp->scc_scce = 0xffff;
509 sp->scc_dsr = 0x7e7e;
510 sp->scc_psmr = 0x3000;
512 /* Make the first buffer the only buffer.
514 tbdf->cbd_sc |= BD_SC_WRAP;
515 rbdf->cbd_sc |= BD_SC_EMPTY | BD_SC_WRAP;
517 /* Enable transmitter/receiver.
519 sp->scc_gsmrl |= (SCC_GSMRL_ENR | SCC_GSMRL_ENT);
527 volatile immap_t *im = (immap_t *)CFG_IMMR;
528 volatile cpm8xx_t *cp = &(im->im_cpm);
530 /* Set up the baud rate generator.
531 * See 8xx_io/commproc.c for details.
536 cp->cp_sicr &= ~(0x000000FF << (8 * SCC_INDEX));
538 serial_setdivisor(cp);
542 serial_putc(const char c)
544 volatile cbd_t *tbdf;
546 volatile scc_uart_t *up;
547 volatile immap_t *im = (immap_t *)CFG_IMMR;
548 volatile cpm8xx_t *cpmp = &(im->im_cpm);
553 up = (scc_uart_t *)&cpmp->cp_dparam[PROFF_SCC];
555 tbdf = (cbd_t *)&cpmp->cp_dpmem[up->scc_genscc.scc_tbase];
557 /* Wait for last character to go.
560 buf = (char *)tbdf->cbd_bufaddr;
563 tbdf->cbd_datlen = 1;
564 tbdf->cbd_sc |= BD_SC_READY;
567 while (tbdf->cbd_sc & BD_SC_READY) {
576 volatile cbd_t *rbdf;
577 volatile unsigned char *buf;
578 volatile scc_uart_t *up;
579 volatile immap_t *im = (immap_t *)CFG_IMMR;
580 volatile cpm8xx_t *cpmp = &(im->im_cpm);
583 up = (scc_uart_t *)&cpmp->cp_dparam[PROFF_SCC];
585 rbdf = (cbd_t *)&cpmp->cp_dpmem[up->scc_genscc.scc_rbase];
587 /* Wait for character to show up.
589 buf = (unsigned char *)rbdf->cbd_bufaddr;
591 while (rbdf->cbd_sc & BD_SC_EMPTY)
595 rbdf->cbd_sc |= BD_SC_EMPTY;
603 volatile cbd_t *rbdf;
604 volatile scc_uart_t *up;
605 volatile immap_t *im = (immap_t *)CFG_IMMR;
606 volatile cpm8xx_t *cpmp = &(im->im_cpm);
608 up = (scc_uart_t *)&cpmp->cp_dparam[PROFF_SCC];
610 rbdf = (cbd_t *)&cpmp->cp_dpmem[up->scc_genscc.scc_rbase];
612 return(!(rbdf->cbd_sc & BD_SC_EMPTY));
615 #endif /* CONFIG_8xx_CONS_SMC1, CONFIG_8xx_CONS_SMC2 */
619 serial_puts (const char *s)
627 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
630 kgdb_serial_init(void)
632 #if defined(CONFIG_8xx_CONS_SMC1)
633 serial_printf("[on SMC1] ");
634 #elif defined(CONFIG_8xx_CONS_SMC2)
635 serial_printf("[on SMC2] ");
636 #elif defined(CONFIG_8xx_CONS_SCC1)
637 serial_printf("[on SCC1] ");
638 #elif defined(CONFIG_8xx_CONS_SCC2)
639 serial_printf("[on SCC2] ");
640 #elif defined(CONFIG_8xx_CONS_SCC3)
641 serial_printf("[on SCC3] ");
642 #elif defined(CONFIG_8xx_CONS_SCC4)
643 serial_printf("[on SCC4] ");
654 putDebugStr (const char *str)
662 return serial_getc();
666 kgdb_interruptible (int yes)
670 #endif /* CFG_CMD_KGDB */
672 #endif /* CONFIG_8xx_CONS_NONE */