3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29 #if !defined(CONFIG_8xx_CONS_NONE) /* No Console at all */
31 #if defined(CONFIG_8xx_CONS_SMC1) /* Console on SMC1 */
34 #define PROFF_SMC PROFF_SMC1
35 #define CPM_CR_CH_SMC CPM_CR_CH_SMC1
37 #elif defined(CONFIG_8xx_CONS_SMC2) /* Console on SMC2 */
40 #define PROFF_SMC PROFF_SMC2
41 #define CPM_CR_CH_SMC CPM_CR_CH_SMC2
43 #elif defined(CONFIG_8xx_CONS_SCC1) /* Console on SCC1 */
46 #define PROFF_SCC PROFF_SCC1
47 #define CPM_CR_CH_SCC CPM_CR_CH_SCC1
49 #elif defined(CONFIG_8xx_CONS_SCC2) /* Console on SCC2 */
52 #define PROFF_SCC PROFF_SCC2
53 #define CPM_CR_CH_SCC CPM_CR_CH_SCC2
55 #elif defined(CONFIG_8xx_CONS_SCC3) /* Console on SCC3 */
58 #define PROFF_SCC PROFF_SCC3
59 #define CPM_CR_CH_SCC CPM_CR_CH_SCC3
61 #elif defined(CONFIG_8xx_CONS_SCC4) /* Console on SCC4 */
64 #define PROFF_SCC PROFF_SCC4
65 #define CPM_CR_CH_SCC CPM_CR_CH_SCC4
67 #else /* CONFIG_8xx_CONS_? */
68 #error "console not correctly defined"
71 #if (defined (CONFIG_8xx_CONS_SMC1) || defined (CONFIG_8xx_CONS_SMC2))
74 * Minimal serial functions needed to use one of the SMC ports
75 * as serial console interface.
78 int serial_init (void)
80 volatile immap_t *im = (immap_t *)CFG_IMMR;
82 volatile smc_uart_t *up;
83 volatile cbd_t *tbdf, *rbdf;
84 volatile cpm8xx_t *cp = &(im->im_cpm);
85 #if (!defined(CONFIG_8xx_CONS_SMC1)) && (defined(CONFIG_MPC823) || defined(CONFIG_MPC850))
86 volatile iop8xx_t *ip = (iop8xx_t *)&(im->im_ioport);
90 /* initialize pointers to SMC */
92 sp = (smc_t *) &(cp->cp_smc[SMC_INDEX]);
93 up = (smc_uart_t *) &cp->cp_dparam[PROFF_SMC];
95 /* Disable transmitter/receiver.
97 sp->smc_smcmr &= ~(SMCMR_REN | SMCMR_TEN);
101 im->im_siu_conf.sc_sdcr = 1;
103 /* clear error conditions */
105 im->im_sdma.sdma_sdsr = CFG_SDSR;
107 im->im_sdma.sdma_sdsr = 0x83;
110 /* clear SDMA interrupt mask */
112 im->im_sdma.sdma_sdmr = CFG_SDMR;
114 im->im_sdma.sdma_sdmr = 0x00;
117 #if defined(CONFIG_8xx_CONS_SMC1)
118 /* Use Port B for SMC1 instead of other functions.
120 cp->cp_pbpar |= 0x000000c0;
121 cp->cp_pbdir &= ~0x000000c0;
122 cp->cp_pbodr &= ~0x000000c0;
123 #else /* CONFIG_8xx_CONS_SMC2 */
124 # if defined(CONFIG_MPC823) || defined(CONFIG_MPC850)
125 /* Use Port A for SMC2 instead of other functions.
127 ip->iop_papar |= 0x00c0;
128 ip->iop_padir &= ~0x00c0;
129 ip->iop_paodr &= ~0x00c0;
130 # else /* must be a 860 then */
131 /* Use Port B for SMC2 instead of other functions.
133 cp->cp_pbpar |= 0x00000c00;
134 cp->cp_pbdir &= ~0x00000c00;
135 cp->cp_pbodr &= ~0x00000c00;
139 #if defined(CONFIG_FADS)
141 #if defined(CONFIG_8xx_CONS_SMC1)
142 *((uint *) BCSR1) &= ~BCSR1_RS232EN_1;
144 *((uint *) BCSR1) &= ~BCSR1_RS232EN_2;
146 #endif /* CONFIG_FADS */
148 #if defined(CONFIG_RPXLITE) || defined(CONFIG_RPXCLASSIC)
149 /* Enable Monitor Port Transceiver */
150 *((uchar *) BCSR0) |= BCSR0_ENMONXCVR ;
151 #endif /* CONFIG_RPXLITE */
153 /* Set the physical address of the host memory buffers in
154 * the buffer descriptors.
157 #ifdef CFG_ALLOC_DPRAM
158 dpaddr = dpram_alloc_align (sizeof(cbd_t)*2 + 2, 8) ;
160 dpaddr = CPM_SERIAL_BASE ;
163 /* Allocate space for two buffer descriptors in the DP ram.
164 * For now, this address seems OK, but it may have to
165 * change with newer versions of the firmware.
166 * damm: allocating space after the two buffers for rx/tx data
169 rbdf = (cbd_t *)&cp->cp_dpmem[dpaddr];
170 rbdf->cbd_bufaddr = (uint) (rbdf+2);
173 tbdf->cbd_bufaddr = ((uint) (rbdf+2)) + 1;
176 /* Set up the uart parameters in the parameter ram.
178 up->smc_rbase = dpaddr;
179 up->smc_tbase = dpaddr+sizeof(cbd_t);
180 up->smc_rfcr = SMC_EB;
181 up->smc_tfcr = SMC_EB;
183 #if defined(CONFIG_MBX)
185 #endif /* CONFIG_MBX */
187 /* Set UART mode, 8 bit, no parity, one stop.
188 * Enable receive and transmit.
190 sp->smc_smcmr = smcr_mk_clen(9) | SMCMR_SM_UART;
192 /* Mask all interrupts and remove anything pending.
197 /* Set up the baud rate generator.
201 /* Make the first buffer the only buffer.
203 tbdf->cbd_sc |= BD_SC_WRAP;
204 rbdf->cbd_sc |= BD_SC_EMPTY | BD_SC_WRAP;
206 /* Single character receive.
211 /* Initialize Tx/Rx parameters.
214 while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */
217 cp->cp_cpcr = mk_cr_cmd(CPM_CR_CH_SMC, CPM_CR_INIT_TRX) | CPM_CR_FLG;
219 while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */
222 /* Enable transmitter/receiver.
224 sp->smc_smcmr |= SMCMR_REN | SMCMR_TEN;
232 DECLARE_GLOBAL_DATA_PTR;
234 volatile immap_t *im = (immap_t *)CFG_IMMR;
235 volatile cpm8xx_t *cp = &(im->im_cpm);
237 /* Set up the baud rate generator.
238 * See 8xx_io/commproc.c for details.
243 cp->cp_simode = 0x00000000;
246 (((gd->cpu_clk / 16 / gd->baudrate)-1) << 1) | CPM_BRG_EN;
250 serial_putc(const char c)
252 volatile cbd_t *tbdf;
254 volatile smc_uart_t *up;
255 volatile immap_t *im = (immap_t *)CFG_IMMR;
256 volatile cpm8xx_t *cpmp = &(im->im_cpm);
261 up = (smc_uart_t *)&cpmp->cp_dparam[PROFF_SMC];
263 tbdf = (cbd_t *)&cpmp->cp_dpmem[up->smc_tbase];
265 /* Wait for last character to go.
268 buf = (char *)tbdf->cbd_bufaddr;
271 tbdf->cbd_datlen = 1;
272 tbdf->cbd_sc |= BD_SC_READY;
275 while (tbdf->cbd_sc & BD_SC_READY) {
284 volatile cbd_t *rbdf;
285 volatile unsigned char *buf;
286 volatile smc_uart_t *up;
287 volatile immap_t *im = (immap_t *)CFG_IMMR;
288 volatile cpm8xx_t *cpmp = &(im->im_cpm);
291 up = (smc_uart_t *)&cpmp->cp_dparam[PROFF_SMC];
293 rbdf = (cbd_t *)&cpmp->cp_dpmem[up->smc_rbase];
295 /* Wait for character to show up.
297 buf = (unsigned char *)rbdf->cbd_bufaddr;
299 while (rbdf->cbd_sc & BD_SC_EMPTY)
303 rbdf->cbd_sc |= BD_SC_EMPTY;
311 volatile cbd_t *rbdf;
312 volatile smc_uart_t *up;
313 volatile immap_t *im = (immap_t *)CFG_IMMR;
314 volatile cpm8xx_t *cpmp = &(im->im_cpm);
316 up = (smc_uart_t *)&cpmp->cp_dparam[PROFF_SMC];
318 rbdf = (cbd_t *)&cpmp->cp_dpmem[up->smc_rbase];
320 return(!(rbdf->cbd_sc & BD_SC_EMPTY));
323 #else /* ! CONFIG_8xx_CONS_SMC1, CONFIG_8xx_CONS_SMC2 */
325 int serial_init (void)
327 volatile immap_t *im = (immap_t *)CFG_IMMR;
329 volatile scc_uart_t *up;
330 volatile cbd_t *tbdf, *rbdf;
331 volatile cpm8xx_t *cp = &(im->im_cpm);
333 #if (SCC_INDEX != 2) || !defined(CONFIG_MPC850)
334 volatile iop8xx_t *ip = (iop8xx_t *)&(im->im_ioport);
337 /* initialize pointers to SCC */
339 sp = (scc_t *) &(cp->cp_scc[SCC_INDEX]);
340 up = (scc_uart_t *) &cp->cp_dparam[PROFF_SCC];
342 #if defined(CONFIG_LWMON) && defined(CONFIG_8xx_CONS_SCC2)
343 { /* Disable Ethernet, enable Serial */
347 c &= ~0x40; /* enable COM3 */
348 c |= 0x80; /* disable Ethernet */
352 cp->cp_pbpar |= 0x2000;
353 cp->cp_pbdat |= 0x2000;
354 cp->cp_pbdir |= 0x2000;
356 #endif /* CONFIG_LWMON */
358 /* Disable transmitter/receiver.
360 sp->scc_gsmrl &= ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
362 #if (SCC_INDEX == 2) && defined(CONFIG_MPC850)
364 * The MPC850 has SCC3 on Port B
366 cp->cp_pbpar |= 0x06;
367 cp->cp_pbdir &= ~0x06;
368 cp->cp_pbodr &= ~0x06;
370 #elif (SCC_INDEX < 2) || !defined(CONFIG_IP860)
372 * Standard configuration for SCC's is on Part A
374 ip->iop_papar |= ((3 << (2 * SCC_INDEX)));
375 ip->iop_padir &= ~((3 << (2 * SCC_INDEX)));
376 ip->iop_paodr &= ~((3 << (2 * SCC_INDEX)));
379 * The IP860 has SCC3 and SCC4 on Port D
381 ip->iop_pdpar |= ((3 << (2 * SCC_INDEX)));
384 /* Allocate space for two buffer descriptors in the DP ram.
387 #ifdef CFG_ALLOC_DPRAM
388 dpaddr = dpram_alloc_align (sizeof(cbd_t)*2 + 2, 8) ;
390 dpaddr = CPM_SERIAL_BASE ;
395 im->im_siu_conf.sc_sdcr = 0x0001;
397 /* Set the physical address of the host memory buffers in
398 * the buffer descriptors.
401 rbdf = (cbd_t *)&cp->cp_dpmem[dpaddr];
402 rbdf->cbd_bufaddr = (uint) (rbdf+2);
405 tbdf->cbd_bufaddr = ((uint) (rbdf+2)) + 1;
408 /* Set up the baud rate generator.
412 /* Set up the uart parameters in the parameter ram.
414 up->scc_genscc.scc_rbase = dpaddr;
415 up->scc_genscc.scc_tbase = dpaddr+sizeof(cbd_t);
417 /* Initialize Tx/Rx parameters.
419 while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */
421 cp->cp_cpcr = mk_cr_cmd(CPM_CR_CH_SCC, CPM_CR_INIT_TRX) | CPM_CR_FLG;
423 while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */
426 up->scc_genscc.scc_rfcr = SCC_EB | 0x05;
427 up->scc_genscc.scc_tfcr = SCC_EB | 0x05;
429 up->scc_genscc.scc_mrblr = 1; /* Single character receive */
430 up->scc_maxidl = 0; /* disable max idle */
431 up->scc_brkcr = 1; /* send one break character on stop TX */
439 up->scc_char1 = 0x8000;
440 up->scc_char2 = 0x8000;
441 up->scc_char3 = 0x8000;
442 up->scc_char4 = 0x8000;
443 up->scc_char5 = 0x8000;
444 up->scc_char6 = 0x8000;
445 up->scc_char7 = 0x8000;
446 up->scc_char8 = 0x8000;
447 up->scc_rccm = 0xc0ff;
449 /* Set low latency / small fifo.
451 sp->scc_gsmrh = SCC_GSMRH_RFW;
453 /* Set SCC(x) clock mode to 16x
454 * See 8xx_io/commproc.c for details.
459 /* Set UART mode, clock divider 16 on Tx and Rx
462 (SCC_GSMRL_MODE_UART | SCC_GSMRL_TDCR_16 | SCC_GSMRL_RDCR_16);
464 sp->scc_psmr |= SCU_PSMR_CL;
466 /* Mask all interrupts and remove anything pending.
469 sp->scc_scce = 0xffff;
470 sp->scc_dsr = 0x7e7e;
471 sp->scc_psmr = 0x3000;
473 /* Make the first buffer the only buffer.
475 tbdf->cbd_sc |= BD_SC_WRAP;
476 rbdf->cbd_sc |= BD_SC_EMPTY | BD_SC_WRAP;
478 /* Enable transmitter/receiver.
480 sp->scc_gsmrl |= (SCC_GSMRL_ENR | SCC_GSMRL_ENT);
488 DECLARE_GLOBAL_DATA_PTR;
490 volatile immap_t *im = (immap_t *)CFG_IMMR;
491 volatile cpm8xx_t *cp = &(im->im_cpm);
493 /* Set up the baud rate generator.
494 * See 8xx_io/commproc.c for details.
499 cp->cp_sicr &= ~(0x000000FF << (8 * SCC_INDEX));
500 /* no |= needed, since BRG1 is 000 */
503 (((gd->cpu_clk / 16 / gd->baudrate)-1) << 1) | CPM_BRG_EN;
507 serial_putc(const char c)
509 volatile cbd_t *tbdf;
511 volatile scc_uart_t *up;
512 volatile immap_t *im = (immap_t *)CFG_IMMR;
513 volatile cpm8xx_t *cpmp = &(im->im_cpm);
518 up = (scc_uart_t *)&cpmp->cp_dparam[PROFF_SCC];
520 tbdf = (cbd_t *)&cpmp->cp_dpmem[up->scc_genscc.scc_tbase];
522 /* Wait for last character to go.
525 buf = (char *)tbdf->cbd_bufaddr;
528 tbdf->cbd_datlen = 1;
529 tbdf->cbd_sc |= BD_SC_READY;
532 while (tbdf->cbd_sc & BD_SC_READY) {
541 volatile cbd_t *rbdf;
542 volatile unsigned char *buf;
543 volatile scc_uart_t *up;
544 volatile immap_t *im = (immap_t *)CFG_IMMR;
545 volatile cpm8xx_t *cpmp = &(im->im_cpm);
548 up = (scc_uart_t *)&cpmp->cp_dparam[PROFF_SCC];
550 rbdf = (cbd_t *)&cpmp->cp_dpmem[up->scc_genscc.scc_rbase];
552 /* Wait for character to show up.
554 buf = (unsigned char *)rbdf->cbd_bufaddr;
556 while (rbdf->cbd_sc & BD_SC_EMPTY)
560 rbdf->cbd_sc |= BD_SC_EMPTY;
568 volatile cbd_t *rbdf;
569 volatile scc_uart_t *up;
570 volatile immap_t *im = (immap_t *)CFG_IMMR;
571 volatile cpm8xx_t *cpmp = &(im->im_cpm);
573 up = (scc_uart_t *)&cpmp->cp_dparam[PROFF_SCC];
575 rbdf = (cbd_t *)&cpmp->cp_dpmem[up->scc_genscc.scc_rbase];
577 return(!(rbdf->cbd_sc & BD_SC_EMPTY));
580 #endif /* CONFIG_8xx_CONS_SMC1, CONFIG_8xx_CONS_SMC2 */
584 serial_puts (const char *s)
592 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
595 kgdb_serial_init(void)
597 #if defined(CONFIG_8xx_CONS_SMC1)
598 serial_printf("[on SMC1] ");
599 #elif defined(CONFIG_8xx_CONS_SMC2)
600 serial_printf("[on SMC2] ");
601 #elif defined(CONFIG_8xx_CONS_SCC1)
602 serial_printf("[on SCC1] ");
603 #elif defined(CONFIG_8xx_CONS_SCC2)
604 serial_printf("[on SCC2] ");
605 #elif defined(CONFIG_8xx_CONS_SCC3)
606 serial_printf("[on SCC3] ");
607 #elif defined(CONFIG_8xx_CONS_SCC4)
608 serial_printf("[on SCC4] ");
619 putDebugStr (const char *str)
627 return serial_getc();
631 kgdb_interruptible (int yes)
635 #endif /* CFG_CMD_KGDB */
637 #endif /* CONFIG_8xx_CONS_NONE */