4 * Basic ET HW initialization and packet RX/TX routines
6 * NOTE <<<IMPORTANT: PLEASE READ>>>:
7 * Do not cache Rx/Tx buffers!
11 * MPC823 <-> MC68160 Connections:
13 * Setup MPC823 to work with MC68160 Enhanced Ethernet
14 * Serial Tranceiver as follows:
16 * MPC823 Signal MC68160 Comments
17 * ------ ------ ------- --------
18 * PA-12 ETHTX --------> TX Eth. Port Transmit Data
19 * PB-18 E_TENA --------> TENA Eth. Transmit Port Enable
20 * PA-5 ETHTCK <-------- TCLK Eth. Port Transmit Clock
21 * PA-13 ETHRX <-------- RX Eth. Port Receive Data
22 * PC-8 E_RENA <-------- RENA Eth. Receive Enable
23 * PA-6 ETHRCK <-------- RCLK Eth. Port Receive Clock
24 * PC-9 E_CLSN <-------- CLSN Eth. Port Collision Indication
26 * FADS Board Signal MC68160 Comments
27 * ----------------- ------- --------
28 * (BCSR1) ETHEN* --------> CS2 Eth. Port Enable
29 * (BSCR4) TPSQEL* --------> TPSQEL Twisted Pair Signal Quality Error Test Enable
30 * (BCSR4) TPFLDL* --------> TPFLDL Twisted Pair Full-Duplex
31 * (BCSR4) ETHLOOP --------> LOOP Eth. Port Diagnostic Loop-Back
41 #if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(SCC_ENET)
43 /* Ethernet Transmit and Receive Buffers */
44 #define DBUF_LENGTH 1520
50 static char txbuf[DBUF_LENGTH];
52 static uint rxIdx; /* index of the current RX buffer */
53 static uint txIdx; /* index of the current TX buffer */
56 * SCC Ethernet Tx and Rx buffer descriptors allocated at the
57 * immr->udata_bd address on Dual-Port RAM
58 * Provide for Double Buffering
61 typedef volatile struct CommonBufferDescriptor {
62 cbd_t rxbd[PKTBUFSRX]; /* Rx BD */
63 cbd_t txbd[TX_BUF_CNT]; /* Tx BD */
68 static int scc_send(struct eth_device* dev, volatile void *packet, int length);
69 static int scc_recv(struct eth_device* dev);
70 static int scc_init (struct eth_device* dev, bd_t * bd);
71 static void scc_halt(struct eth_device* dev);
73 int scc_initialize(bd_t *bis)
75 struct eth_device* dev;
77 dev = (struct eth_device*) malloc(sizeof *dev);
79 sprintf(dev->name, "SCC ETHERNET");
92 static int scc_send(struct eth_device* dev, volatile void *packet, int length)
96 volatile char *in, *out;
103 while (rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY);
104 out = (char *)(rtx->txbd[txIdx].cbd_bufaddr);
106 for(i = 0; i < length; i++) {
109 rtx->txbd[txIdx].cbd_datlen = length;
110 rtx->txbd[txIdx].cbd_sc |= (BD_ENET_TX_READY | BD_ENET_TX_LAST);
111 while (rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY) j++;
114 printf("cycles: %d status: %x\n", j, rtx->txbd[txIdx].cbd_sc);
116 i = (rtx->txbd[txIdx++].cbd_sc & BD_ENET_TX_STATS) /* return only status bits */;
118 /* wrap around buffer index when necessary */
119 if (txIdx >= TX_BUF_CNT) txIdx = 0;
122 while ((rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY) && (j<TOUT_LOOP)) {
123 udelay (1); /* will also trigger Wd if needed */
126 if (j>=TOUT_LOOP) printf("TX not ready\n");
127 rtx->txbd[txIdx].cbd_bufaddr = (uint)packet;
128 rtx->txbd[txIdx].cbd_datlen = length;
129 rtx->txbd[txIdx].cbd_sc |= (BD_ENET_TX_READY | BD_ENET_TX_LAST |BD_ENET_TX_WRAP);
130 while ((rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY) && (j<TOUT_LOOP)) {
131 udelay (1); /* will also trigger Wd if needed */
134 if (j>=TOUT_LOOP) printf("TX timeout\n");
136 printf("cycles: %d status: %x\n", j, rtx->txbd[txIdx].cbd_sc);
138 i = (rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_STATS) /* return only status bits */;
142 static int scc_recv(struct eth_device* dev)
147 /* section 16.9.23.2 */
148 if (rtx->rxbd[rxIdx].cbd_sc & BD_ENET_RX_EMPTY) {
150 break; /* nothing received - leave for() loop */
153 length = rtx->rxbd[rxIdx].cbd_datlen;
155 if (rtx->rxbd[rxIdx].cbd_sc & 0x003f) {
157 printf("err: %x\n", rtx->rxbd[rxIdx].cbd_sc);
160 /* Pass the packet up to the protocol layers. */
161 NetReceive(NetRxPackets[rxIdx], length - 4);
165 /* Give the buffer back to the SCC. */
166 rtx->rxbd[rxIdx].cbd_datlen = 0;
168 /* wrap around buffer index when necessary */
169 if ((rxIdx + 1) >= PKTBUFSRX) {
170 rtx->rxbd[PKTBUFSRX - 1].cbd_sc = (BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY);
173 rtx->rxbd[rxIdx].cbd_sc = BD_ENET_RX_EMPTY;
180 /**************************************************************
182 * SCC Ethernet Initialization Routine
184 *************************************************************/
186 static int scc_init(struct eth_device* dev, bd_t *bis)
190 scc_enet_t *pram_ptr;
192 volatile immap_t *immr = (immap_t *)CFG_IMMR;
194 #if defined(CONFIG_FADS)
195 #if defined(CONFIG_MPC860T)
196 /* The FADS860T doesn't use the MODEM_EN or DATA_VOICE signals. */
197 *((uint *) BCSR4) &= ~BCSR4_ETHLOOP;
198 *((uint *) BCSR4) |= BCSR4_TFPLDL|BCSR4_TPSQEL;
199 *((uint *) BCSR1) &= ~BCSR1_ETHEN;
201 *((uint *) BCSR4) &= ~(BCSR4_ETHLOOP|BCSR4_MODEM_EN);
202 *((uint *) BCSR4) |= BCSR4_TFPLDL|BCSR4_TPSQEL|BCSR4_DATA_VOICE;
203 *((uint *) BCSR1) &= ~BCSR1_ETHEN;
207 pram_ptr = (scc_enet_t *)&(immr->im_cpm.cp_dparam[PROFF_ENET]);
212 #ifdef CFG_ALLOC_DPRAM
213 rtx = (RTXBD *) (immr->im_cpm.cp_dpmem +
214 dpram_alloc_align(sizeof(RTXBD), 8));
216 rtx = (RTXBD *) (immr->im_cpm.cp_dpmem + CPM_SCC_BASE);
219 #if (defined(PA_ENET_RXD) && defined(PA_ENET_TXD))
220 /* Configure port A pins for Txd and Rxd.
222 immr->im_ioport.iop_papar |= (PA_ENET_RXD | PA_ENET_TXD);
223 immr->im_ioport.iop_padir &= ~(PA_ENET_RXD | PA_ENET_TXD);
224 immr->im_ioport.iop_paodr &= ~PA_ENET_TXD;
225 #elif (defined(PB_ENET_RXD) && defined(PB_ENET_TXD))
226 /* Configure port B pins for Txd and Rxd.
228 immr->im_cpm.cp_pbpar |= (PB_ENET_RXD | PB_ENET_TXD);
229 immr->im_cpm.cp_pbdir &= ~(PB_ENET_RXD | PB_ENET_TXD);
230 immr->im_cpm.cp_pbodr &= ~PB_ENET_TXD;
232 #error Configuration Error: exactly ONE of PA_ENET_[RT]XD, PB_ENET_[RT]XD must be defined
235 #if defined(PC_ENET_LBK)
236 /* Configure port C pins to disable External Loopback
238 immr->im_ioport.iop_pcpar &= ~PC_ENET_LBK;
239 immr->im_ioport.iop_pcdir |= PC_ENET_LBK;
240 immr->im_ioport.iop_pcso &= ~PC_ENET_LBK;
241 immr->im_ioport.iop_pcdat &= ~PC_ENET_LBK; /* Disable Loopback */
242 #endif /* PC_ENET_LBK */
244 /* Configure port C pins to enable CLSN and RENA.
246 immr->im_ioport.iop_pcpar &= ~(PC_ENET_CLSN | PC_ENET_RENA);
247 immr->im_ioport.iop_pcdir &= ~(PC_ENET_CLSN | PC_ENET_RENA);
248 immr->im_ioport.iop_pcso |= (PC_ENET_CLSN | PC_ENET_RENA);
250 /* Configure port A for TCLK and RCLK.
252 immr->im_ioport.iop_papar |= (PA_ENET_TCLK | PA_ENET_RCLK);
253 immr->im_ioport.iop_padir &= ~(PA_ENET_TCLK | PA_ENET_RCLK);
256 * Configure Serial Interface clock routing -- see section 16.7.5.3
257 * First, clear all SCC bits to zero, then set the ones we want.
260 immr->im_cpm.cp_sicr &= ~SICR_ENET_MASK;
261 immr->im_cpm.cp_sicr |= SICR_ENET_CLKRT;
265 * Initialize SDCR -- see section 16.9.23.7
266 * SDMA configuration register
268 immr->im_siu_conf.sc_sdcr = 0x01;
272 * Setup SCC Ethernet Parameter RAM
275 pram_ptr->sen_genscc.scc_rfcr = 0x18; /* Normal Operation and Mot byte ordering */
276 pram_ptr->sen_genscc.scc_tfcr = 0x18; /* Mot byte ordering, Normal access */
278 pram_ptr->sen_genscc.scc_mrblr = DBUF_LENGTH; /* max. ET package len 1520 */
280 pram_ptr->sen_genscc.scc_rbase = (unsigned int)(&rtx->rxbd[0]); /* Set RXBD tbl start at Dual Port */
281 pram_ptr->sen_genscc.scc_tbase = (unsigned int)(&rtx->txbd[0]); /* Set TXBD tbl start at Dual Port */
284 * Setup Receiver Buffer Descriptors (13.14.24.18)
289 for (i = 0; i < PKTBUFSRX; i++)
291 rtx->rxbd[i].cbd_sc = BD_ENET_RX_EMPTY;
292 rtx->rxbd[i].cbd_datlen = 0; /* Reset */
293 rtx->rxbd[i].cbd_bufaddr = (uint)NetRxPackets[i];
296 rtx->rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP;
299 * Setup Ethernet Transmitter Buffer Descriptors (13.14.24.19)
301 * Add PADs to Short FRAMES, Wrap, Last, Tx CRC
304 for (i = 0; i < TX_BUF_CNT; i++)
306 rtx->txbd[i].cbd_sc = (BD_ENET_TX_PAD | BD_ENET_TX_LAST | BD_ENET_TX_TC);
307 rtx->txbd[i].cbd_datlen = 0; /* Reset */
308 rtx->txbd[i].cbd_bufaddr = (uint) (&txbuf[0]);
311 rtx->txbd[TX_BUF_CNT - 1].cbd_sc |= BD_ENET_TX_WRAP;
314 * Enter Command: Initialize Rx Params for SCC
317 do { /* Spin until ready to issue command */
319 } while (immr->im_cpm.cp_cpcr & CPM_CR_FLG);
321 immr->im_cpm.cp_cpcr = ((CPM_CR_INIT_RX << 8) | (CPM_CR_ENET << 4) | CPM_CR_FLG);
322 do { /* Spin until command processed */
324 } while (immr->im_cpm.cp_cpcr & CPM_CR_FLG);
327 * Ethernet Specific Parameter RAM
328 * see table 13-16, pg. 660,
329 * pg. 681 (example with suggested settings)
332 pram_ptr->sen_cpres = ~(0x0); /* Preset CRC */
333 pram_ptr->sen_cmask = 0xdebb20e3; /* Constant Mask for CRC */
334 pram_ptr->sen_crcec = 0x0; /* Error Counter CRC (unused) */
335 pram_ptr->sen_alec = 0x0; /* Alignment Error Counter (unused) */
336 pram_ptr->sen_disfc = 0x0; /* Discard Frame Counter (unused) */
337 pram_ptr->sen_pads = 0x8888; /* Short Frame PAD Characters */
339 pram_ptr->sen_retlim = 15; /* Retry Limit Threshold */
340 pram_ptr->sen_maxflr = 1518; /* MAX Frame Length Register */
341 pram_ptr->sen_minflr = 64; /* MIN Frame Length Register */
343 pram_ptr->sen_maxd1 = DBUF_LENGTH; /* MAX DMA1 Length Register */
344 pram_ptr->sen_maxd2 = DBUF_LENGTH; /* MAX DMA2 Length Register */
346 pram_ptr->sen_gaddr1 = 0x0; /* Group Address Filter 1 (unused) */
347 pram_ptr->sen_gaddr2 = 0x0; /* Group Address Filter 2 (unused) */
348 pram_ptr->sen_gaddr3 = 0x0; /* Group Address Filter 3 (unused) */
349 pram_ptr->sen_gaddr4 = 0x0; /* Group Address Filter 4 (unused) */
351 #define ea eth_get_dev()->enetaddr
352 pram_ptr->sen_paddrh = (ea[5] << 8) + ea[4];
353 pram_ptr->sen_paddrm = (ea[3] << 8) + ea[2];
354 pram_ptr->sen_paddrl = (ea[1] << 8) + ea[0];
357 pram_ptr->sen_pper = 0x0; /* Persistence (unused) */
358 pram_ptr->sen_iaddr1 = 0x0; /* Individual Address Filter 1 (unused) */
359 pram_ptr->sen_iaddr2 = 0x0; /* Individual Address Filter 2 (unused) */
360 pram_ptr->sen_iaddr3 = 0x0; /* Individual Address Filter 3 (unused) */
361 pram_ptr->sen_iaddr4 = 0x0; /* Individual Address Filter 4 (unused) */
362 pram_ptr->sen_taddrh = 0x0; /* Tmp Address (MSB) (unused) */
363 pram_ptr->sen_taddrm = 0x0; /* Tmp Address (unused) */
364 pram_ptr->sen_taddrl = 0x0; /* Tmp Address (LSB) (unused) */
367 * Enter Command: Initialize Tx Params for SCC
370 do { /* Spin until ready to issue command */
372 } while (immr->im_cpm.cp_cpcr & CPM_CR_FLG);
374 immr->im_cpm.cp_cpcr = ((CPM_CR_INIT_TX << 8) | (CPM_CR_ENET << 4) | CPM_CR_FLG);
375 do { /* Spin until command processed */
377 } while (immr->im_cpm.cp_cpcr & CPM_CR_FLG);
380 * Mask all Events in SCCM - we use polling mode
382 immr->im_cpm.cp_scc[SCC_ENET].scc_sccm = 0;
385 * Clear Events in SCCE -- Clear bits by writing 1's
388 immr->im_cpm.cp_scc[SCC_ENET].scc_scce = ~(0x0);
392 * Initialize GSMR High 32-Bits
393 * Settings: Normal Mode
396 immr->im_cpm.cp_scc[SCC_ENET].scc_gsmrh = 0;
399 * Initialize GSMR Low 32-Bits, but do not Enable Transmit/Receive
403 * TPP = Repeating 10's
407 immr->im_cpm.cp_scc[SCC_ENET].scc_gsmrl = ( SCC_GSMRL_TCI | \
410 SCC_GSMRL_MODE_ENET);
413 * Initialize the DSR -- see section 13.14.4 (pg. 513) v0.4
416 immr->im_cpm.cp_scc[SCC_ENET].scc_dsr = 0xd555;
419 * Initialize the PSMR
422 * NIB = Begin searching for SFD 22 bits after RENA
423 * FDE = Full Duplex Enable
424 * LPB = Loopback Enable (Needed when FDE is set)
425 * BRO = Reject broadcast packets
426 * PROMISCOUS = Catch all packets regardless of dest. MAC adress
428 immr->im_cpm.cp_scc[SCC_ENET].scc_psmr = SCC_PSMR_ENCRC |
430 #if defined(CONFIG_SCC_ENET_FULL_DUPLEX)
434 #if defined(CONFIG_SCC_ENET_NO_BROADCAST)
437 #if defined(CONFIG_SCC_ENET_PROMISCOUS)
443 * Configure Ethernet TENA Signal
446 #if (defined(PC_ENET_TENA) && !defined(PB_ENET_TENA))
447 immr->im_ioport.iop_pcpar |= PC_ENET_TENA;
448 immr->im_ioport.iop_pcdir &= ~PC_ENET_TENA;
449 #elif (defined(PB_ENET_TENA) && !defined(PC_ENET_TENA))
450 immr->im_cpm.cp_pbpar |= PB_ENET_TENA;
451 immr->im_cpm.cp_pbdir |= PB_ENET_TENA;
453 #error Configuration Error: exactly ONE of PB_ENET_TENA, PC_ENET_TENA must be defined
456 #if defined(CONFIG_ADS) && defined(CONFIG_MPC860)
458 * Port C is used to control the PHY,MC68160.
460 immr->im_ioport.iop_pcdir |=
461 (PC_ENET_ETHLOOP | PC_ENET_TPFLDL | PC_ENET_TPSQEL);
463 immr->im_ioport.iop_pcdat |= PC_ENET_TPFLDL;
464 immr->im_ioport.iop_pcdat &= ~(PC_ENET_ETHLOOP | PC_ENET_TPSQEL);
465 *((uint *) BCSR1) &= ~BCSR1_ETHEN;
466 #endif /* MPC860ADS */
468 #if defined(CONFIG_AMX860)
470 * Port B is used to control the PHY,MC68160.
472 immr->im_cpm.cp_pbdir |=
473 (PB_ENET_ETHLOOP | PB_ENET_TPFLDL | PB_ENET_TPSQEL);
475 immr->im_cpm.cp_pbdat |= PB_ENET_TPFLDL;
476 immr->im_cpm.cp_pbdat &= ~(PB_ENET_ETHLOOP | PB_ENET_TPSQEL);
478 immr->im_ioport.iop_pddir |= PD_ENET_ETH_EN;
479 immr->im_ioport.iop_pddat &= ~PD_ENET_ETH_EN;
482 #ifdef CONFIG_RPXCLASSIC
483 *((uchar *)BCSR0) &= ~BCSR0_ETHLPBK;
484 *((uchar *)BCSR0) |= (BCSR0_ETHEN | BCSR0_COLTEST | BCSR0_FULLDPLX);
487 #ifdef CONFIG_RPXLITE
488 *((uchar *)BCSR0) |= BCSR0_ETHEN ;
495 #if defined(CONFIG_NETVIA)
496 #if defined(PB_ENET_PDN)
497 immr->im_cpm.cp_pbpar &= ~PB_ENET_PDN;
498 immr->im_cpm.cp_pbdir |= PB_ENET_PDN;
499 immr->im_cpm.cp_pbdat |= PB_ENET_PDN;
500 #elif defined(PC_ENET_PDN)
501 immr->im_cpm.cp_pcpar &= ~PC_ENET_PDN;
502 immr->im_cpm.cp_pcdir |= PC_ENET_PDN;
503 immr->im_cpm.cp_pcdat |= PC_ENET_PDN;
508 * Set the ENT/ENR bits in the GSMR Low -- Enable Transmit/Receive
511 immr->im_cpm.cp_scc[SCC_ENET].scc_gsmrl |= (SCC_GSMRL_ENR | SCC_GSMRL_ENT);
514 * Work around transmit problem with first eth packet
516 #if defined (CONFIG_FADS)
517 udelay(10000); /* wait 10 ms */
518 #elif defined (CONFIG_AMX860) || defined(CONFIG_RPXCLASSIC)
519 udelay(100000); /* wait 100 ms */
527 static void scc_halt(struct eth_device* dev)
529 volatile immap_t *immr = (immap_t *)CFG_IMMR;
530 immr->im_cpm.cp_scc[SCC_ENET].scc_gsmrl &= ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
536 volatile immap_t *immr = (immap_t *)CFG_IMMR;
537 immr->im_cpm.cp_scc[SCC_ENET].scc_gsmrl |= (SCC_GSMRL_ENR | SCC_GSMRL_ENT);
541 #endif /* CFG_CMD_NET, SCC_ENET */