2 * (C) Copyright 2001-2002
3 * Wolfgang Denk, DENX Software Engineering -- wd@denx.de
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 /************************************************************************/
26 /************************************************************************/
37 #include <linux/types.h>
39 #if defined(CONFIG_POST)
46 /************************************************************************/
47 /* ** CONFIG STUFF -- should be moved to board config file */
48 /************************************************************************/
49 #define CONFIG_LCD_LOGO
50 #define LCD_INFO /* Display Logo, (C) and system info */
52 #if defined(CONFIG_V37) || defined(CONFIG_EDT32F10)
53 #undef CONFIG_LCD_LOGO
57 /*----------------------------------------------------------------------*/
58 #ifdef CONFIG_KYOCERA_KCS057QV1AJ
60 * Kyocera KCS057QV1AJ-G23. Passive, color, single scan.
62 #define LCD_BPP LCD_COLOR4
64 vidinfo_t panel_info = {
65 640, 480, 132, 99, CFG_HIGH, CFG_HIGH, CFG_HIGH, CFG_HIGH, CFG_HIGH,
66 LCD_BPP, 1, 0, 1, 0, 5, 0, 0, 0
67 /* wbl, vpw, lcdac, wbf */
69 #endif /* CONFIG_KYOCERA_KCS057QV1AJ */
70 /*----------------------------------------------------------------------*/
72 /*----------------------------------------------------------------------*/
73 #ifdef CONFIG_HITACHI_SP19X001_Z1A
75 * Hitachi SP19X001-. Active, color, single scan.
77 vidinfo_t panel_info = {
78 640, 480, 154, 116, CFG_HIGH, CFG_HIGH, CFG_HIGH, CFG_HIGH, CFG_HIGH,
79 LCD_COLOR8, 1, 0, 1, 0, 0, 0, 0, 0
80 /* wbl, vpw, lcdac, wbf */
82 #endif /* CONFIG_HITACHI_SP19X001_Z1A */
83 /*----------------------------------------------------------------------*/
85 /*----------------------------------------------------------------------*/
86 #ifdef CONFIG_NEC_NL6448AC33
88 * NEC NL6448AC33-18. Active, color, single scan.
90 vidinfo_t panel_info = {
91 640, 480, 132, 99, CFG_HIGH, CFG_HIGH, CFG_LOW, CFG_LOW, CFG_HIGH,
92 3, 0, 0, 1, 1, 144, 2, 0, 33
93 /* wbl, vpw, lcdac, wbf */
95 #endif /* CONFIG_NEC_NL6448AC33 */
96 /*----------------------------------------------------------------------*/
98 #ifdef CONFIG_NEC_NL6448BC20
100 * NEC NL6448BC20-08. 6.5", 640x480. Active, color, single scan.
102 vidinfo_t panel_info = {
103 640, 480, 132, 99, CFG_HIGH, CFG_HIGH, CFG_LOW, CFG_LOW, CFG_HIGH,
104 3, 0, 0, 1, 1, 144, 2, 0, 33
105 /* wbl, vpw, lcdac, wbf */
107 #endif /* CONFIG_NEC_NL6448BC20 */
108 /*----------------------------------------------------------------------*/
110 #ifdef CONFIG_NEC_NL6448BC33_54
112 * NEC NL6448BC33-54. 10.4", 640x480. Active, color, single scan.
114 vidinfo_t panel_info = {
115 640, 480, 212, 158, CFG_HIGH, CFG_HIGH, CFG_LOW, CFG_LOW, CFG_HIGH,
116 3, 0, 0, 1, 1, 144, 2, 0, 33
117 /* wbl, vpw, lcdac, wbf */
119 #endif /* CONFIG_NEC_NL6448BC33_54 */
120 /*----------------------------------------------------------------------*/
122 #ifdef CONFIG_SHARP_LQ104V7DS01
124 * SHARP LQ104V7DS01. 6.5", 640x480. Active, color, single scan.
126 vidinfo_t panel_info = {
127 640, 480, 132, 99, CFG_HIGH, CFG_HIGH, CFG_LOW, CFG_LOW, CFG_LOW,
128 3, 0, 0, 1, 1, 25, 1, 0, 33
129 /* wbl, vpw, lcdac, wbf */
131 #endif /* CONFIG_SHARP_LQ104V7DS01 */
132 /*----------------------------------------------------------------------*/
134 #ifdef CONFIG_SHARP_16x9
136 * Sharp 320x240. Active, color, single scan. It isn't 16x9, and I am
137 * not sure what it is.......
139 vidinfo_t panel_info = {
140 320, 240, 0, 0, CFG_HIGH, CFG_HIGH, CFG_HIGH, CFG_HIGH, CFG_HIGH,
141 3, 0, 0, 1, 1, 15, 4, 0, 3
143 #endif /* CONFIG_SHARP_16x9 */
144 /*----------------------------------------------------------------------*/
146 #ifdef CONFIG_SHARP_LQ057Q3DC02
148 * Sharp LQ057Q3DC02 display. Active, color, single scan.
153 vidinfo_t panel_info = {
154 320, 240, 0, 0, CFG_HIGH, CFG_HIGH, CFG_LOW, CFG_LOW, CFG_HIGH,
155 3, 0, 0, 1, 1, 15, 4, 0, 3
156 /* wbl, vpw, lcdac, wbf */
158 #define LCD_INFO_BELOW_LOGO
159 #endif /* CONFIG_SHARP_LQ057Q3DC02 */
160 /*----------------------------------------------------------------------*/
162 #ifdef CONFIG_SHARP_LQ64D341
164 * Sharp LQ64D341 display, 640x480. Active, color, single scan.
166 vidinfo_t panel_info = {
167 640, 480, 0, 0, CFG_HIGH, CFG_HIGH, CFG_LOW, CFG_LOW, CFG_HIGH,
168 3, 0, 0, 1, 1, 128, 16, 0, 32
169 /* wbl, vpw, lcdac, wbf */
171 #endif /* CONFIG_SHARP_LQ64D341 */
173 #ifdef CONFIG_SHARP_LQ065T9DR51U
175 * Sharp LQ065T9DR51U display, 400x240. Active, color, single scan.
177 vidinfo_t panel_info = {
178 400, 240, 143, 79, CFG_HIGH, CFG_HIGH, CFG_HIGH, CFG_HIGH, CFG_HIGH,
179 3, 0, 0, 1, 1, 248, 4, 0, 35
180 /* wbl, vpw, lcdac, wbf */
182 #define LCD_INFO_BELOW_LOGO
183 #endif /* CONFIG_SHARP_LQ065T9DR51U */
185 #ifdef CONFIG_SHARP_LQ084V1DG21
187 * Sharp LQ084V1DG21 display, 640x480. Active, color, single scan.
189 vidinfo_t panel_info = {
190 640, 480, 171, 129, CFG_HIGH, CFG_HIGH, CFG_LOW, CFG_LOW, CFG_LOW,
191 3, 0, 0, 1, 1, 160, 3, 0, 48
192 /* wbl, vpw, lcdac, wbf */
194 #endif /* CONFIG_SHARP_LQ084V1DG21 */
196 /*----------------------------------------------------------------------*/
198 #ifdef CONFIG_HLD1045
200 * HLD1045 display, 640x480. Active, color, single scan.
202 vidinfo_t panel_info = {
203 640, 480, 0, 0, CFG_HIGH, CFG_HIGH, CFG_LOW, CFG_LOW, CFG_HIGH,
204 3, 0, 0, 1, 1, 160, 3, 0, 48
205 /* wbl, vpw, lcdac, wbf */
207 #endif /* CONFIG_HLD1045 */
208 /*----------------------------------------------------------------------*/
210 #ifdef CONFIG_PRIMEVIEW_V16C6448AC
212 * Prime View V16C6448AC
214 vidinfo_t panel_info = {
215 640, 480, 130, 98, CFG_HIGH, CFG_HIGH, CFG_LOW, CFG_LOW, CFG_HIGH,
216 3, 0, 0, 1, 1, 144, 2, 0, 35
217 /* wbl, vpw, lcdac, wbf */
219 #endif /* CONFIG_PRIMEVIEW_V16C6448AC */
221 /*----------------------------------------------------------------------*/
223 #ifdef CONFIG_OPTREX_BW
225 * Optrex CBL50840-2 NF-FW 99 22 M5
227 * Hitachi LMG6912RPFC-00T
231 * 320x240. Black & white.
233 #define OPTREX_BPP 0 /* 0 - monochrome, 1 bpp */
234 /* 1 - 4 grey levels, 2 bpp */
235 /* 2 - 16 grey levels, 4 bpp */
236 vidinfo_t panel_info = {
237 320, 240, 0, 0, CFG_HIGH, CFG_HIGH, CFG_HIGH, CFG_HIGH, CFG_LOW,
238 OPTREX_BPP, 0, 0, 0, 0, 0, 0, 0, 0, 4
240 #endif /* CONFIG_OPTREX_BW */
242 /*-----------------------------------------------------------------*/
243 #ifdef CONFIG_EDT32F10
245 * Emerging Display Technologies 320x240. Passive, monochrome, single scan.
247 #define LCD_BPP LCD_MONOCHROME
250 vidinfo_t panel_info = {
251 320, 240, 0, 0, CFG_HIGH, CFG_HIGH, CFG_HIGH, CFG_HIGH, CFG_LOW,
252 LCD_BPP, 0, 0, 0, 0, 33, 0, 0, 0
255 /*----------------------------------------------------------------------*/
264 * Frame buffer memory information
266 void *lcd_base; /* Start of framebuffer memory */
267 void *lcd_console_address; /* Start of console buffer */
272 /************************************************************************/
274 void lcd_ctrl_init (void *lcdbase);
275 void lcd_enable (void);
276 #if LCD_BPP == LCD_COLOR8
277 void lcd_setcolreg (ushort regno,
278 ushort red, ushort green, ushort blue);
280 #if LCD_BPP == LCD_MONOCHROME
281 void lcd_initcolregs (void);
284 #if defined(CONFIG_RBC823)
285 void lcd_disable (void);
288 /************************************************************************/
290 /************************************************************************/
291 /* ----------------- chipset specific functions ----------------------- */
292 /************************************************************************/
295 * Calculate fb size for VIDEOLFB_ATAG.
297 ulong calc_fbsize (void)
300 int line_length = (panel_info.vl_col * NBITS (panel_info.vl_bpix)) / 8;
302 size = line_length * panel_info.vl_row;
307 void lcd_ctrl_init (void *lcdbase)
309 volatile immap_t *immr = (immap_t *) CFG_IMMR;
310 volatile lcd823_t *lcdp = &immr->im_lcd;
315 /* Initialize the LCD control register according to the LCD
316 * parameters defined. We do everything here but enable
320 #ifdef CONFIG_RPXLITE
321 /* This is special for RPXlite_DW Software Development Platform **[Sam]** */
322 panel_info.vl_dp = CFG_LOW;
325 lccrtmp = LCDBIT (LCCR_BNUM_BIT,
326 (((panel_info.vl_row * panel_info.vl_col) * (1 << LCD_BPP)) / 128));
328 lccrtmp |= LCDBIT (LCCR_CLKP_BIT, panel_info.vl_clkp) |
329 LCDBIT (LCCR_OEP_BIT, panel_info.vl_oep) |
330 LCDBIT (LCCR_HSP_BIT, panel_info.vl_hsp) |
331 LCDBIT (LCCR_VSP_BIT, panel_info.vl_vsp) |
332 LCDBIT (LCCR_DP_BIT, panel_info.vl_dp) |
333 LCDBIT (LCCR_BPIX_BIT, panel_info.vl_bpix) |
334 LCDBIT (LCCR_LBW_BIT, panel_info.vl_lbw) |
335 LCDBIT (LCCR_SPLT_BIT, panel_info.vl_splt) |
336 LCDBIT (LCCR_CLOR_BIT, panel_info.vl_clor) |
337 LCDBIT (LCCR_TFT_BIT, panel_info.vl_tft);
340 lccrtmp |= ((SIU_LEVEL5 / 2) << 12);
341 lccrtmp |= LCCR_EIEN;
344 lcdp->lcd_lccr = lccrtmp;
345 lcdp->lcd_lcsr = 0xFF; /* Clear pending interrupts */
347 /* Initialize LCD controller bus priorities.
350 immr->im_siu_conf.sc_sdcr = (immr->im_siu_conf.sc_sdcr & ~0x0f) | 1; /* RAID = 01, LAID = 00 */
352 immr->im_siu_conf.sc_sdcr &= ~0x0f; /* RAID = LAID = 0 */
354 /* set SHFT/CLOCK division factor 4
355 * This needs to be set based upon display type and processor
356 * speed. The TFT displays run about 20 to 30 MHz.
357 * I was running 64 MHz processor speed.
358 * The value for this divider must be chosen so the result is
359 * an integer of the processor speed (i.e., divide by 3 with
360 * 64 MHz would be bad).
362 immr->im_clkrst.car_sccr &= ~0x1F;
363 immr->im_clkrst.car_sccr |= LCD_DF; /* was 8 */
365 #endif /* CONFIG_RBC823 */
367 #if defined(CONFIG_RBC823)
368 /* Enable LCD on port D.
370 immr->im_ioport.iop_pddat &= 0x0300;
371 immr->im_ioport.iop_pdpar |= 0x1CFF;
372 immr->im_ioport.iop_pddir |= 0x1CFF;
374 /* Configure LCD_ON, VEE_ON, CCFL_ON on port B.
376 immr->im_cpm.cp_pbdat &= ~0x00005001;
377 immr->im_cpm.cp_pbpar &= ~0x00005001;
378 immr->im_cpm.cp_pbdir |= 0x00005001;
379 #elif !defined(CONFIG_EDT32F10)
380 /* Enable LCD on port D.
382 immr->im_ioport.iop_pdpar |= 0x1FFF;
383 immr->im_ioport.iop_pddir |= 0x1FFF;
385 /* Enable LCD_A/B/C on port B.
387 immr->im_cpm.cp_pbpar |= 0x00005001;
388 immr->im_cpm.cp_pbdir |= 0x00005001;
390 /* Enable LCD on port D.
392 immr->im_ioport.iop_pdpar |= 0x1DFF;
393 immr->im_ioport.iop_pdpar &= ~0x0200;
394 immr->im_ioport.iop_pddir |= 0x1FFF;
395 immr->im_ioport.iop_pddat |= 0x0200;
398 /* Load the physical address of the linear frame buffer
399 * into the LCD controller.
400 * BIG NOTE: This has to be modified to load A and B depending
401 * upon the split mode of the LCD.
403 lcdp->lcd_lcfaa = (ulong)lcd_base;
404 lcdp->lcd_lcfba = (ulong)lcd_base;
406 /* MORE HACKS...This must be updated according to 823 manual
407 * for different panels.
408 * Udi Finkelstein - done - see below:
409 * Note: You better not try unsupported combinations such as
410 * 4-bit wide passive dual scan LCD at 4/8 Bit color.
414 (panel_info.vl_tft ? 8 :
415 (((2 - panel_info.vl_lbw) << /* 4 bit=2, 8-bit = 1 */
416 /* use << to mult by: single scan = 1, dual scan = 2 */
417 panel_info.vl_splt) *
418 (panel_info.vl_bpix | 1)))) >> 3; /* 2/4 BPP = 1, 8/16 BPP = 3 */
420 lcdp->lcd_lchcr = LCHCR_BO |
421 LCDBIT (LCHCR_AT_BIT, 4) |
422 LCDBIT (LCHCR_HPC_BIT, lchcr_hpc_tmp) |
425 lcdp->lcd_lcvcr = LCDBIT (LCVCR_VPW_BIT, panel_info.vl_vpw) |
426 LCDBIT (LCVCR_LCD_AC_BIT, panel_info.vl_lcdac) |
427 LCDBIT (LCVCR_VPC_BIT, panel_info.vl_row) |
432 /*----------------------------------------------------------------------*/
434 #ifdef NOT_USED_SO_FAR
436 lcd_getcolreg (ushort regno, ushort *red, ushort *green, ushort *blue)
438 volatile immap_t *immr = (immap_t *) CFG_IMMR;
439 volatile cpm8xx_t *cp = &(immr->im_cpm);
440 unsigned short colreg, *cmap_ptr;
442 cmap_ptr = (unsigned short *)&cp->lcd_cmap[regno * 2];
445 #ifdef CFG_INVERT_COLORS
449 *red = (colreg >> 8) & 0x0F;
450 *green = (colreg >> 4) & 0x0F;
451 *blue = colreg & 0x0F;
453 #endif /* NOT_USED_SO_FAR */
455 /*----------------------------------------------------------------------*/
457 #if LCD_BPP == LCD_COLOR8
459 lcd_setcolreg (ushort regno, ushort red, ushort green, ushort blue)
461 volatile immap_t *immr = (immap_t *) CFG_IMMR;
462 volatile cpm8xx_t *cp = &(immr->im_cpm);
463 unsigned short colreg, *cmap_ptr;
465 cmap_ptr = (unsigned short *)&cp->lcd_cmap[regno * 2];
467 colreg = ((red & 0x0F) << 8) |
468 ((green & 0x0F) << 4) |
470 #ifdef CFG_INVERT_COLORS
475 debug ("setcolreg: reg %2d @ %p: R=%02X G=%02X B=%02X => %02X%02X\n",
476 regno, &(cp->lcd_cmap[regno * 2]),
478 cp->lcd_cmap[ regno * 2 ], cp->lcd_cmap[(regno * 2) + 1]);
480 #endif /* LCD_COLOR8 */
482 /*----------------------------------------------------------------------*/
484 #if LCD_BPP == LCD_MONOCHROME
486 void lcd_initcolregs (void)
488 volatile immap_t *immr = (immap_t *) CFG_IMMR;
489 volatile cpm8xx_t *cp = &(immr->im_cpm);
492 for (regno = 0; regno < 16; regno++) {
493 cp->lcd_cmap[regno * 2] = 0;
494 cp->lcd_cmap[(regno * 2) + 1] = regno & 0x0f;
499 /*----------------------------------------------------------------------*/
501 void lcd_enable (void)
503 volatile immap_t *immr = (immap_t *) CFG_IMMR;
504 volatile lcd823_t *lcdp = &immr->im_lcd;
506 /* Enable the LCD panel */
507 #ifndef CONFIG_RBC823
508 immr->im_siu_conf.sc_sdcr |= (1 << (31 - 25)); /* LAM = 1 */
510 lcdp->lcd_lccr |= LCCR_PON;
513 /* Turn on display backlight */
514 immr->im_cpm.cp_pbpar |= 0x00008000;
515 immr->im_cpm.cp_pbdir |= 0x00008000;
516 #elif defined(CONFIG_RBC823)
517 /* Turn on display backlight */
518 immr->im_cpm.cp_pbdat |= 0x00004000;
521 #if defined(CONFIG_LWMON)
522 { uchar c = pic_read (0x60);
523 #if defined(CONFIG_LCD) && defined(CONFIG_LWMON) && (CONFIG_POST & CFG_POST_SYSMON)
524 /* Enable LCD later in sysmon test, only if temperature is OK */
526 c |= 0x07; /* Power on CCFL, Enable CCFL, Chip Enable LCD */
530 #endif /* CONFIG_LWMON */
532 #if defined(CONFIG_R360MPI)
534 extern void r360_i2c_lcd_write (uchar data0, uchar data1);
535 unsigned long bgi, ctr;
538 if ((p = getenv("lcdbgi")) != NULL) {
539 bgi = simple_strtoul (p, 0, 10) & 0xFFF;
544 if ((p = getenv("lcdctr")) != NULL) {
545 ctr = simple_strtoul (p, 0, 10) & 0xFFF;
550 r360_i2c_lcd_write(0x10, 0x01);
551 r360_i2c_lcd_write(0x20, 0x01);
552 r360_i2c_lcd_write(0x30 | ((bgi>>8) & 0xF), bgi & 0xFF);
553 r360_i2c_lcd_write(0x40 | ((ctr>>8) & 0xF), ctr & 0xFF);
555 #endif /* CONFIG_R360MPI */
557 udelay(200000); /* wait 200ms */
558 /* Turn VEE_ON first */
559 immr->im_cpm.cp_pbdat |= 0x00000001;
560 udelay(200000); /* wait 200ms */
561 /* Now turn on LCD_ON */
562 immr->im_cpm.cp_pbdat |= 0x00001000;
564 #ifdef CONFIG_RRVISION
565 debug ("PC4->Output(1): enable LVDS\n");
566 debug ("PC5->Output(0): disable PAL clock\n");
567 immr->im_ioport.iop_pddir |= 0x1000;
568 immr->im_ioport.iop_pcpar &= ~(0x0C00);
569 immr->im_ioport.iop_pcdir |= 0x0C00 ;
570 immr->im_ioport.iop_pcdat |= 0x0800 ;
571 immr->im_ioport.iop_pcdat &= ~(0x0400);
572 debug ("PDPAR=0x%04X PDDIR=0x%04X PDDAT=0x%04X\n",
573 immr->im_ioport.iop_pdpar,
574 immr->im_ioport.iop_pddir,
575 immr->im_ioport.iop_pddat);
576 debug ("PCPAR=0x%04X PCDIR=0x%04X PCDAT=0x%04X\n",
577 immr->im_ioport.iop_pcpar,
578 immr->im_ioport.iop_pcdir,
579 immr->im_ioport.iop_pcdat);
583 /*----------------------------------------------------------------------*/
585 #if defined (CONFIG_RBC823)
586 void lcd_disable (void)
588 volatile immap_t *immr = (immap_t *) CFG_IMMR;
589 volatile lcd823_t *lcdp = &immr->im_lcd;
591 #if defined(CONFIG_LWMON)
592 { uchar c = pic_read (0x60);
593 c &= ~0x07; /* Power off CCFL, Disable CCFL, Chip Disable LCD */
596 #elif defined(CONFIG_R360MPI)
598 extern void r360_i2c_lcd_write (uchar data0, uchar data1);
600 r360_i2c_lcd_write(0x10, 0x00);
601 r360_i2c_lcd_write(0x20, 0x00);
602 r360_i2c_lcd_write(0x30, 0x00);
603 r360_i2c_lcd_write(0x40, 0x00);
605 #endif /* CONFIG_LWMON */
606 /* Disable the LCD panel */
607 lcdp->lcd_lccr &= ~LCCR_PON;
609 /* Turn off display backlight, VEE and LCD_ON */
610 immr->im_cpm.cp_pbdat &= ~0x00005001;
612 immr->im_siu_conf.sc_sdcr &= ~(1 << (31 - 25)); /* LAM = 0 */
613 #endif /* CONFIG_RBC823 */
615 #endif /* NOT_USED_SO_FAR || CONFIG_RBC823 */
618 /************************************************************************/
620 #endif /* CONFIG_LCD */