3 * Paolo Scaffardi, AIRVENT SAM s.p.a - RIMINI(ITALY), arsenio@tin.it
5 * (C) Copyright 2000 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
6 * Marius Groeger <mgroeger@sysgo.de>
8 * See file CREDITS for list of people who contributed to this
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 * Back ported to the 8xx platform (from the 8260 platform) by
27 * Murray.Jensen@cmst.csiro.au, 27-Jan-01.
32 #ifdef CONFIG_HARD_I2C
40 /* define to enable debug messages */
43 /*-----------------------------------------------------------------------
47 #define CFG_I2C_SPEED 50000
51 #define CFG_I2C_SLAVE 0xFE
53 /*-----------------------------------------------------------------------
56 /* tx/rx timeout (we need the i2c early, so we don't use get_timer()) */
57 #define TOUT_LOOP 1000000
61 #define MAX_TX_SPACE 256
62 #define I2C_RXTX_LEN 128 /* maximum tx/rx buffer length */
66 unsigned short status;
67 unsigned short length;
70 #define BD_I2C_TX_START 0x0400 /* special status for i2c: Start condition */
72 #define BD_I2C_TX_CL 0x0001 /* collision error */
73 #define BD_I2C_TX_UN 0x0002 /* underflow error */
74 #define BD_I2C_TX_NAK 0x0004 /* no acknowledge error */
75 #define BD_I2C_TX_ERR (BD_I2C_TX_NAK|BD_I2C_TX_UN|BD_I2C_TX_CL)
77 #define BD_I2C_RX_ERR BD_SC_OV
79 typedef void (*i2c_ecb_t)(int, int); /* error callback function */
81 /* This structure keeps track of the bd and buffer space usage. */
82 typedef struct i2c_state {
83 int rx_idx; /* index to next free Rx BD */
84 int tx_idx; /* index to next free Tx BD */
85 void *rxbd; /* pointer to next free Rx BD */
86 void *txbd; /* pointer to next free Tx BD */
87 int tx_space; /* number of Tx bytes left */
88 unsigned char *tx_buf; /* pointer to free Tx area */
89 i2c_ecb_t err_cb; /* error callback function */
93 /* flags for i2c_send() and i2c_receive() */
94 #define I2CF_ENABLE_SECONDARY 0x01 /* secondary_address is valid */
95 #define I2CF_START_COND 0x02 /* tx: generate start condition */
96 #define I2CF_STOP_COND 0x04 /* tx: generate stop condition */
99 #define I2CERR_NO_BUFFERS 0x01 /* no more BDs or buffer space */
100 #define I2CERR_MSG_TOO_LONG 0x02 /* tried to send/receive to much data */
101 #define I2CERR_TIMEOUT 0x03 /* timeout in i2c_doio() */
102 #define I2CERR_QUEUE_EMPTY 0x04 /* i2c_doio called without send/receive */
104 /* error callback flags */
105 #define I2CECB_RX_ERR 0x10 /* this is a receive error */
106 #define I2CECB_RX_ERR_OV 0x02 /* receive overrun error */
107 #define I2CECB_RX_MASK 0x0f /* mask for error bits */
108 #define I2CECB_TX_ERR 0x20 /* this is a transmit error */
109 #define I2CECB_TX_CL 0x01 /* transmit collision error */
110 #define I2CECB_TX_UN 0x02 /* transmit underflow error */
111 #define I2CECB_TX_NAK 0x04 /* transmit no ack error */
112 #define I2CECB_TX_MASK 0x0f /* mask for error bits */
113 #define I2CECB_TIMEOUT 0x40 /* this is a timeout error */
116 #define PRINTD(x) printf x
122 * Returns the best value of I2BRG to meet desired clock speed of I2C with
123 * input parameters (clock speed, filter, and predivider value).
124 * It returns computer speed value and the difference between it and desired
128 i2c_roundrate(int hz, int speed, int filter, int modval,
129 int *brgval, int *totspeed)
131 int moddiv = 1 << (5-(modval & 3)), brgdiv, div;
133 PRINTD(("\t[I2C] trying hz=%d, speed=%d, filter=%d, modval=%d\n",
134 hz, speed, filter, modval));
136 div = moddiv * speed;
137 brgdiv = (hz + div - 1) / div;
139 PRINTD(("\t\tmoddiv=%d, brgdiv=%d\n", moddiv, brgdiv));
141 *brgval = ((brgdiv + 1) / 2) - 3 - (2*filter);
143 if ((*brgval < 0) || (*brgval > 255)) {
144 PRINTD(("\t\trejected brgval=%d\n", *brgval));
148 brgdiv = 2 * (*brgval + 3 + (2 * filter));
149 div = moddiv * brgdiv ;
150 *totspeed = hz / div;
152 PRINTD(("\t\taccepted brgval=%d, totspeed=%d\n", *brgval, *totspeed));
158 * Sets the I2C clock predivider and divider to meet required clock speed.
161 i2c_setrate (int hz, int speed)
163 immap_t *immap = (immap_t *) CFG_IMMR;
164 volatile i2c8xx_t *i2c = (i2c8xx_t *) & immap->im_i2c;
167 bestspeed_diff = speed,
168 bestspeed_brgval = 0,
169 bestspeed_modval = 0,
170 bestspeed_filter = 0,
172 filter = 0; /* Use this fixed value */
174 for (modval = 0; modval < 4; modval++) {
175 if (i2c_roundrate(hz,speed,filter,modval,&brgval,&totspeed) == 0) {
176 int diff = speed - totspeed;
178 if ((diff >= 0) && (diff < bestspeed_diff)) {
179 bestspeed_diff = diff;
180 bestspeed_modval = modval;
181 bestspeed_brgval = brgval;
182 bestspeed_filter = filter;
187 PRINTD (("[I2C] Best is:\n"));
188 PRINTD (("[I2C] CPU=%dhz RATE=%d F=%d I2MOD=%08x I2BRG=%08x DIFF=%dhz\n",
196 i2c->i2c_i2mod |= ((bestspeed_modval & 3) << 1) | (bestspeed_filter << 3);
197 i2c->i2c_i2brg = bestspeed_brgval & 0xff;
199 PRINTD (("[I2C] i2mod=%08x i2brg=%08x\n", i2c->i2c_i2mod,
206 i2c_init(int speed, int slaveaddr)
208 DECLARE_GLOBAL_DATA_PTR;
210 volatile immap_t *immap = (immap_t *)CFG_IMMR ;
211 volatile cpm8xx_t *cp = (cpm8xx_t *)&immap->im_cpm;
212 volatile i2c8xx_t *i2c = (i2c8xx_t *)&immap->im_i2c;
213 volatile iic_t *iip = (iic_t *)&cp->cp_dparam[PROFF_IIC];
215 volatile I2C_BD *rxbd, *txbd;
218 #ifdef CFG_I2C_UCODE_PATCH
219 iip = (iic_t *)&cp->cp_dpmem[iip->iic_rpbase];
221 /* Disable relocation */
225 #ifdef CFG_ALLOC_DPRAM
226 dpaddr = iip->iic_rbase;
228 /* need to allocate dual port ram */
229 dpaddr = dpram_alloc_align(
230 (NUM_RX_BDS * sizeof(I2C_BD)) + (NUM_TX_BDS * sizeof(I2C_BD)) +
234 dpaddr = CPM_I2C_BASE;
238 * initialise data in dual port ram:
240 * dpaddr->rbase -> rx BD (NUM_RX_BDS * sizeof(I2C_BD) bytes)
241 * tbase -> tx BD (NUM_TX_BDS * sizeof(I2C_BD) bytes)
242 * tx buffer (MAX_TX_SPACE bytes)
246 tbase = rbase + NUM_RX_BDS * sizeof(I2C_BD);
248 /* Initialize Port B I2C pins. */
249 cp->cp_pbpar |= 0x00000030;
250 cp->cp_pbdir |= 0x00000030;
251 cp->cp_pbodr |= 0x00000030;
253 /* Disable interrupts */
254 i2c->i2c_i2mod = 0x00;
255 i2c->i2c_i2cmr = 0x00;
256 i2c->i2c_i2cer = 0xff;
257 i2c->i2c_i2add = slaveaddr;
260 * Set the I2C BRG Clock division factor from desired i2c rate
261 * and current CPU rate (we assume sccr dfbgr field is 0;
262 * divide BRGCLK by 1)
264 PRINTD(("[I2C] Setting rate...\n"));
265 i2c_setrate (gd->cpu_clk, CFG_I2C_SPEED) ;
267 /* Set I2C controller in master mode */
268 i2c->i2c_i2com = 0x01;
270 /* Set SDMA bus arbitration level to 5 (SDCR) */
271 immap->im_siu_conf.sc_sdcr = 0x0001 ;
273 /* Initialize Tx/Rx parameters */
274 iip->iic_rbase = rbase;
275 iip->iic_tbase = tbase;
276 rxbd = (I2C_BD *)((unsigned char *)&cp->cp_dpmem[iip->iic_rbase]);
277 txbd = (I2C_BD *)((unsigned char *)&cp->cp_dpmem[iip->iic_tbase]);
279 PRINTD(("[I2C] rbase = %04x\n", iip->iic_rbase));
280 PRINTD(("[I2C] tbase = %04x\n", iip->iic_tbase));
281 PRINTD(("[I2C] rxbd = %08x\n", (int)rxbd));
282 PRINTD(("[I2C] txbd = %08x\n", (int)txbd));
284 /* Set big endian byte order */
285 iip->iic_tfcr = 0x10;
286 iip->iic_rfcr = 0x10;
288 /* Set maximum receive size. */
289 iip->iic_mrblr = I2C_RXTX_LEN;
291 #ifdef CFG_I2C_UCODE_PATCH
293 * Initialize required parameters if using microcode patch.
295 iip->iic_rbptr = iip->iic_rbase;
296 iip->iic_tbptr = iip->iic_tbase;
300 cp->cp_cpcr = mk_cr_cmd(CPM_CR_CH_I2C, CPM_CR_INIT_TRX) | CPM_CR_FLG;
302 __asm__ __volatile__ ("eieio");
303 } while (cp->cp_cpcr & CPM_CR_FLG);
306 /* Clear events and interrupts */
307 i2c->i2c_i2cer = 0xff;
308 i2c->i2c_i2cmr = 0x00;
312 i2c_newio(i2c_state_t *state)
314 volatile immap_t *immap = (immap_t *)CFG_IMMR ;
315 volatile cpm8xx_t *cp = (cpm8xx_t *)&immap->im_cpm;
316 volatile iic_t *iip = (iic_t *)&cp->cp_dparam[PROFF_IIC];
318 PRINTD(("[I2C] i2c_newio\n"));
320 #ifdef CFG_I2C_UCODE_PATCH
321 iip = (iic_t *)&cp->cp_dpmem[iip->iic_rpbase];
325 state->rxbd = (void*)&cp->cp_dpmem[iip->iic_rbase];
326 state->txbd = (void*)&cp->cp_dpmem[iip->iic_tbase];
327 state->tx_space = MAX_TX_SPACE;
328 state->tx_buf = (uchar*)state->txbd + NUM_TX_BDS * sizeof(I2C_BD);
329 state->err_cb = NULL;
331 PRINTD(("[I2C] rxbd = %08x\n", (int)state->rxbd));
332 PRINTD(("[I2C] txbd = %08x\n", (int)state->txbd));
333 PRINTD(("[I2C] tx_buf = %08x\n", (int)state->tx_buf));
335 /* clear the buffer memory */
336 memset((char *)state->tx_buf, 0, MAX_TX_SPACE);
340 i2c_send(i2c_state_t *state,
341 unsigned char address,
342 unsigned char secondary_address,
345 unsigned char *dataout)
347 volatile I2C_BD *txbd;
350 PRINTD(("[I2C] i2c_send add=%02d sec=%02d flag=%02d size=%d\n",
351 address, secondary_address, flags, size));
353 /* trying to send message larger than BD */
354 if (size > I2C_RXTX_LEN)
355 return I2CERR_MSG_TOO_LONG;
357 /* no more free bds */
358 if (state->tx_idx >= NUM_TX_BDS || state->tx_space < (2 + size))
359 return I2CERR_NO_BUFFERS;
361 txbd = (I2C_BD *)state->txbd;
362 txbd->addr = state->tx_buf;
364 PRINTD(("[I2C] txbd = %08x\n", (int)txbd));
366 if (flags & I2CF_START_COND) {
367 PRINTD(("[I2C] Formatting addresses...\n"));
368 if (flags & I2CF_ENABLE_SECONDARY) {
369 txbd->length = size + 2; /* Length of msg + dest addr */
370 txbd->addr[0] = address << 1;
371 txbd->addr[1] = secondary_address;
374 txbd->length = size + 1; /* Length of msg + dest addr */
375 txbd->addr[0] = address << 1; /* Write dest addr to BD */
379 txbd->length = size; /* Length of message */
384 txbd->status = BD_SC_READY;
385 if (flags & I2CF_START_COND)
386 txbd->status |= BD_I2C_TX_START;
387 if (flags & I2CF_STOP_COND)
388 txbd->status |= BD_SC_LAST | BD_SC_WRAP;
390 /* Copy data to send into buffer */
391 PRINTD(("[I2C] copy data...\n"));
392 for(j = 0; j < size; i++, j++)
393 txbd->addr[i] = dataout[j];
395 PRINTD(("[I2C] txbd: length=0x%04x status=0x%04x addr[0]=0x%02x addr[1]=0x%02x\n",
402 state->tx_buf += txbd->length;
403 state->tx_space -= txbd->length;
405 state->txbd = (void*)(txbd + 1);
411 i2c_receive(i2c_state_t *state,
412 unsigned char address,
413 unsigned char secondary_address,
415 unsigned short size_to_expect,
416 unsigned char *datain)
418 volatile I2C_BD *rxbd, *txbd;
420 PRINTD(("[I2C] i2c_receive %02d %02d %02d\n", address, secondary_address, flags));
422 /* Expected to receive too much */
423 if (size_to_expect > I2C_RXTX_LEN)
424 return I2CERR_MSG_TOO_LONG;
426 /* no more free bds */
427 if (state->tx_idx >= NUM_TX_BDS || state->rx_idx >= NUM_RX_BDS
428 || state->tx_space < 2)
429 return I2CERR_NO_BUFFERS;
431 rxbd = (I2C_BD *)state->rxbd;
432 txbd = (I2C_BD *)state->txbd;
434 PRINTD(("[I2C] rxbd = %08x\n", (int)rxbd));
435 PRINTD(("[I2C] txbd = %08x\n", (int)txbd));
437 txbd->addr = state->tx_buf;
439 /* set up TXBD for destination address */
440 if (flags & I2CF_ENABLE_SECONDARY) {
442 txbd->addr[0] = address << 1; /* Write data */
443 txbd->addr[1] = secondary_address; /* Internal address */
444 txbd->status = BD_SC_READY;
446 txbd->length = 1 + size_to_expect;
447 txbd->addr[0] = (address << 1) | 0x01;
448 txbd->status = BD_SC_READY;
449 memset(&txbd->addr[1], 0, txbd->length);
452 /* set up rxbd for reception */
453 rxbd->status = BD_SC_EMPTY;
454 rxbd->length = size_to_expect;
457 txbd->status |= BD_I2C_TX_START;
458 if (flags & I2CF_STOP_COND) {
459 txbd->status |= BD_SC_LAST | BD_SC_WRAP;
460 rxbd->status |= BD_SC_WRAP;
463 PRINTD(("[I2C] txbd: length=0x%04x status=0x%04x addr[0]=0x%02x addr[1]=0x%02x\n",
468 PRINTD(("[I2C] rxbd: length=0x%04x status=0x%04x addr[0]=0x%02x addr[1]=0x%02x\n",
475 state->tx_buf += txbd->length;
476 state->tx_space -= txbd->length;
478 state->txbd = (void*)(txbd + 1);
480 state->rxbd = (void*)(rxbd + 1);
486 static int i2c_doio(i2c_state_t *state)
488 volatile immap_t *immap = (immap_t *)CFG_IMMR ;
489 volatile cpm8xx_t *cp = (cpm8xx_t *)&immap->im_cpm;
490 volatile i2c8xx_t *i2c = (i2c8xx_t *)&immap->im_i2c;
491 volatile iic_t *iip = (iic_t *)&cp->cp_dparam[PROFF_IIC];
492 volatile I2C_BD *txbd, *rxbd;
495 PRINTD(("[I2C] i2c_doio\n"));
497 #ifdef CFG_I2C_UCODE_PATCH
498 iip = (iic_t *)&cp->cp_dpmem[iip->iic_rpbase];
501 if (state->tx_idx <= 0 && state->rx_idx <= 0) {
502 PRINTD(("[I2C] No I/O is queued\n"));
503 return I2CERR_QUEUE_EMPTY;
506 iip->iic_rbptr = iip->iic_rbase;
507 iip->iic_tbptr = iip->iic_tbase;
510 PRINTD(("[I2C] Enabling I2C...\n"));
511 i2c->i2c_i2mod |= 0x01;
513 /* Begin transmission */
514 i2c->i2c_i2com |= 0x80;
516 /* Loop until transmit & receive completed */
518 if (state->tx_idx > 0) {
519 txbd = ((I2C_BD*)state->txbd) - 1;
520 PRINTD(("[I2C] Transmitting...(txbd=0x%08lx)\n", (ulong)txbd));
521 while((txbd->status & BD_SC_READY) && (j++ < TOUT_LOOP)) {
525 __asm__ __volatile__ ("eieio");
529 if ((state->rx_idx > 0) && (j < TOUT_LOOP)) {
530 rxbd = ((I2C_BD*)state->rxbd) - 1;
531 PRINTD(("[I2C] Receiving...(rxbd=0x%08lx)\n", (ulong)rxbd));
532 while((rxbd->status & BD_SC_EMPTY) && (j++ < TOUT_LOOP)) {
536 __asm__ __volatile__ ("eieio");
541 i2c->i2c_i2mod &= ~0x01;
543 if (state->err_cb != NULL) {
547 * if we have an error callback function, look at the
548 * error bits in the bd status and pass them back
551 if ((n = state->tx_idx) > 0) {
552 for (i = 0; i < n; i++) {
553 txbd = ((I2C_BD*)state->txbd) - (n - i);
554 if ((b = txbd->status & BD_I2C_TX_ERR) != 0)
555 (*state->err_cb)(I2CECB_TX_ERR|b, i);
559 if ((n = state->rx_idx) > 0) {
560 for (i = 0; i < n; i++) {
561 rxbd = ((I2C_BD*)state->rxbd) - (n - i);
562 if ((b = rxbd->status & BD_I2C_RX_ERR) != 0)
563 (*state->err_cb)(I2CECB_RX_ERR|b, i);
568 (*state->err_cb)(I2CECB_TIMEOUT, 0);
571 return (j >= TOUT_LOOP) ? I2CERR_TIMEOUT : 0;
574 static int had_tx_nak;
577 i2c_test_callback(int flags, int xnum)
579 if ((flags & I2CECB_TX_ERR) && (flags & I2CECB_TX_NAK))
583 int i2c_probe(uchar chip)
589 i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE);
593 state.err_cb = i2c_test_callback;
596 rc = i2c_receive(&state, chip, 0, I2CF_START_COND|I2CF_STOP_COND, 1, buf);
601 rc = i2c_doio(&state);
603 if ((rc != 0) && (rc != I2CERR_TIMEOUT))
609 int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
611 DECLARE_GLOBAL_DATA_PTR;
621 xaddr[0] = (addr >> 24) & 0xFF;
622 xaddr[1] = (addr >> 16) & 0xFF;
623 xaddr[2] = (addr >> 8) & 0xFF;
624 xaddr[3] = addr & 0xFF;
626 #ifdef CFG_I2C_EEPROM_ADDR_OVERFLOW
628 * EEPROM chips that implement "address overflow" are ones like
629 * Catalyst 24WC04/08/16 which has 9/10/11 bits of address and the
630 * extra bits end up in the "chip address" bit slots. This makes
631 * a 24WC08 (1Kbyte) chip look like four 256 byte chips.
633 * Note that we consider the length of the address field to still
634 * be one byte because the extra address bits are hidden in the
637 chip |= ((addr >> (alen * 8)) & CFG_I2C_EEPROM_ADDR_OVERFLOW);
642 rc = i2c_send(&state, chip, 0, I2CF_START_COND, alen, &xaddr[4-alen]);
644 if (gd->have_console)
645 printf("i2c_read: i2c_send failed (%d)\n", rc);
649 rc = i2c_receive(&state, chip, 0, I2CF_STOP_COND, len, buffer);
651 if (gd->have_console)
652 printf("i2c_read: i2c_receive failed (%d)\n", rc);
656 rc = i2c_doio(&state);
658 if (gd->have_console)
659 printf("i2c_read: i2c_doio failed (%d)\n", rc);
665 int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
667 DECLARE_GLOBAL_DATA_PTR;
673 xaddr[0] = (addr >> 24) & 0xFF;
674 xaddr[1] = (addr >> 16) & 0xFF;
675 xaddr[2] = (addr >> 8) & 0xFF;
676 xaddr[3] = addr & 0xFF;
678 #ifdef CFG_I2C_EEPROM_ADDR_OVERFLOW
680 * EEPROM chips that implement "address overflow" are ones like
681 * Catalyst 24WC04/08/16 which has 9/10/11 bits of address and the
682 * extra bits end up in the "chip address" bit slots. This makes
683 * a 24WC08 (1Kbyte) chip look like four 256 byte chips.
685 * Note that we consider the length of the address field to still
686 * be one byte because the extra address bits are hidden in the
689 chip |= ((addr >> (alen * 8)) & CFG_I2C_EEPROM_ADDR_OVERFLOW);
694 rc = i2c_send(&state, chip, 0, I2CF_START_COND, alen, &xaddr[4-alen]);
696 if (gd->have_console)
697 printf("i2c_write: first i2c_send failed (%d)\n", rc);
701 rc = i2c_send(&state, 0, 0, I2CF_STOP_COND, len, buffer);
703 if (gd->have_console)
704 printf("i2c_write: second i2c_send failed (%d)\n", rc);
708 rc = i2c_doio(&state);
710 if (gd->have_console)
711 printf("i2c_write: i2c_doio failed (%d)\n", rc);
718 i2c_reg_read(uchar i2c_addr, uchar reg)
722 i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE);
724 i2c_read(i2c_addr, reg, 1, &buf, 1);
730 i2c_reg_write(uchar i2c_addr, uchar reg, uchar val)
732 i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE);
734 i2c_write(i2c_addr, reg, 1, &val, 1);
737 #endif /* CONFIG_HARD_I2C */