3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
32 #if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(FEC_ENET)
34 #ifdef CFG_DISCOVER_PHY
36 static void mii_discover_phy(void);
39 /* Ethernet Transmit and Receive Buffers */
40 #define DBUF_LENGTH 1520
46 #define PKT_MAXBUF_SIZE 1518
47 #define PKT_MINBUF_SIZE 64
48 #define PKT_MAXBLR_SIZE 1520
51 static char txbuf[DBUF_LENGTH];
53 static uint rxIdx; /* index of the current RX buffer */
54 static uint txIdx; /* index of the current TX buffer */
57 * FEC Ethernet Tx and Rx buffer descriptors allocated at the
58 * immr->udata_bd address on Dual-Port RAM
59 * Provide for Double Buffering
62 typedef volatile struct CommonBufferDescriptor {
63 cbd_t rxbd[PKTBUFSRX]; /* Rx BD */
64 cbd_t txbd[TX_BUF_CNT]; /* Tx BD */
67 static RTXBD *rtx = NULL;
69 static int fec_send(struct eth_device* dev, volatile void *packet, int length);
70 static int fec_recv(struct eth_device* dev);
71 static int fec_init(struct eth_device* dev, bd_t * bd);
72 static void fec_halt(struct eth_device* dev);
74 int fec_initialize(bd_t *bis)
76 struct eth_device* dev;
78 dev = (struct eth_device*) malloc(sizeof *dev);
79 memset(dev, 0, sizeof *dev);
81 sprintf(dev->name, "FEC ETHERNET");
94 static int fec_send(struct eth_device* dev, volatile void *packet, int length)
97 volatile immap_t *immr = (immap_t *) CFG_IMMR;
98 volatile fec_t *fecp = &(immr->im_cpm.cp_fec);
104 while ((rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY) && (j<TOUT_LOOP)) {
109 printf("TX not ready\n");
112 rtx->txbd[txIdx].cbd_bufaddr = (uint)packet;
113 rtx->txbd[txIdx].cbd_datlen = length;
114 rtx->txbd[txIdx].cbd_sc |= BD_ENET_TX_READY | BD_ENET_TX_LAST;
117 /* Activate transmit Buffer Descriptor polling */
118 fecp->fec_x_des_active = 0x01000000; /* Descriptor polling active */
121 while ((rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY) && (j<TOUT_LOOP)) {
122 #if defined(CONFIG_ICU862)
130 printf("TX timeout\n");
133 printf("%s[%d] %s: cycles: %d status: %x retry cnt: %d\n",
134 __FILE__,__LINE__,__FUNCTION__,j,rtx->txbd[txIdx].cbd_sc,
135 (rtx->txbd[txIdx].cbd_sc & 0x003C)>>2);
137 /* return only status bits */;
138 rc = (rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_STATS);
140 txIdx = (txIdx + 1) % TX_BUF_CNT;
145 static int fec_recv(struct eth_device* dev)
148 volatile immap_t *immr = (immap_t *) CFG_IMMR;
149 volatile fec_t *fecp = &(immr->im_cpm.cp_fec);
152 /* section 16.9.23.2 */
153 if (rtx->rxbd[rxIdx].cbd_sc & BD_ENET_RX_EMPTY) {
155 break; /* nothing received - leave for() loop */
158 length = rtx->rxbd[rxIdx].cbd_datlen;
160 if (rtx->rxbd[rxIdx].cbd_sc & 0x003f) {
162 printf("%s[%d] err: %x\n",
163 __FUNCTION__,__LINE__,rtx->rxbd[rxIdx].cbd_sc);
166 /* Pass the packet up to the protocol layers. */
167 NetReceive(NetRxPackets[rxIdx], length - 4);
170 /* Give the buffer back to the FEC. */
171 rtx->rxbd[rxIdx].cbd_datlen = 0;
173 /* wrap around buffer index when necessary */
174 if ((rxIdx + 1) >= PKTBUFSRX) {
175 rtx->rxbd[PKTBUFSRX - 1].cbd_sc = (BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY);
178 rtx->rxbd[rxIdx].cbd_sc = BD_ENET_RX_EMPTY;
184 /* Try to fill Buffer Descriptors */
185 fecp->fec_r_des_active = 0x01000000; /* Descriptor polling active */
191 /**************************************************************
193 * FEC Ethernet Initialization Routine
195 *************************************************************/
197 #define FEC_ECNTRL_PINMUX 0x00000004
198 #define FEC_ECNTRL_ETHER_EN 0x00000002
199 #define FEC_ECNTRL_RESET 0x00000001
201 #define FEC_RCNTRL_BC_REJ 0x00000010
202 #define FEC_RCNTRL_PROM 0x00000008
203 #define FEC_RCNTRL_MII_MODE 0x00000004
204 #define FEC_RCNTRL_DRT 0x00000002
205 #define FEC_RCNTRL_LOOP 0x00000001
207 #define FEC_TCNTRL_FDEN 0x00000004
208 #define FEC_TCNTRL_HBC 0x00000002
209 #define FEC_TCNTRL_GTS 0x00000001
211 #define FEC_RESET_DELAY 50
213 static int fec_init(struct eth_device* dev, bd_t * bd)
217 volatile immap_t *immr = (immap_t *) CFG_IMMR;
218 volatile fec_t *fecp = &(immr->im_cpm.cp_fec);
220 #if defined(CONFIG_FADS) && \
221 ( defined(CONFIG_MPC860T) || defined(CONFIG_MPC866_et_al) )
222 /* configure FADS for fast (FEC) ethernet, half-duplex */
223 /* The LXT970 needs about 50ms to recover from reset, so
224 * wait for it by discovering the PHY before leaving eth_init().
227 volatile uint *bcsr4 = (volatile uint *) BCSR4;
228 *bcsr4 = (*bcsr4 & ~(BCSR4_FETH_EN | BCSR4_FETHCFG1))
229 | (BCSR4_FETHCFG0 | BCSR4_FETHFDE | BCSR4_FETHRST);
231 /* reset the LXT970 PHY */
232 *bcsr4 &= ~BCSR4_FETHRST;
234 *bcsr4 |= BCSR4_FETHRST;
239 * A delay is required between a reset of the FEC block and
240 * initialization of other FEC registers because the reset takes
241 * some time to complete. If you don't delay, subsequent writes
242 * to FEC registers might get killed by the reset routine which is
245 fecp->fec_ecntrl = FEC_ECNTRL_PINMUX | FEC_ECNTRL_RESET;
247 (fecp->fec_ecntrl & FEC_ECNTRL_RESET) && (i < FEC_RESET_DELAY);
251 if (i == FEC_RESET_DELAY) {
252 printf ("FEC_RESET_DELAY timeout\n");
256 /* We use strictly polling mode only
260 /* Clear any pending interrupt
262 fecp->fec_ievent = 0xffc0;
264 /* No need to set the IVEC register */
266 /* Set station address
268 #define ea eth_get_dev()->enetaddr
269 fecp->fec_addr_low = (ea[0] << 24) | (ea[1] << 16) |
270 (ea[2] << 8) | (ea[3] ) ;
271 fecp->fec_addr_high = (ea[4] << 8) | (ea[5] ) ;
274 /* Clear multicast address hash table
276 fecp->fec_hash_table_high = 0;
277 fecp->fec_hash_table_low = 0;
279 /* Set maximum receive buffer size.
281 fecp->fec_r_buff_size = PKT_MAXBLR_SIZE;
283 /* Set maximum frame length
285 fecp->fec_r_hash = PKT_MAXBUF_SIZE;
288 * Setup Buffers and Buffer Desriptors
294 #ifdef CFG_ALLOC_DPRAM
295 rtx = (RTXBD *) (immr->im_cpm.cp_dpmem + dpram_alloc_align(sizeof(RTXBD),8));
297 rtx = (RTXBD *) (immr->im_cpm.cp_dpmem + CPM_FEC_BASE);
301 * Setup Receiver Buffer Descriptors (13.14.24.18)
305 for (i = 0; i < PKTBUFSRX; i++) {
306 rtx->rxbd[i].cbd_sc = BD_ENET_RX_EMPTY;
307 rtx->rxbd[i].cbd_datlen = 0; /* Reset */
308 rtx->rxbd[i].cbd_bufaddr = (uint) NetRxPackets[i];
310 rtx->rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP;
313 * Setup Ethernet Transmitter Buffer Descriptors (13.14.24.19)
317 for (i = 0; i < TX_BUF_CNT; i++) {
318 rtx->txbd[i].cbd_sc = BD_ENET_TX_LAST | BD_ENET_TX_TC;
319 rtx->txbd[i].cbd_datlen = 0; /* Reset */
320 rtx->txbd[i].cbd_bufaddr = (uint) (&txbuf[0]);
322 rtx->txbd[TX_BUF_CNT - 1].cbd_sc |= BD_ENET_TX_WRAP;
324 /* Set receive and transmit descriptor base
326 fecp->fec_r_des_start = (unsigned int) (&rtx->rxbd[0]);
327 fecp->fec_x_des_start = (unsigned int) (&rtx->txbd[0]);
331 #if 0 /* Full duplex mode */
332 fecp->fec_r_cntrl = FEC_RCNTRL_MII_MODE;
333 fecp->fec_x_cntrl = FEC_TCNTRL_FDEN;
334 #else /* Half duplex mode */
335 fecp->fec_r_cntrl = FEC_RCNTRL_MII_MODE | FEC_RCNTRL_DRT;
336 fecp->fec_x_cntrl = 0;
339 /* Enable big endian and don't care about SDMA FC.
341 fecp->fec_fun_code = 0x78000000;
343 /* Set MII speed to 2.5 MHz or slightly below.
344 * According to the MPC860T (Rev. D) Fast ethernet controller user
346 * the MII management interface clock must be less than or equal
348 * This MDC frequency is equal to system clock / (2 * MII_SPEED).
349 * Then MII_SPEED = system_clock / 2 * 2,5 Mhz.
351 fecp->fec_mii_speed = ((bd->bi_intfreq + 4999999) / 5000000) << 1;
353 #if !defined(CONFIG_ICU862) && !defined(CONFIG_IAD210)
354 /* Configure all of port D for MII.
356 immr->im_ioport.iop_pdpar = 0x1fff;
358 /* Bits moved from Rev. D onward */
359 if ((get_immr (0) & 0xffff) < 0x0501) {
360 immr->im_ioport.iop_pddir = 0x1c58; /* Pre rev. D */
362 immr->im_ioport.iop_pddir = 0x1fff; /* Rev. D and later */
365 /* Configure port A for MII.
368 #if defined(CONFIG_ICU862) && defined(CFG_DISCOVER_PHY)
370 /* On the ICU862 board the MII-MDC pin is routed to PD8 pin
371 * of CPU, so for this board we need to configure Utopia and
372 * enable PD8 to MII-MDC function */
373 immr->im_ioport.iop_pdpar |= 0x4080;
376 /* Has Utopia been configured? */
377 if (immr->im_ioport.iop_pdpar & (0x8000 >> 1)) {
379 * YES - Use MUXED mode for UTOPIA bus.
380 * This frees Port A for use by MII (see 862UM table 41-6).
382 immr->im_ioport.utmode &= ~0x80;
385 * NO - set SPLIT mode for UTOPIA bus.
387 * This doesn't really effect UTOPIA (which isn't
388 * enabled anyway) but just tells the 862
389 * to use port A for MII (see 862UM table 41-6).
391 immr->im_ioport.utmode |= 0x80;
393 #endif /* !defined(CONFIG_ICU862) */
398 /* Now enable the transmit and receive processing
400 fecp->fec_ecntrl = FEC_ECNTRL_PINMUX | FEC_ECNTRL_ETHER_EN;
402 #ifdef CFG_DISCOVER_PHY
403 /* wait for the PHY to wake up after reset
408 /* And last, try to fill Rx Buffer Descriptors */
409 fecp->fec_r_des_active = 0x01000000; /* Descriptor polling active */
415 static void fec_halt(struct eth_device* dev)
418 volatile immap_t *immr = (immap_t *)CFG_IMMR;
419 immr->im_cpm.cp_scc[SCC_ENET].scc_gsmrl &= ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
426 volatile immap_t *immr = (immap_t *)CFG_IMMR;
427 immr->im_cpm.cp_scc[SCC_ENET].scc_gsmrl |= (SCC_GSMRL_ENR | SCC_GSMRL_ENT);
431 #if defined(CFG_DISCOVER_PHY) || (CONFIG_COMMANDS & CFG_CMD_MII)
433 static int phyaddr = -1; /* didn't find a PHY yet */
436 /* Make MII read/write commands for the FEC.
439 #define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | \
442 #define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | \
443 (REG & 0x1f) << 18) | \
446 /* Interrupt events/masks.
448 #define FEC_ENET_HBERR ((uint)0x80000000) /* Heartbeat error */
449 #define FEC_ENET_BABR ((uint)0x40000000) /* Babbling receiver */
450 #define FEC_ENET_BABT ((uint)0x20000000) /* Babbling transmitter */
451 #define FEC_ENET_GRA ((uint)0x10000000) /* Graceful stop complete */
452 #define FEC_ENET_TXF ((uint)0x08000000) /* Full frame transmitted */
453 #define FEC_ENET_TXB ((uint)0x04000000) /* A buffer was transmitted */
454 #define FEC_ENET_RXF ((uint)0x02000000) /* Full frame received */
455 #define FEC_ENET_RXB ((uint)0x01000000) /* A buffer was received */
456 #define FEC_ENET_MII ((uint)0x00800000) /* MII interrupt */
457 #define FEC_ENET_EBERR ((uint)0x00400000) /* SDMA bus error */
459 /* PHY identification
461 #define PHY_ID_LXT970 0x78100000 /* LXT970 */
462 #define PHY_ID_LXT971 0x001378e0 /* LXT971 and 972 */
463 #define PHY_ID_82555 0x02a80150 /* Intel 82555 */
464 #define PHY_ID_QS6612 0x01814400 /* QS6612 */
465 #define PHY_ID_AMD79C784 0x00225610 /* AMD 79C784 */
466 #define PHY_ID_LSI80225 0x0016f870 /* LSI 80225 */
467 #define PHY_ID_LSI80225B 0x0016f880 /* LSI 80225/B */
470 /* send command to phy using mii, wait for result */
472 mii_send(uint mii_cmd)
477 ep = &(((immap_t *)CFG_IMMR)->im_cpm.cp_fec);
479 ep->fec_mii_data = mii_cmd; /* command to phy */
481 /* wait for mii complete */
482 while (!(ep->fec_ievent & FEC_ENET_MII))
483 ; /* spin until done */
484 mii_reply = ep->fec_mii_data; /* result from phy */
485 ep->fec_ievent = FEC_ENET_MII; /* clear MII complete */
487 printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n",
488 __FILE__,__LINE__,__FUNCTION__,mii_cmd,mii_reply);
490 return (mii_reply & 0xffff); /* data read from phy */
492 #endif /* CFG_DISCOVER_PHY || (CONFIG_COMMANDS & CFG_CMD_MII) */
494 #if defined(CFG_DISCOVER_PHY)
496 mii_discover_phy(void)
498 #define MAX_PHY_PASSES 11
502 phyaddr = -1; /* didn't find a PHY yet */
503 for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) {
505 /* PHY may need more time to recover from reset.
506 * The LXT970 needs 50ms typical, no maximum is
507 * specified, so wait 10ms before try again.
508 * With 11 passes this gives it 100ms to wake up.
510 udelay(10000); /* wait 10ms */
512 for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) {
513 phytype = mii_send(mk_mii_read(phyno, PHY_PHYIDR1));
515 printf("PHY type 0x%x pass %d type ", phytype, pass);
517 if (phytype != 0xffff) {
520 phytype |= mii_send(mk_mii_read(phyno,
524 printf("PHY @ 0x%x pass %d type ",phyno,pass);
525 switch (phytype & 0xfffffff0) {
538 case PHY_ID_AMD79C784:
539 printf("AMD79C784\n");
541 case PHY_ID_LSI80225B:
542 printf("LSI L80225/B\n");
545 printf("0x%08x\n", phytype);
553 printf("No PHY device found.\n");
556 #endif /* CFG_DISCOVER_PHY */
558 #if (CONFIG_COMMANDS & CFG_CMD_MII) && !defined(CONFIG_BITBANGMII)
560 static int mii_init_done = 0;
562 /****************************************************************************
563 * mii_init -- Initialize the MII for MII command without ethernet
564 * This function is a subset of eth_init
565 ****************************************************************************
569 DECLARE_GLOBAL_DATA_PTR;
572 volatile immap_t *immr = (immap_t *) CFG_IMMR;
573 volatile fec_t *fecp = &(immr->im_cpm.cp_fec);
576 if (mii_init_done != 0) {
581 * A delay is required between a reset of the FEC block and
582 * initialization of other FEC registers because the reset takes
583 * some time to complete. If you don't delay, subsequent writes
584 * to FEC registers might get killed by the reset routine which is
588 fecp->fec_ecntrl = FEC_ECNTRL_PINMUX | FEC_ECNTRL_RESET;
590 (fecp->fec_ecntrl & FEC_ECNTRL_RESET) && (i < FEC_RESET_DELAY);
594 if (i == FEC_RESET_DELAY) {
595 printf ("FEC_RESET_DELAY timeout\n");
599 /* We use strictly polling mode only
603 /* Clear any pending interrupt
605 fecp->fec_ievent = 0xffc0;
607 /* Set MII speed to 2.5 MHz or slightly below.
608 * According to the MPC860T (Rev. D) Fast ethernet controller user
610 * the MII management interface clock must be less than or equal
612 * This MDC frequency is equal to system clock / (2 * MII_SPEED).
613 * Then MII_SPEED = system_clock / 2 * 2,5 Mhz.
615 fecp->fec_mii_speed = ((bd->bi_intfreq + 4999999) / 5000000) << 1;
617 #if !defined(CONFIG_ICU862) && !defined(CONFIG_IAD210)
618 /* Configure all of port D for MII.
620 immr->im_ioport.iop_pdpar = 0x1fff;
622 /* Bits moved from Rev. D onward */
623 if ((get_immr (0) & 0xffff) < 0x0501) {
624 immr->im_ioport.iop_pddir = 0x1c58; /* Pre rev. D */
626 immr->im_ioport.iop_pddir = 0x1fff; /* Rev. D and later */
629 /* Configure port A for MII.
632 #if defined(CONFIG_ICU862)
634 /* On the ICU862 board the MII-MDC pin is routed to PD8 pin
635 * of CPU, so for this board we need to configure Utopia and
636 * enable PD8 to MII-MDC function */
637 immr->im_ioport.iop_pdpar |= 0x4080;
640 /* Has Utopia been configured? */
641 if (immr->im_ioport.iop_pdpar & (0x8000 >> 1)) {
643 * YES - Use MUXED mode for UTOPIA bus.
644 * This frees Port A for use by MII (see 862UM table 41-6).
646 immr->im_ioport.utmode &= ~0x80;
649 * NO - set SPLIT mode for UTOPIA bus.
651 * This doesn't really effect UTOPIA (which isn't
652 * enabled anyway) but just tells the 862
653 * to use port A for MII (see 862UM table 41-6).
655 immr->im_ioport.utmode |= 0x80;
657 #endif /* !defined(CONFIG_ICU862) */
658 /* Now enable the transmit and receive processing
660 fecp->fec_ecntrl = FEC_ECNTRL_PINMUX | FEC_ECNTRL_ETHER_EN;
664 /*****************************************************************************
665 * Read and write a MII PHY register, routines used by MII Utilities
667 * FIXME: These routines are expected to return 0 on success, but mii_send
668 * does _not_ return an error code. Maybe 0xFFFF means error, i.e.
669 * no PHY connected...
670 * For now always return 0.
671 * FIXME: These routines only work after calling eth_init() at least once!
672 * Otherwise they hang in mii_send() !!! Sorry!
673 *****************************************************************************/
675 int miiphy_read(unsigned char addr, unsigned char reg, unsigned short *value)
677 short rdreg; /* register working value */
680 printf ("miiphy_read(0x%x) @ 0x%x = ", reg, addr);
682 rdreg = mii_send(mk_mii_read(addr, reg));
687 printf ("0x%04x\n", *value);
693 int miiphy_write(unsigned char addr, unsigned char reg, unsigned short value)
695 short rdreg; /* register working value */
698 printf ("miiphy_write(0x%x) @ 0x%x = ", reg, addr);
701 rdreg = mii_send(mk_mii_write(addr, reg, value));
704 printf ("0x%04x\n", value);
709 #endif /* (CONFIG_COMMANDS & CFG_CMD_MII) && !defined(CONFIG_BITBANGMII)*/
711 #endif /* CFG_CMD_NET, FEC_ENET */