2 * (C) Copyright 2000-2002
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
30 #if defined(CFG_RTCSC) || defined(CFG_RMDS)
31 DECLARE_GLOBAL_DATA_PTR;
34 #if defined(CFG_I2C_UCODE_PATCH) || defined(CFG_SPI_UCODE_PATCH)
35 void cpm_load_patch (volatile immap_t * immr);
39 * Breath some life into the CPU...
41 * Set up the memory map,
42 * initialize a bunch of registers,
43 * initialize the UPM's
45 void cpu_init_f (volatile immap_t * immr)
48 volatile memctl8xx_t *memctl = &immr->im_memctl;
55 /* SYPCR - contains watchdog control (11-9) */
57 immr->im_siu_conf.sc_sypcr = CFG_SYPCR;
59 #if defined(CONFIG_WATCHDOG)
60 reset_8xx_watchdog (immr);
61 #endif /* CONFIG_WATCHDOG */
63 /* SIUMCR - contains debug pin configuration (11-6) */
64 #ifndef CONFIG_SVM_SC8xx
65 immr->im_siu_conf.sc_siumcr |= CFG_SIUMCR;
67 immr->im_siu_conf.sc_siumcr = CFG_SIUMCR;
69 /* initialize timebase status and control register (11-26) */
72 immr->im_sitk.sitk_tbscrk = KAPWR_KEY;
73 immr->im_sit.sit_tbscr = CFG_TBSCR;
75 /* initialize the PIT (11-31) */
77 immr->im_sitk.sitk_piscrk = KAPWR_KEY;
78 immr->im_sit.sit_piscr = CFG_PISCR;
80 /* System integration timers. Don't change EBDF! (15-27) */
82 immr->im_clkrstk.cark_sccrk = KAPWR_KEY;
83 reg = immr->im_clkrst.car_sccr;
86 immr->im_clkrst.car_sccr = reg;
88 /* PLL (CPU clock) settings (15-30) */
90 immr->im_clkrstk.cark_plprcrk = KAPWR_KEY;
92 #ifndef CONFIG_MBX /* MBX board does things different */
94 /* If CFG_PLPRCR (set in the various *_config.h files) tries to
95 * set the MF field, then just copy CFG_PLPRCR over car_plprcr,
96 * otherwise OR in CFG_PLPRCR so we do not change the current MF
99 * For newer (starting MPC866) chips PLPRCR layout is different.
102 if (get_immr(0xFFFF) >= MPC8xx_NEW_CLK)
103 mfmask = PLPRCR_MFACT_MSK;
105 mfmask = PLPRCR_MF_MSK;
107 if ((CFG_PLPRCR & mfmask) != 0)
108 reg = CFG_PLPRCR; /* reset control bits */
110 reg = immr->im_clkrst.car_plprcr;
111 reg &= mfmask; /* isolate MF-related fields */
112 reg |= CFG_PLPRCR; /* reset control bits */
114 immr->im_clkrst.car_plprcr = reg;
121 /* perform BR0 reset that MPC850 Rev. A can't guarantee */
122 reg = memctl->memc_br0;
123 reg &= BR_PS_MSK; /* Clear everything except Port Size bits */
124 reg |= BR_V; /* then add just the "Bank Valid" bit */
125 memctl->memc_br0 = reg;
127 /* Map banks 0 (and maybe 1) to the FLASH banks 0 (and 1) at
128 * preliminary addresses - these have to be modified later
129 * when FLASH size has been determined
131 * Depending on the size of the memory region defined by
132 * CFG_OR0_REMAP some boards (wide address mask) allow to map the
133 * CFG_MONITOR_BASE, while others (narrower address mask) can't
134 * map CFG_MONITOR_BASE.
136 * For example, for CONFIG_IVMS8, the CFG_MONITOR_BASE is
137 * 0xff000000, but CFG_OR0_REMAP's address mask is 0xfff80000.
139 * If BR0 wasn't loaded with address base 0xff000000, then BR0's
140 * base address remains as 0x00000000. However, the address mask
141 * have been narrowed to 512Kb, so CFG_MONITOR_BASE wasn't mapped
144 * This is why CONFIG_IVMS8 and similar boards must load BR0 with
145 * CFG_BR0_PRELIM in advance.
147 * [Thanks to Michael Liao for this explanation.
148 * I owe him a free beer. - wd]
151 #if defined(CONFIG_GTH) || \
152 defined(CONFIG_HERMES) || \
153 defined(CONFIG_ICU862) || \
154 defined(CONFIG_IP860) || \
155 defined(CONFIG_IVML24) || \
156 defined(CONFIG_IVMS8) || \
157 defined(CONFIG_LWMON) || \
158 defined(CONFIG_MHPC) || \
159 defined(CONFIG_PCU_E) || \
160 defined(CONFIG_R360MPI) || \
161 defined(CONFIG_RMU) || \
162 defined(CONFIG_RPXCLASSIC) || \
163 defined(CONFIG_RPXLITE) || \
164 defined(CONFIG_SPD823TS)
166 memctl->memc_br0 = CFG_BR0_PRELIM;
169 #if defined(CFG_OR0_REMAP)
170 memctl->memc_or0 = CFG_OR0_REMAP;
172 #if defined(CFG_OR1_REMAP)
173 memctl->memc_or1 = CFG_OR1_REMAP;
175 #if defined(CFG_OR5_REMAP)
176 memctl->memc_or5 = CFG_OR5_REMAP;
179 /* now restrict to preliminary range */
180 memctl->memc_br0 = CFG_BR0_PRELIM;
181 memctl->memc_or0 = CFG_OR0_PRELIM;
183 #if (defined(CFG_OR1_PRELIM) && defined(CFG_BR1_PRELIM))
184 memctl->memc_or1 = CFG_OR1_PRELIM;
185 memctl->memc_br1 = CFG_BR1_PRELIM;
188 #if defined(CONFIG_IP860) /* disable CS0 now that Flash is mapped on CS1 */
189 memctl->memc_br0 = 0;
192 #if defined(CFG_OR2_PRELIM) && defined(CFG_BR2_PRELIM)
193 memctl->memc_or2 = CFG_OR2_PRELIM;
194 memctl->memc_br2 = CFG_BR2_PRELIM;
197 #if defined(CFG_OR3_PRELIM) && defined(CFG_BR3_PRELIM)
198 memctl->memc_or3 = CFG_OR3_PRELIM;
199 memctl->memc_br3 = CFG_BR3_PRELIM;
202 #if defined(CFG_OR4_PRELIM) && defined(CFG_BR4_PRELIM)
203 memctl->memc_or4 = CFG_OR4_PRELIM;
204 memctl->memc_br4 = CFG_BR4_PRELIM;
207 #if defined(CFG_OR5_PRELIM) && defined(CFG_BR5_PRELIM)
208 memctl->memc_or5 = CFG_OR5_PRELIM;
209 memctl->memc_br5 = CFG_BR5_PRELIM;
212 #if defined(CFG_OR6_PRELIM) && defined(CFG_BR6_PRELIM)
213 memctl->memc_or6 = CFG_OR6_PRELIM;
214 memctl->memc_br6 = CFG_BR6_PRELIM;
217 #if defined(CFG_OR7_PRELIM) && defined(CFG_BR7_PRELIM)
218 memctl->memc_or7 = CFG_OR7_PRELIM;
219 memctl->memc_br7 = CFG_BR7_PRELIM;
222 #endif /* ! CONFIG_MBX */
227 immr->im_cpm.cp_cpcr = CPM_CR_RST | CPM_CR_FLG;
228 do { /* Spin until command processed */
230 } while (immr->im_cpm.cp_cpcr & CPM_CR_FLG);
234 * on the MBX, things are a little bit different:
235 * - we need to read the VPD to get board information
236 * - the plprcr is set up dynamically
237 * - the memory controller is set up dynamically
240 #endif /* CONFIG_MBX */
242 #ifdef CONFIG_RPXCLASSIC
246 #if defined(CONFIG_RPXLITE) && defined(CFG_ENV_IS_IN_NVRAM)
250 #ifdef CFG_RCCR /* must be done before cpm_load_patch() */
251 /* write config value */
252 immr->im_cpm.cp_rccr = CFG_RCCR;
255 #if defined(CFG_I2C_UCODE_PATCH) || defined(CFG_SPI_UCODE_PATCH)
256 cpm_load_patch (immr); /* load mpc8xx microcode patch */
261 * initialize higher level parts of CPU like timers
263 int cpu_init_r (void)
265 #if defined(CFG_RTCSC) || defined(CFG_RMDS)
267 volatile immap_t *immr = (volatile immap_t *) (bd->bi_immr_base);
271 /* Unlock RTSC register */
272 immr->im_sitk.sitk_rtcsck = KAPWR_KEY;
273 /* write config value */
274 immr->im_sit.sit_rtcsc = CFG_RTCSC;
278 /* write config value */
279 immr->im_cpm.cp_rmds = CFG_RMDS;