2 * (C) Copyright 2000-2002
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
30 #if defined(CFG_I2C_UCODE_PATCH) || defined(CFG_SPI_UCODE_PATCH)
31 void cpm_load_patch (volatile immap_t * immr);
35 * Breath some life into the CPU...
37 * Set up the memory map,
38 * initialize a bunch of registers,
39 * initialize the UPM's
41 void cpu_init_f (volatile immap_t * immr)
44 volatile memctl8xx_t *memctl = &immr->im_memctl;
48 /* SYPCR - contains watchdog control (11-9) */
50 immr->im_siu_conf.sc_sypcr = CFG_SYPCR;
52 #if defined(CONFIG_WATCHDOG)
53 reset_8xx_watchdog (immr);
54 #endif /* CONFIG_WATCHDOG */
56 /* SIUMCR - contains debug pin configuration (11-6) */
57 #ifndef CONFIG_SVM_SC8xx
58 immr->im_siu_conf.sc_siumcr |= CFG_SIUMCR;
60 immr->im_siu_conf.sc_siumcr = CFG_SIUMCR;
62 /* initialize timebase status and control register (11-26) */
65 immr->im_sitk.sitk_tbscrk = KAPWR_KEY;
66 immr->im_sit.sit_tbscr = CFG_TBSCR;
68 /* initialize the PIT (11-31) */
70 immr->im_sitk.sitk_piscrk = KAPWR_KEY;
71 immr->im_sit.sit_piscr = CFG_PISCR;
73 /* System integration timers. Don't change EBDF! (15-27) */
75 immr->im_clkrstk.cark_sccrk = KAPWR_KEY;
76 reg = immr->im_clkrst.car_sccr;
79 immr->im_clkrst.car_sccr = reg;
81 /* PLL (CPU clock) settings (15-30) */
83 immr->im_clkrstk.cark_plprcrk = KAPWR_KEY;
85 #ifndef CONFIG_MBX /* MBX board does things different */
87 /* If CFG_PLPRCR (set in the various *_config.h files) tries to
88 * set the MF field, then just copy CFG_PLPRCR over car_plprcr,
89 * otherwise OR in CFG_PLPRCR so we do not change the currentMF
92 #if ((CFG_PLPRCR & PLPRCR_MF_MSK) != 0)
93 reg = CFG_PLPRCR; /* reset control bits */
95 reg = immr->im_clkrst.car_plprcr;
96 reg &= PLPRCR_MF_MSK; /* isolate MF field */
97 reg |= CFG_PLPRCR; /* reset control bits */
99 immr->im_clkrst.car_plprcr = reg;
105 /* perform BR0 reset that MPC850 Rev. A can't guarantee */
106 reg = memctl->memc_br0;
107 reg &= BR_PS_MSK; /* Clear everything except Port Size bits */
108 reg |= BR_V; /* then add just the "Bank Valid" bit */
109 memctl->memc_br0 = reg;
111 /* Map banks 0 (and maybe 1) to the FLASH banks 0 (and 1) at
112 * preliminary addresses - these have to be modified later
113 * when FLASH size has been determined
115 * Depending on the size of the memory region defined by
116 * CFG_OR0_REMAP some boards (wide address mask) allow to map the
117 * CFG_MONITOR_BASE, while others (narrower address mask) can't
118 * map CFG_MONITOR_BASE.
120 * For example, for CONFIG_IVMS8, the CFG_MONITOR_BASE is
121 * 0xff000000, but CFG_OR0_REMAP's address mask is 0xfff80000.
123 * If BR0 wasn't loaded with address base 0xff000000, then BR0's
124 * base address remains as 0x00000000. However, the address mask
125 * have been narrowed to 512Kb, so CFG_MONITOR_BASE wasn't mapped
128 * This is why CONFIG_IVMS8 and similar boards must load BR0 with
129 * CFG_BR0_PRELIM in advance.
131 * [Thanks to Michael Liao for this explanation.
132 * I owe him a free beer. - wd]
135 #if defined(CONFIG_ADDERII) || \
136 defined(CONFIG_GTH) || \
137 defined(CONFIG_HERMES) || \
138 defined(CONFIG_ICU862) || \
139 defined(CONFIG_IP860) || \
140 defined(CONFIG_IVML24) || \
141 defined(CONFIG_IVMS8) || \
142 defined(CONFIG_LWMON) || \
143 defined(CONFIG_MHPC) || \
144 defined(CONFIG_PCU_E) || \
145 defined(CONFIG_R360MPI) || \
146 defined(CONFIG_RPXCLASSIC) || \
147 defined(CONFIG_RPXLITE) || \
148 defined(CONFIG_SPD823TS) || \
149 defined(CONFIG_MPC86xADS) || \
150 (defined(CONFIG_MPC860T) && defined(CONFIG_FADS))
152 memctl->memc_br0 = CFG_BR0_PRELIM;
155 #if defined(CFG_OR0_REMAP)
156 memctl->memc_or0 = CFG_OR0_REMAP;
158 #if defined(CFG_OR1_REMAP)
159 memctl->memc_or1 = CFG_OR1_REMAP;
161 #if defined(CFG_OR5_REMAP)
162 memctl->memc_or5 = CFG_OR5_REMAP;
165 /* now restrict to preliminary range */
166 memctl->memc_br0 = CFG_BR0_PRELIM;
167 memctl->memc_or0 = CFG_OR0_PRELIM;
169 #if (defined(CFG_OR1_PRELIM) && defined(CFG_BR1_PRELIM))
170 memctl->memc_or1 = CFG_OR1_PRELIM;
171 memctl->memc_br1 = CFG_BR1_PRELIM;
174 #if defined(CONFIG_IP860) /* disable CS0 now that Flash is mapped on CS1 */
175 memctl->memc_br0 = 0;
178 #if defined(CFG_OR2_PRELIM) && defined(CFG_BR2_PRELIM)
179 memctl->memc_or2 = CFG_OR2_PRELIM;
180 memctl->memc_br2 = CFG_BR2_PRELIM;
183 #if defined(CFG_OR3_PRELIM) && defined(CFG_BR3_PRELIM)
184 memctl->memc_or3 = CFG_OR3_PRELIM;
185 memctl->memc_br3 = CFG_BR3_PRELIM;
188 #if defined(CFG_OR4_PRELIM) && defined(CFG_BR4_PRELIM)
189 memctl->memc_or4 = CFG_OR4_PRELIM;
190 memctl->memc_br4 = CFG_BR4_PRELIM;
193 #if defined(CFG_OR5_PRELIM) && defined(CFG_BR5_PRELIM)
194 memctl->memc_or5 = CFG_OR5_PRELIM;
195 memctl->memc_br5 = CFG_BR5_PRELIM;
198 #if defined(CFG_OR6_PRELIM) && defined(CFG_BR6_PRELIM)
199 memctl->memc_or6 = CFG_OR6_PRELIM;
200 memctl->memc_br6 = CFG_BR6_PRELIM;
203 #if defined(CFG_OR7_PRELIM) && defined(CFG_BR7_PRELIM)
204 memctl->memc_or7 = CFG_OR7_PRELIM;
205 memctl->memc_br7 = CFG_BR7_PRELIM;
208 #endif /* ! CONFIG_MBX */
213 immr->im_cpm.cp_cpcr = CPM_CR_RST | CPM_CR_FLG;
214 do { /* Spin until command processed */
216 } while (immr->im_cpm.cp_cpcr & CPM_CR_FLG);
220 * on the MBX, things are a little bit different:
221 * - we need to read the VPD to get board information
222 * - the plprcr is set up dynamically
223 * - the memory controller is set up dynamically
226 #endif /* CONFIG_MBX */
228 #ifdef CONFIG_RPXCLASSIC
232 #ifdef CFG_RCCR /* must be done before cpm_load_patch() */
233 /* write config value */
234 immr->im_cpm.cp_rccr = CFG_RCCR;
237 #if defined(CFG_I2C_UCODE_PATCH) || defined(CFG_SPI_UCODE_PATCH)
238 cpm_load_patch (immr); /* load mpc8xx microcode patch */
243 * initialize higher level parts of CPU like timers
245 int cpu_init_r (void)
247 #if defined(CFG_RTCSC) || defined(CFG_RMDS)
248 DECLARE_GLOBAL_DATA_PTR;
251 volatile immap_t *immr = (volatile immap_t *) (bd->bi_immr_base);
255 /* Unlock RTSC register */
256 immr->im_sitk.sitk_rtcsck = KAPWR_KEY;
257 /* write config value */
258 immr->im_sit.sit_rtcsc = CFG_RTCSC;
262 /* write config value */
263 immr->im_cpm.cp_rmds = CFG_RMDS;