2 * (C) Copyright 2000-2002
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29 * written or collected and sometimes rewritten by
30 * Magnus Damm <damm@bitsmart.com>
32 * minor modifications by
33 * Wolfgang Denk <wd@denx.de>
40 #include <asm/cache.h>
42 static char *cpu_warning = "\n " \
43 "*** Warning: CPU Core has Silicon Bugs -- Check the Errata ***";
45 #if ((defined(CONFIG_MPC86x) || defined(CONFIG_MPC855)) && \
46 !defined(CONFIG_MPC862))
48 static int check_CPU (long clock, uint pvr, uint immr)
51 # if defined(CONFIG_MPC855)
53 # elif defined(CONFIG_MPC860P)
58 volatile immap_t *immap = (immap_t *) (immr & 0xFFFF0000);
65 /* the highest 16 bits should be 0x0050 for a 860 */
67 if ((pvr >> 16) != 0x0050)
70 k = (immr << 16) | *((ushort *) & immap->im_cpm.cp_dparam[0xB0]);
74 * Some boards use sockets so different CPUs can be used.
75 * We have to check chip version in run time.
78 case 0x00020001: pre = 'P'; suf = ""; break;
79 case 0x00030001: suf = ""; break;
80 case 0x00120003: suf = "A"; break;
81 case 0x00130003: suf = "A3"; break;
83 case 0x00200004: suf = "B"; break;
85 case 0x00300004: suf = "C"; break;
86 case 0x00310004: suf = "C1"; m = 1; break;
88 case 0x00200064: mid = "SR"; suf = "B"; break;
89 case 0x00300065: mid = "SR"; suf = "C"; break;
90 case 0x00310065: mid = "SR"; suf = "C1"; m = 1; break;
91 case 0x05010000: suf = "D3"; m = 1; break;
92 case 0x05020000: suf = "D4"; m = 1; break;
93 /* this value is not documented anywhere */
94 case 0x40000000: pre = 'P'; suf = "D"; m = 1; break;
95 /* MPC866P/MPC866T/MPC859T/MPC859DSL/MPC852T */
96 case 0x08000003: pre = 'M'; suf = ""; m = 1;
99 # if defined(CONFIG_MPC852T)
101 # elif defined(CONFIG_MPC859T)
103 # elif defined(CONFIG_MPC859DSL)
105 # elif defined(CONFIG_MPC866T)
108 "PC866x"; /* Unknown chip from MPC866 family */
111 case 0x09000000: pre = 'M'; mid = suf = ""; m = 1;
113 id_str = "PC885"; /* 870/875/880/885 */
116 default: suf = NULL; break;
120 id_str = "PC86x"; /* Unknown 86x chip */
122 printf ("%c%s%sZPnn%s", pre, id_str, mid, suf);
124 printf ("unknown M%s (0x%08x)", id_str, k);
126 printf (" at %s MHz:", strmhz (buf, clock));
128 printf (" %u kB I-Cache", checkicache () >> 10);
129 printf (" %u kB D-Cache", checkdcache () >> 10);
131 /* do we have a FEC (860T/P or 852/859/866)? */
133 immap->im_cpm.cp_fec.fec_addr_low = 0x12345678;
134 if (immap->im_cpm.cp_fec.fec_addr_low == 0x12345678) {
135 printf (" FEC present");
145 if(clock != measure_gclk()) {
146 printf ("clock %ldHz != %dHz\n", clock, measure_gclk());
153 #elif defined(CONFIG_MPC862)
155 static int check_CPU (long clock, uint pvr, uint immr)
157 volatile immap_t *immap = (immap_t *) (immr & 0xFFFF0000);
164 /* the highest 16 bits should be 0x0050 for a 8xx */
166 if ((pvr >> 16) != 0x0050)
169 k = (immr << 16) | *((ushort *) & immap->im_cpm.cp_dparam[0xB0]);
174 /* this value is not documented anywhere */
175 case 0x06000000: mid = "P"; suf = "0"; break;
176 case 0x06010001: mid = "P"; suf = "A"; m = 1; break;
177 case 0x07000003: mid = "P"; suf = "B"; m = 1; break;
178 default: suf = NULL; break;
182 printf ("%cPC862%sZPnn%s", pre, mid, suf);
184 printf ("unknown MPC862 (0x%08x)", k);
186 printf (" at %s MHz:", strmhz (buf, clock));
188 printf (" %u kB I-Cache", checkicache () >> 10);
189 printf (" %u kB D-Cache", checkdcache () >> 10);
191 /* lets check and see if we're running on a 862T (or P?) */
193 immap->im_cpm.cp_fec.fec_addr_low = 0x12345678;
194 if (immap->im_cpm.cp_fec.fec_addr_low == 0x12345678) {
195 printf (" FEC present");
207 #elif defined(CONFIG_MPC823)
209 static int check_CPU (long clock, uint pvr, uint immr)
211 volatile immap_t *immap = (immap_t *) (immr & 0xFFFF0000);
216 /* the highest 16 bits should be 0x0050 for a 8xx */
218 if ((pvr >> 16) != 0x0050)
221 k = (immr << 16) | *((ushort *) & immap->im_cpm.cp_dparam[0xB0]);
226 case 0x20000000: suf = "0"; break;
227 case 0x20010000: suf = "0.1"; break;
228 case 0x20020000: suf = "Z2/3"; break;
229 case 0x20020001: suf = "Z3"; break;
230 case 0x21000000: suf = "A"; break;
231 case 0x21010000: suf = "B"; m = 1; break;
232 case 0x21010001: suf = "B2"; m = 1; break;
234 case 0x24010000: suf = NULL;
235 puts ("PPC823EZTnnB2");
240 printf ("unknown MPC823 (0x%08x)", k);
244 printf ("PPC823ZTnn%s", suf);
246 printf (" at %s MHz:", strmhz (buf, clock));
248 printf (" %u kB I-Cache", checkicache () >> 10);
249 printf (" %u kB D-Cache", checkdcache () >> 10);
251 /* lets check and see if we're running on a 860T (or P?) */
253 immap->im_cpm.cp_fec.fec_addr_low = 0x12345678;
254 if (immap->im_cpm.cp_fec.fec_addr_low == 0x12345678) {
255 puts (" FEC present");
267 #elif defined(CONFIG_MPC850)
269 static int check_CPU (long clock, uint pvr, uint immr)
271 volatile immap_t *immap = (immap_t *) (immr & 0xFFFF0000);
275 /* the highest 16 bits should be 0x0050 for a 8xx */
277 if ((pvr >> 16) != 0x0050)
280 k = (immr << 16) | *((ushort *) & immap->im_cpm.cp_dparam[0xB0]);
285 printf ("XPC850xxZT");
288 printf ("XPC850xxZTA");
291 printf ("XPC850xxZTB");
295 printf ("XPC850xxZTC");
299 printf ("unknown MPC850 (0x%08x)", k);
301 printf (" at %s MHz:", strmhz (buf, clock));
303 printf (" %u kB I-Cache", checkicache () >> 10);
304 printf (" %u kB D-Cache", checkdcache () >> 10);
306 /* lets check and see if we're running on a 850T (or P?) */
308 immap->im_cpm.cp_fec.fec_addr_low = 0x12345678;
309 if (immap->im_cpm.cp_fec.fec_addr_low == 0x12345678) {
310 printf (" FEC present");
324 /* ------------------------------------------------------------------------- */
328 DECLARE_GLOBAL_DATA_PTR;
330 ulong clock = gd->cpu_clk;
331 uint immr = get_immr (0); /* Return full IMMR contents */
332 uint pvr = get_pvr ();
336 /* 850 has PARTNUM 20 */
337 /* 801 has PARTNUM 10 */
338 return check_CPU (clock, pvr, immr);
341 /* ------------------------------------------------------------------------- */
343 /* the standard 860 has 128 sets of 16 bytes in 2 ways (= 4 kB) */
344 /* the 860 P (plus) has 256 sets of 16 bytes in 4 ways (= 16 kB) */
346 int checkicache (void)
348 volatile immap_t *immap = (immap_t *) CFG_IMMR;
349 volatile memctl8xx_t *memctl = &immap->im_memctl;
350 u32 cacheon = rd_ic_cst () & IDC_ENABLED;
353 u32 k = memctl->memc_br1 & ~0x00007fff; /* probe in flash memoryarea */
355 u32 k = memctl->memc_br0 & ~0x00007fff; /* probe in flash memoryarea */
360 wr_ic_cst (IDC_UNALL);
361 wr_ic_cst (IDC_INVALL);
362 wr_ic_cst (IDC_DISABLE);
363 __asm__ volatile ("isync");
365 while (!((m = rd_ic_cst ()) & IDC_CERR2)) {
367 wr_ic_cst (IDC_LDLCK);
368 __asm__ volatile ("isync");
371 k += 0x10; /* the number of bytes in a cacheline */
374 wr_ic_cst (IDC_UNALL);
375 wr_ic_cst (IDC_INVALL);
378 wr_ic_cst (IDC_ENABLE);
380 wr_ic_cst (IDC_DISABLE);
382 __asm__ volatile ("isync");
387 /* ------------------------------------------------------------------------- */
389 /* the standard 860 has 128 sets of 16 bytes in 2 ways (= 4 kB) */
390 /* the 860 P (plus) has 256 sets of 16 bytes in 2 ways (= 8 kB) */
391 /* call with cache disabled */
393 int checkdcache (void)
395 volatile immap_t *immap = (immap_t *) CFG_IMMR;
396 volatile memctl8xx_t *memctl = &immap->im_memctl;
397 u32 cacheon = rd_dc_cst () & IDC_ENABLED;
400 u32 k = memctl->memc_br1 & ~0x00007fff; /* probe in flash memoryarea */
402 u32 k = memctl->memc_br0 & ~0x00007fff; /* probe in flash memoryarea */
407 wr_dc_cst (IDC_UNALL);
408 wr_dc_cst (IDC_INVALL);
409 wr_dc_cst (IDC_DISABLE);
411 while (!((m = rd_dc_cst ()) & IDC_CERR2)) {
413 wr_dc_cst (IDC_LDLCK);
415 k += 0x10; /* the number of bytes in a cacheline */
418 wr_dc_cst (IDC_UNALL);
419 wr_dc_cst (IDC_INVALL);
422 wr_dc_cst (IDC_ENABLE);
424 wr_dc_cst (IDC_DISABLE);
429 /* ------------------------------------------------------------------------- */
431 void upmconfig (uint upm, uint * table, uint size)
435 volatile immap_t *immap = (immap_t *) CFG_IMMR;
436 volatile memctl8xx_t *memctl = &immap->im_memctl;
438 for (i = 0; i < size; i++) {
439 memctl->memc_mdr = table[i]; /* (16-15) */
440 memctl->memc_mcr = addr | upm; /* (16-16) */
445 /* ------------------------------------------------------------------------- */
447 int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
451 volatile immap_t *immap = (immap_t *) CFG_IMMR;
453 immap->im_clkrst.car_plprcr |= PLPRCR_CSR; /* Checkstop Reset enable */
455 /* Interrupts and MMU off */
456 __asm__ volatile ("mtspr 81, 0");
457 __asm__ volatile ("mfmsr %0":"=r" (msr));
460 __asm__ volatile ("mtmsr %0"::"r" (msr));
463 * Trying to execute the next instruction at a non-existing address
464 * should cause a machine check, resulting in reset
466 #ifdef CFG_RESET_ADDRESS
467 addr = CFG_RESET_ADDRESS;
470 * note: when CFG_MONITOR_BASE points to a RAM address, CFG_MONITOR_BASE
471 * - sizeof (ulong) is usually a valid address. Better pick an address
472 * known to be invalid on your system and assign it to CFG_RESET_ADDRESS.
473 * "(ulong)-1" used to be a good choice for many systems...
475 addr = CFG_MONITOR_BASE - sizeof (ulong);
477 ((void (*)(void)) addr) ();
481 /* ------------------------------------------------------------------------- */
484 * Get timebase clock frequency (like cpu_clk in Hz)
486 * See sections 14.2 and 14.6 of the User's Manual
488 unsigned long get_tbclk (void)
490 DECLARE_GLOBAL_DATA_PTR;
492 uint immr = get_immr (0); /* Return full IMMR contents */
493 volatile immap_t *immap = (volatile immap_t *)(immr & 0xFFFF0000);
494 ulong oscclk, factor, pll;
496 if (immap->im_clkrst.car_sccr & SCCR_TBS) {
497 return (gd->cpu_clk / 16);
500 pll = immap->im_clkrst.car_plprcr;
502 #define PLPRCR_val(a) ((pll & PLPRCR_ ## a ## _MSK) >> PLPRCR_ ## a ## _SHIFT)
505 * For newer PQ1 chips (MPC866/87x/88x families), PLL multiplication
506 * factor is calculated as follows:
511 * factor = -----------------
514 * For older chips, it's just MF field of PLPRCR plus one.
516 if ((immr & 0xFFFF) >= MPC8xx_NEW_CLK) { /* MPC866/87x/88x series */
517 factor = (PLPRCR_val(MFI) + PLPRCR_val(MFN)/(PLPRCR_val(MFD)+1))/
518 (PLPRCR_val(PDF)+1) / (1<<PLPRCR_val(S));
520 factor = PLPRCR_val(MF)+1;
523 oscclk = gd->cpu_clk / factor;
525 if ((immap->im_clkrst.car_sccr & SCCR_RTSEL) == 0 || factor > 2) {
528 return (oscclk / 16);
531 /* ------------------------------------------------------------------------- */
533 #if defined(CONFIG_WATCHDOG)
534 void watchdog_reset (void)
536 int re_enable = disable_interrupts ();
538 reset_8xx_watchdog ((immap_t *) CFG_IMMR);
540 enable_interrupts ();
543 void reset_8xx_watchdog (volatile immap_t * immr)
545 # if defined(CONFIG_LWMON)
547 * The LWMON board uses a MAX6301 Watchdog
548 * with the trigger pin connected to port PA.7
550 * (The old board version used a MAX706TESA Watchdog, which
551 * had to be handled exactly the same.)
553 # define WATCHDOG_BIT 0x0100
554 immr->im_ioport.iop_papar &= ~(WATCHDOG_BIT); /* GPIO */
555 immr->im_ioport.iop_padir |= WATCHDOG_BIT; /* Output */
556 immr->im_ioport.iop_paodr &= ~(WATCHDOG_BIT); /* active output */
558 immr->im_ioport.iop_padat ^= WATCHDOG_BIT; /* Toggle WDI */
561 * All other boards use the MPC8xx Internal Watchdog
563 immr->im_siu_conf.sc_swsr = 0x556c; /* write magic1 */
564 immr->im_siu_conf.sc_swsr = 0xaa39; /* write magic2 */
565 # endif /* CONFIG_LWMON */
568 #endif /* CONFIG_WATCHDOG */
570 /* ------------------------------------------------------------------------- */