2 * (C) Copyright 2000-2002
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29 * written or collected and sometimes rewritten by
30 * Magnus Damm <damm@bitsmart.com>
32 * minor modifications by
33 * Wolfgang Denk <wd@denx.de>
40 #include <asm/cache.h>
42 static char *cpu_warning = "\n " \
43 "*** Warning: CPU Core has Silicon Bugs -- Check the Errata ***";
45 #if ((defined(CONFIG_MPC86x) || defined(CONFIG_MPC855)) && \
46 !defined(CONFIG_MPC862))
48 static int check_CPU (long clock, uint pvr, uint immr)
51 # if defined(CONFIG_MPC855)
53 # elif defined(CONFIG_MPC860P)
58 volatile immap_t *immap = (immap_t *) (immr & 0xFFFF0000);
65 /* the highest 16 bits should be 0x0050 for a 860 */
67 if ((pvr >> 16) != 0x0050)
70 k = (immr << 16) | *((ushort *) & immap->im_cpm.cp_dparam[0xB0]);
74 * Some boards use sockets so different CPUs can be used.
75 * We have to check chip version in run time.
78 case 0x00020001: pre = 'P'; suf = ""; break;
79 case 0x00030001: suf = ""; break;
80 case 0x00120003: suf = "A"; break;
81 case 0x00130003: suf = "A3"; break;
83 case 0x00200004: suf = "B"; break;
85 case 0x00300004: suf = "C"; break;
86 case 0x00310004: suf = "C1"; m = 1; break;
88 case 0x00200064: mid = "SR"; suf = "B"; break;
89 case 0x00300065: mid = "SR"; suf = "C"; break;
90 case 0x00310065: mid = "SR"; suf = "C1"; m = 1; break;
91 case 0x05010000: suf = "D3"; m = 1; break;
92 case 0x05020000: suf = "D4"; m = 1; break;
93 /* this value is not documented anywhere */
94 case 0x40000000: pre = 'P'; suf = "D"; m = 1; break;
95 /* MPC866P/MPC866T/MPC859T/MPC859DSL/MPC852T */
96 case 0x08000003: pre = 'M'; suf = ""; m = 1;
99 # if defined(CONFIG_MPC852T)
101 # elif defined(CONFIG_MPC859T)
103 # elif defined(CONFIG_MPC859DSL)
105 # elif defined(CONFIG_MPC866T)
108 "PC866x"; /* Unknown chip from MPC866 family */
111 case 0x09000000: pre = 'M'; mid = suf = ""; m = 1;
113 id_str = "PC885"; /* 870/875/880/885 */
116 default: suf = NULL; break;
120 id_str = "PC86x"; /* Unknown 86x chip */
122 printf ("%c%s%sZPnn%s", pre, id_str, mid, suf);
124 printf ("unknown M%s (0x%08x)", id_str, k);
127 #if defined(CFG_866_CPUCLK_MIN) && defined(CFG_866_CPUCLK_MAX)
128 printf (" at %s MHz [%d.%d...%d.%d MHz]\n ",
130 CFG_866_CPUCLK_MIN / 1000000,
131 ((CFG_866_CPUCLK_MIN % 1000000) + 50000) / 100000,
132 CFG_866_CPUCLK_MAX / 1000000,
133 ((CFG_866_CPUCLK_MAX % 1000000) + 50000) / 100000
136 printf (" at %s MHz: ", strmhz (buf, clock));
138 printf ("%u kB I-Cache %u kB D-Cache",
139 checkicache () >> 10,
143 /* do we have a FEC (860T/P or 852/859/866)? */
145 immap->im_cpm.cp_fec.fec_addr_low = 0x12345678;
146 if (immap->im_cpm.cp_fec.fec_addr_low == 0x12345678) {
147 printf (" FEC present");
157 if(clock != measure_gclk()) {
158 printf ("clock %ldHz != %dHz\n", clock, measure_gclk());
165 #elif defined(CONFIG_MPC862)
167 static int check_CPU (long clock, uint pvr, uint immr)
169 volatile immap_t *immap = (immap_t *) (immr & 0xFFFF0000);
176 /* the highest 16 bits should be 0x0050 for a 8xx */
178 if ((pvr >> 16) != 0x0050)
181 k = (immr << 16) | *((ushort *) & immap->im_cpm.cp_dparam[0xB0]);
186 /* this value is not documented anywhere */
187 case 0x06000000: mid = "P"; suf = "0"; break;
188 case 0x06010001: mid = "P"; suf = "A"; m = 1; break;
189 case 0x07000003: mid = "P"; suf = "B"; m = 1; break;
190 default: suf = NULL; break;
194 printf ("%cPC862%sZPnn%s", pre, mid, suf);
196 printf ("unknown MPC862 (0x%08x)", k);
198 printf (" at %s MHz:", strmhz (buf, clock));
200 printf (" %u kB I-Cache", checkicache () >> 10);
201 printf (" %u kB D-Cache", checkdcache () >> 10);
203 /* lets check and see if we're running on a 862T (or P?) */
205 immap->im_cpm.cp_fec.fec_addr_low = 0x12345678;
206 if (immap->im_cpm.cp_fec.fec_addr_low == 0x12345678) {
207 printf (" FEC present");
219 #elif defined(CONFIG_MPC823)
221 static int check_CPU (long clock, uint pvr, uint immr)
223 volatile immap_t *immap = (immap_t *) (immr & 0xFFFF0000);
228 /* the highest 16 bits should be 0x0050 for a 8xx */
230 if ((pvr >> 16) != 0x0050)
233 k = (immr << 16) | *((ushort *) & immap->im_cpm.cp_dparam[0xB0]);
238 case 0x20000000: suf = "0"; break;
239 case 0x20010000: suf = "0.1"; break;
240 case 0x20020000: suf = "Z2/3"; break;
241 case 0x20020001: suf = "Z3"; break;
242 case 0x21000000: suf = "A"; break;
243 case 0x21010000: suf = "B"; m = 1; break;
244 case 0x21010001: suf = "B2"; m = 1; break;
246 case 0x24010000: suf = NULL;
247 puts ("PPC823EZTnnB2");
252 printf ("unknown MPC823 (0x%08x)", k);
256 printf ("PPC823ZTnn%s", suf);
258 printf (" at %s MHz:", strmhz (buf, clock));
260 printf (" %u kB I-Cache", checkicache () >> 10);
261 printf (" %u kB D-Cache", checkdcache () >> 10);
263 /* lets check and see if we're running on a 860T (or P?) */
265 immap->im_cpm.cp_fec.fec_addr_low = 0x12345678;
266 if (immap->im_cpm.cp_fec.fec_addr_low == 0x12345678) {
267 puts (" FEC present");
279 #elif defined(CONFIG_MPC850)
281 static int check_CPU (long clock, uint pvr, uint immr)
283 volatile immap_t *immap = (immap_t *) (immr & 0xFFFF0000);
287 /* the highest 16 bits should be 0x0050 for a 8xx */
289 if ((pvr >> 16) != 0x0050)
292 k = (immr << 16) | *((ushort *) & immap->im_cpm.cp_dparam[0xB0]);
297 printf ("XPC850xxZT");
300 printf ("XPC850xxZTA");
303 printf ("XPC850xxZTB");
307 printf ("XPC850xxZTC");
311 printf ("unknown MPC850 (0x%08x)", k);
313 printf (" at %s MHz:", strmhz (buf, clock));
315 printf (" %u kB I-Cache", checkicache () >> 10);
316 printf (" %u kB D-Cache", checkdcache () >> 10);
318 /* lets check and see if we're running on a 850T (or P?) */
320 immap->im_cpm.cp_fec.fec_addr_low = 0x12345678;
321 if (immap->im_cpm.cp_fec.fec_addr_low == 0x12345678) {
322 printf (" FEC present");
336 /* ------------------------------------------------------------------------- */
340 DECLARE_GLOBAL_DATA_PTR;
342 ulong clock = gd->cpu_clk;
343 uint immr = get_immr (0); /* Return full IMMR contents */
344 uint pvr = get_pvr ();
348 /* 850 has PARTNUM 20 */
349 /* 801 has PARTNUM 10 */
350 return check_CPU (clock, pvr, immr);
353 /* ------------------------------------------------------------------------- */
355 /* the standard 860 has 128 sets of 16 bytes in 2 ways (= 4 kB) */
356 /* the 860 P (plus) has 256 sets of 16 bytes in 4 ways (= 16 kB) */
358 int checkicache (void)
360 volatile immap_t *immap = (immap_t *) CFG_IMMR;
361 volatile memctl8xx_t *memctl = &immap->im_memctl;
362 u32 cacheon = rd_ic_cst () & IDC_ENABLED;
365 u32 k = memctl->memc_br1 & ~0x00007fff; /* probe in flash memoryarea */
367 u32 k = memctl->memc_br0 & ~0x00007fff; /* probe in flash memoryarea */
372 wr_ic_cst (IDC_UNALL);
373 wr_ic_cst (IDC_INVALL);
374 wr_ic_cst (IDC_DISABLE);
375 __asm__ volatile ("isync");
377 while (!((m = rd_ic_cst ()) & IDC_CERR2)) {
379 wr_ic_cst (IDC_LDLCK);
380 __asm__ volatile ("isync");
383 k += 0x10; /* the number of bytes in a cacheline */
386 wr_ic_cst (IDC_UNALL);
387 wr_ic_cst (IDC_INVALL);
390 wr_ic_cst (IDC_ENABLE);
392 wr_ic_cst (IDC_DISABLE);
394 __asm__ volatile ("isync");
399 /* ------------------------------------------------------------------------- */
401 /* the standard 860 has 128 sets of 16 bytes in 2 ways (= 4 kB) */
402 /* the 860 P (plus) has 256 sets of 16 bytes in 2 ways (= 8 kB) */
403 /* call with cache disabled */
405 int checkdcache (void)
407 volatile immap_t *immap = (immap_t *) CFG_IMMR;
408 volatile memctl8xx_t *memctl = &immap->im_memctl;
409 u32 cacheon = rd_dc_cst () & IDC_ENABLED;
412 u32 k = memctl->memc_br1 & ~0x00007fff; /* probe in flash memoryarea */
414 u32 k = memctl->memc_br0 & ~0x00007fff; /* probe in flash memoryarea */
419 wr_dc_cst (IDC_UNALL);
420 wr_dc_cst (IDC_INVALL);
421 wr_dc_cst (IDC_DISABLE);
423 while (!((m = rd_dc_cst ()) & IDC_CERR2)) {
425 wr_dc_cst (IDC_LDLCK);
427 k += 0x10; /* the number of bytes in a cacheline */
430 wr_dc_cst (IDC_UNALL);
431 wr_dc_cst (IDC_INVALL);
434 wr_dc_cst (IDC_ENABLE);
436 wr_dc_cst (IDC_DISABLE);
441 /* ------------------------------------------------------------------------- */
443 void upmconfig (uint upm, uint * table, uint size)
447 volatile immap_t *immap = (immap_t *) CFG_IMMR;
448 volatile memctl8xx_t *memctl = &immap->im_memctl;
450 for (i = 0; i < size; i++) {
451 memctl->memc_mdr = table[i]; /* (16-15) */
452 memctl->memc_mcr = addr | upm; /* (16-16) */
457 /* ------------------------------------------------------------------------- */
459 int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
463 volatile immap_t *immap = (immap_t *) CFG_IMMR;
465 immap->im_clkrst.car_plprcr |= PLPRCR_CSR; /* Checkstop Reset enable */
467 /* Interrupts and MMU off */
468 __asm__ volatile ("mtspr 81, 0");
469 __asm__ volatile ("mfmsr %0":"=r" (msr));
472 __asm__ volatile ("mtmsr %0"::"r" (msr));
475 * Trying to execute the next instruction at a non-existing address
476 * should cause a machine check, resulting in reset
478 #ifdef CFG_RESET_ADDRESS
479 addr = CFG_RESET_ADDRESS;
482 * note: when CFG_MONITOR_BASE points to a RAM address, CFG_MONITOR_BASE
483 * - sizeof (ulong) is usually a valid address. Better pick an address
484 * known to be invalid on your system and assign it to CFG_RESET_ADDRESS.
485 * "(ulong)-1" used to be a good choice for many systems...
487 addr = CFG_MONITOR_BASE - sizeof (ulong);
489 ((void (*)(void)) addr) ();
493 /* ------------------------------------------------------------------------- */
496 * Get timebase clock frequency (like cpu_clk in Hz)
498 * See sections 14.2 and 14.6 of the User's Manual
500 unsigned long get_tbclk (void)
502 DECLARE_GLOBAL_DATA_PTR;
504 uint immr = get_immr (0); /* Return full IMMR contents */
505 volatile immap_t *immap = (volatile immap_t *)(immr & 0xFFFF0000);
506 ulong oscclk, factor, pll;
508 if (immap->im_clkrst.car_sccr & SCCR_TBS) {
509 return (gd->cpu_clk / 16);
512 pll = immap->im_clkrst.car_plprcr;
514 #define PLPRCR_val(a) ((pll & PLPRCR_ ## a ## _MSK) >> PLPRCR_ ## a ## _SHIFT)
517 * For newer PQ1 chips (MPC866/87x/88x families), PLL multiplication
518 * factor is calculated as follows:
523 * factor = -----------------
526 * For older chips, it's just MF field of PLPRCR plus one.
528 if ((immr & 0x0FFF) >= MPC8xx_NEW_CLK) { /* MPC866/87x/88x series */
529 factor = (PLPRCR_val(MFI) + PLPRCR_val(MFN)/(PLPRCR_val(MFD)+1))/
530 (PLPRCR_val(PDF)+1) / (1<<PLPRCR_val(S));
532 factor = PLPRCR_val(MF)+1;
535 oscclk = gd->cpu_clk / factor;
537 if ((immap->im_clkrst.car_sccr & SCCR_RTSEL) == 0 || factor > 2) {
540 return (oscclk / 16);
543 /* ------------------------------------------------------------------------- */
545 #if defined(CONFIG_WATCHDOG)
546 void watchdog_reset (void)
548 int re_enable = disable_interrupts ();
550 reset_8xx_watchdog ((immap_t *) CFG_IMMR);
552 enable_interrupts ();
555 void reset_8xx_watchdog (volatile immap_t * immr)
557 # if defined(CONFIG_LWMON)
559 * The LWMON board uses a MAX6301 Watchdog
560 * with the trigger pin connected to port PA.7
562 * (The old board version used a MAX706TESA Watchdog, which
563 * had to be handled exactly the same.)
565 # define WATCHDOG_BIT 0x0100
566 immr->im_ioport.iop_papar &= ~(WATCHDOG_BIT); /* GPIO */
567 immr->im_ioport.iop_padir |= WATCHDOG_BIT; /* Output */
568 immr->im_ioport.iop_paodr &= ~(WATCHDOG_BIT); /* active output */
570 immr->im_ioport.iop_padat ^= WATCHDOG_BIT; /* Toggle WDI */
571 # elif defined(CONFIG_KUP4K) || defined(CONFIG_KUP4X)
573 * The KUP4 boards uses a TPS3705 Watchdog
574 * with the trigger pin connected to port PA.5
576 # define WATCHDOG_BIT 0x0400
577 immr->im_ioport.iop_papar &= ~(WATCHDOG_BIT); /* GPIO */
578 immr->im_ioport.iop_padir |= WATCHDOG_BIT; /* Output */
579 immr->im_ioport.iop_paodr &= ~(WATCHDOG_BIT); /* active output */
581 immr->im_ioport.iop_padat ^= WATCHDOG_BIT; /* Toggle WDI */
584 * All other boards use the MPC8xx Internal Watchdog
586 immr->im_siu_conf.sc_swsr = 0x556c; /* write magic1 */
587 immr->im_siu_conf.sc_swsr = 0xaa39; /* write magic2 */
588 # endif /* CONFIG_LWMON */
591 #endif /* CONFIG_WATCHDOG */
593 /* ------------------------------------------------------------------------- */