2 * (C) Copyright 2000-2002
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29 * written or collected and sometimes rewritten by
30 * Magnus Damm <damm@bitsmart.com>
32 * minor modifications by
33 * Wolfgang Denk <wd@denx.de>
40 #include <asm/cache.h>
42 static char *cpu_warning = "\n " \
43 "*** Warning: CPU Core has Silicon Bugs -- Check the Errata ***";
45 #if ((defined(CONFIG_MPC86x) || defined(CONFIG_MPC855)) && \
46 !defined(CONFIG_MPC862))
48 # if defined(CONFIG_MPC855)
49 # define ID_STR "PC855"
50 # elif defined(CONFIG_MPC852T)
51 # define ID_STR "PC852T"
52 # elif defined(CONFIG_MPC859T)
53 # define ID_STR "PC859T"
54 # elif defined(CONFIG_MPC859DSL)
55 # define ID_STR "PC859DSL"
56 # elif defined(CONFIG_MPC860P)
57 # define ID_STR "PC860P"
58 # elif defined(CONFIG_MPC866T)
59 # define ID_STR "PC866T"
61 # define ID_STR "PC86x" /* unknown 86x chip */
64 static int check_CPU (long clock, uint pvr, uint immr)
66 volatile immap_t *immap = (immap_t *) (immr & 0xFFFF0000);
73 /* the highest 16 bits should be 0x0050 for a 860 */
75 if ((pvr >> 16) != 0x0050)
78 k = (immr << 16) | *((ushort *) & immap->im_cpm.cp_dparam[0xB0]);
82 #ifdef CONFIG_MPC866_et_al
83 /* MPC866P/MPC866T/MPC859T/MPC859DSL/MPC852T */
84 case 0x08000003: pre = 'M'; suf = ""; m = 1; break;
86 case 0x00020001: pre = 'p'; suf = ""; break;
87 case 0x00030001: suf = ""; break;
88 case 0x00120003: suf = "A"; break;
89 case 0x00130003: suf = "A3"; break;
91 case 0x00200004: suf = "B"; break;
93 case 0x00300004: suf = "C"; break;
94 case 0x00310004: suf = "C1"; m = 1; break;
96 case 0x00200064: mid = "SR"; suf = "B"; break;
97 case 0x00300065: mid = "SR"; suf = "C"; break;
98 case 0x00310065: mid = "SR"; suf = "C1"; m = 1; break;
99 case 0x05010000: suf = "D3"; m = 1; break;
100 case 0x05020000: suf = "D4"; m = 1; break;
101 /* this value is not documented anywhere */
102 case 0x40000000: pre = 'P'; suf = "D"; m = 1; break;
105 default: suf = NULL; break;
109 printf ("%c" ID_STR "%sZPnn%s", pre, mid, suf);
111 printf ("unknown M" ID_STR " (0x%08x)", k);
113 printf (" at %s MHz:", strmhz (buf, clock));
115 printf (" %u kB I-Cache", checkicache () >> 10);
116 printf (" %u kB D-Cache", checkdcache () >> 10);
118 /* do we have a FEC (860T/P or 852/859/866)? */
120 immap->im_cpm.cp_fec.fec_addr_low = 0x12345678;
121 if (immap->im_cpm.cp_fec.fec_addr_low == 0x12345678) {
122 printf (" FEC present");
132 if(clock != measure_gclk()) {
133 printf ("clock %ldHz != %dHz\n", clock, measure_gclk());
140 #elif defined(CONFIG_MPC862)
142 static int check_CPU (long clock, uint pvr, uint immr)
144 volatile immap_t *immap = (immap_t *) (immr & 0xFFFF0000);
151 /* the highest 16 bits should be 0x0050 for a 8xx */
153 if ((pvr >> 16) != 0x0050)
156 k = (immr << 16) | *((ushort *) & immap->im_cpm.cp_dparam[0xB0]);
161 /* this value is not documented anywhere */
162 case 0x06000000: mid = "P"; suf = "0"; break;
163 case 0x06010001: mid = "P"; suf = "A"; m = 1; break;
164 case 0x07000003: mid = "P"; suf = "B"; m = 1; break;
165 default: suf = NULL; break;
169 printf ("%cPC862%sZPnn%s", pre, mid, suf);
171 printf ("unknown MPC862 (0x%08x)", k);
173 printf (" at %s MHz:", strmhz (buf, clock));
175 printf (" %u kB I-Cache", checkicache () >> 10);
176 printf (" %u kB D-Cache", checkdcache () >> 10);
178 /* lets check and see if we're running on a 862T (or P?) */
180 immap->im_cpm.cp_fec.fec_addr_low = 0x12345678;
181 if (immap->im_cpm.cp_fec.fec_addr_low == 0x12345678) {
182 printf (" FEC present");
194 #elif defined(CONFIG_MPC823)
196 static int check_CPU (long clock, uint pvr, uint immr)
198 volatile immap_t *immap = (immap_t *) (immr & 0xFFFF0000);
203 /* the highest 16 bits should be 0x0050 for a 8xx */
205 if ((pvr >> 16) != 0x0050)
208 k = (immr << 16) | *((ushort *) & immap->im_cpm.cp_dparam[0xB0]);
213 case 0x20000000: suf = "0"; break;
214 case 0x20010000: suf = "0.1"; break;
215 case 0x20020000: suf = "Z2/3"; break;
216 case 0x20020001: suf = "Z3"; break;
217 case 0x21000000: suf = "A"; break;
218 case 0x21010000: suf = "B"; m = 1; break;
219 case 0x21010001: suf = "B2"; m = 1; break;
221 case 0x24010000: suf = NULL;
222 puts ("PPC823EZTnnB2");
227 printf ("unknown MPC823 (0x%08x)", k);
231 printf ("PPC823ZTnn%s", suf);
233 printf (" at %s MHz:", strmhz (buf, clock));
235 printf (" %u kB I-Cache", checkicache () >> 10);
236 printf (" %u kB D-Cache", checkdcache () >> 10);
238 /* lets check and see if we're running on a 860T (or P?) */
240 immap->im_cpm.cp_fec.fec_addr_low = 0x12345678;
241 if (immap->im_cpm.cp_fec.fec_addr_low == 0x12345678) {
242 puts (" FEC present");
254 #elif defined(CONFIG_MPC850)
256 static int check_CPU (long clock, uint pvr, uint immr)
258 volatile immap_t *immap = (immap_t *) (immr & 0xFFFF0000);
262 /* the highest 16 bits should be 0x0050 for a 8xx */
264 if ((pvr >> 16) != 0x0050)
267 k = (immr << 16) | *((ushort *) & immap->im_cpm.cp_dparam[0xB0]);
272 printf ("XPC850xxZT");
275 printf ("XPC850xxZTA");
278 printf ("XPC850xxZTB");
282 printf ("XPC850xxZTC");
286 printf ("unknown MPC850 (0x%08x)", k);
288 printf (" at %s MHz:", strmhz (buf, clock));
290 printf (" %u kB I-Cache", checkicache () >> 10);
291 printf (" %u kB D-Cache", checkdcache () >> 10);
293 /* lets check and see if we're running on a 850T (or P?) */
295 immap->im_cpm.cp_fec.fec_addr_low = 0x12345678;
296 if (immap->im_cpm.cp_fec.fec_addr_low == 0x12345678) {
297 printf (" FEC present");
311 /* ------------------------------------------------------------------------- */
315 DECLARE_GLOBAL_DATA_PTR;
317 ulong clock = gd->cpu_clk;
318 uint immr = get_immr (0); /* Return full IMMR contents */
319 uint pvr = get_pvr ();
323 /* 850 has PARTNUM 20 */
324 /* 801 has PARTNUM 10 */
325 return check_CPU (clock, pvr, immr);
328 /* ------------------------------------------------------------------------- */
330 /* the standard 860 has 128 sets of 16 bytes in 2 ways (= 4 kB) */
331 /* the 860 P (plus) has 256 sets of 16 bytes in 4 ways (= 16 kB) */
333 int checkicache (void)
335 volatile immap_t *immap = (immap_t *) CFG_IMMR;
336 volatile memctl8xx_t *memctl = &immap->im_memctl;
337 u32 cacheon = rd_ic_cst () & IDC_ENABLED;
340 u32 k = memctl->memc_br1 & ~0x00007fff; /* probe in flash memoryarea */
342 u32 k = memctl->memc_br0 & ~0x00007fff; /* probe in flash memoryarea */
347 wr_ic_cst (IDC_UNALL);
348 wr_ic_cst (IDC_INVALL);
349 wr_ic_cst (IDC_DISABLE);
350 __asm__ volatile ("isync");
352 while (!((m = rd_ic_cst ()) & IDC_CERR2)) {
354 wr_ic_cst (IDC_LDLCK);
355 __asm__ volatile ("isync");
358 k += 0x10; /* the number of bytes in a cacheline */
361 wr_ic_cst (IDC_UNALL);
362 wr_ic_cst (IDC_INVALL);
365 wr_ic_cst (IDC_ENABLE);
367 wr_ic_cst (IDC_DISABLE);
369 __asm__ volatile ("isync");
374 /* ------------------------------------------------------------------------- */
376 /* the standard 860 has 128 sets of 16 bytes in 2 ways (= 4 kB) */
377 /* the 860 P (plus) has 256 sets of 16 bytes in 2 ways (= 8 kB) */
378 /* call with cache disabled */
380 int checkdcache (void)
382 volatile immap_t *immap = (immap_t *) CFG_IMMR;
383 volatile memctl8xx_t *memctl = &immap->im_memctl;
384 u32 cacheon = rd_dc_cst () & IDC_ENABLED;
387 u32 k = memctl->memc_br1 & ~0x00007fff; /* probe in flash memoryarea */
389 u32 k = memctl->memc_br0 & ~0x00007fff; /* probe in flash memoryarea */
394 wr_dc_cst (IDC_UNALL);
395 wr_dc_cst (IDC_INVALL);
396 wr_dc_cst (IDC_DISABLE);
398 while (!((m = rd_dc_cst ()) & IDC_CERR2)) {
400 wr_dc_cst (IDC_LDLCK);
402 k += 0x10; /* the number of bytes in a cacheline */
405 wr_dc_cst (IDC_UNALL);
406 wr_dc_cst (IDC_INVALL);
409 wr_dc_cst (IDC_ENABLE);
411 wr_dc_cst (IDC_DISABLE);
416 /* ------------------------------------------------------------------------- */
418 void upmconfig (uint upm, uint * table, uint size)
422 volatile immap_t *immap = (immap_t *) CFG_IMMR;
423 volatile memctl8xx_t *memctl = &immap->im_memctl;
425 for (i = 0; i < size; i++) {
426 memctl->memc_mdr = table[i]; /* (16-15) */
427 memctl->memc_mcr = addr | upm; /* (16-16) */
432 /* ------------------------------------------------------------------------- */
434 int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
438 volatile immap_t *immap = (immap_t *) CFG_IMMR;
440 immap->im_clkrst.car_plprcr |= PLPRCR_CSR; /* Checkstop Reset enable */
442 /* Interrupts and MMU off */
443 __asm__ volatile ("mtspr 81, 0");
444 __asm__ volatile ("mfmsr %0":"=r" (msr));
447 __asm__ volatile ("mtmsr %0"::"r" (msr));
450 * Trying to execute the next instruction at a non-existing address
451 * should cause a machine check, resulting in reset
453 #ifdef CFG_RESET_ADDRESS
454 addr = CFG_RESET_ADDRESS;
457 * note: when CFG_MONITOR_BASE points to a RAM address, CFG_MONITOR_BASE
458 * - sizeof (ulong) is usually a valid address. Better pick an address
459 * known to be invalid on your system and assign it to CFG_RESET_ADDRESS.
460 * "(ulong)-1" used to be a good choice for many systems...
462 addr = CFG_MONITOR_BASE - sizeof (ulong);
464 ((void (*)(void)) addr) ();
468 /* ------------------------------------------------------------------------- */
471 * Get timebase clock frequency (like cpu_clk in Hz)
473 * See table 15-5 pp. 15-16, and SCCR[RTSEL] pp. 15-27.
475 unsigned long get_tbclk (void)
477 DECLARE_GLOBAL_DATA_PTR;
479 volatile immap_t *immr = (volatile immap_t *) CFG_IMMR;
480 ulong oscclk, factor;
482 if (immr->im_clkrst.car_sccr & SCCR_TBS) {
483 return (gd->cpu_clk / 16);
485 #define PLPRCR_val(a) (((CFG_PLPRCR) & PLPRCR_ ## a ## _MSK) >> PLPRCR_ ## a ## _SHIFT)
486 #ifdef CONFIG_MPC866_et_al
490 factor = -----------------
494 factor = (PLPRCR_val(MFI) + PLPRCR_val(MFN)/(PLPRCR_val(MFD)+1))/
495 (PLPRCR_val(PDF)+1) / (1<<PLPRCR_val(S));
497 factor = PLPRCR_val(MF)+1;
500 oscclk = gd->cpu_clk / factor;
502 if ((immr->im_clkrst.car_sccr & SCCR_RTSEL) == 0 || factor > 2) {
505 return (oscclk / 16);
508 /* ------------------------------------------------------------------------- */
510 #if defined(CONFIG_WATCHDOG)
511 void watchdog_reset (void)
513 int re_enable = disable_interrupts ();
515 reset_8xx_watchdog ((immap_t *) CFG_IMMR);
517 enable_interrupts ();
520 void reset_8xx_watchdog (volatile immap_t * immr)
522 # if defined(CONFIG_LWMON)
524 * The LWMON board uses a MAX6301 Watchdog
525 * with the trigger pin connected to port PA.7
527 * (The old board version used a MAX706TESA Watchdog, which
528 * had to be handled exactly the same.)
530 # define WATCHDOG_BIT 0x0100
531 immr->im_ioport.iop_papar &= ~(WATCHDOG_BIT); /* GPIO */
532 immr->im_ioport.iop_padir |= WATCHDOG_BIT; /* Output */
533 immr->im_ioport.iop_paodr &= ~(WATCHDOG_BIT); /* active output */
535 immr->im_ioport.iop_padat ^= WATCHDOG_BIT; /* Toggle WDI */
538 * All other boards use the MPC8xx Internal Watchdog
540 immr->im_siu_conf.sc_swsr = 0x556c; /* write magic1 */
541 immr->im_siu_conf.sc_swsr = 0xaa39; /* write magic2 */
542 # endif /* CONFIG_LWMON */
545 #endif /* CONFIG_WATCHDOG */
547 /* ------------------------------------------------------------------------- */