2 * Copyright 2004 Freescale Semiconductor.
3 * Srikanth Srinivasan <srikanth.srinivaan@freescale.com>
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 /* U-Boot - Startup Code for 86xx PowerPC based Embedded Boards
27 * The processor starts at 0xfff00100 and the code is executed
28 * from flash. The code is organized to be at an other address
29 * in memory, but as long we don't jump around before relocating.
30 * board_init lies at a quite high address and when the cpu has
31 * jumped there, everything is ok.
37 #include <ppc_asm.tmpl>
40 #include <asm/cache.h>
43 #ifndef CONFIG_IDENT_STRING
44 #define CONFIG_IDENT_STRING ""
47 /* We don't want the MMU yet.
50 /* Machine Check and Recoverable Interr. */
51 #define MSR_KERNEL ( MSR_ME | MSR_RI )
54 * Set up GOT: Global Offset Table
56 * Use r14 to access the GOT
59 GOT_ENTRY(_GOT2_TABLE_)
60 GOT_ENTRY(_FIXUP_TABLE_)
63 GOT_ENTRY(_start_of_vectors)
64 GOT_ENTRY(_end_of_vectors)
65 GOT_ENTRY(transfer_to_handler)
69 GOT_ENTRY(__bss_start)
73 * r3 - 1st arg to board_init(): IMMP pointer
74 * r4 - 2nd arg to board_init(): boot flag
77 .long 0x27051956 /* U-Boot Magic Number */
81 .ascii " (", __DATE__, " - ", __TIME__, ")"
82 .ascii CONFIG_IDENT_STRING, "\0"
87 li r21, BOOTFLAG_COLD /* Normal Power-On: Boot from FLASH */
91 . = EXC_OFF_SYS_RESET + 0x10
95 li r21, BOOTFLAG_WARM /* Software reboot */
99 /* the boot code is located below the exception table */
101 .globl _start_of_vectors
105 STD_EXCEPTION(0x200, MachineCheck, MachineCheckException)
107 /* Data Storage exception. */
108 STD_EXCEPTION(0x300, DataStorage, UnknownException)
110 /* Instruction Storage exception. */
111 STD_EXCEPTION(0x400, InstStorage, UnknownException)
113 /* External Interrupt exception. */
114 STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt)
116 /* Alignment exception. */
124 addi r3,r1,STACK_FRAME_OVERHEAD
126 rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */
127 lwz r6,GOT(transfer_to_handler)
131 .long AlignmentException - _start + EXC_OFF_SYS_RESET
132 .long int_return - _start + EXC_OFF_SYS_RESET
134 /* Program check exception */
138 addi r3,r1,STACK_FRAME_OVERHEAD
140 rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */
141 lwz r6,GOT(transfer_to_handler)
145 .long ProgramCheckException - _start + EXC_OFF_SYS_RESET
146 .long int_return - _start + EXC_OFF_SYS_RESET
148 STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
150 /* I guess we could implement decrementer, and may have
151 * to someday for timekeeping.
153 STD_EXCEPTION(0x900, Decrementer, timer_interrupt)
154 STD_EXCEPTION(0xa00, Trap_0a, UnknownException)
155 STD_EXCEPTION(0xb00, Trap_0b, UnknownException)
156 STD_EXCEPTION(0xc00, SystemCall, UnknownException)
157 STD_EXCEPTION(0xd00, SingleStep, UnknownException)
158 STD_EXCEPTION(0xe00, Trap_0e, UnknownException)
159 STD_EXCEPTION(0xf00, Trap_0f, UnknownException)
160 STD_EXCEPTION(0x1000, SoftEmu, SoftEmuException)
161 STD_EXCEPTION(0x1100, InstructionTLBMiss, UnknownException)
162 STD_EXCEPTION(0x1200, DataTLBMiss, UnknownException)
163 STD_EXCEPTION(0x1300, InstructionTLBError, UnknownException)
164 STD_EXCEPTION(0x1400, DataTLBError, UnknownException)
165 STD_EXCEPTION(0x1500, Reserved5, UnknownException)
166 STD_EXCEPTION(0x1600, Reserved6, UnknownException)
167 STD_EXCEPTION(0x1700, Reserved7, UnknownException)
168 STD_EXCEPTION(0x1800, Reserved8, UnknownException)
169 STD_EXCEPTION(0x1900, Reserved9, UnknownException)
170 STD_EXCEPTION(0x1a00, ReservedA, UnknownException)
171 STD_EXCEPTION(0x1b00, ReservedB, UnknownException)
172 STD_EXCEPTION(0x1c00, DataBreakpoint, UnknownException)
173 STD_EXCEPTION(0x1d00, InstructionBreakpoint, UnknownException)
174 STD_EXCEPTION(0x1e00, PeripheralBreakpoint, UnknownException)
175 STD_EXCEPTION(0x1f00, DevPortBreakpoint, UnknownException)
177 .globl _end_of_vectors
185 /* if this is a multi-core system we need to check which cpu
186 * this is, if it is not cpu 0 send the cpu to the linux reset
188 #if (CONFIG_NUM_CPUS > 1)
191 rlwinm r0,r0,27,31,31
195 bl secondary_cpu_setup
198 /* disable everything */
207 /* init the L2 cache */
208 addis r3, r0, L2_INIT@h
209 ori r3, r3, L2_INIT@l
211 /* invalidate the L2 cache */
212 bl l2cache_invalidate
217 * Calculate absolute address in FLASH and jump there
218 *------------------------------------------------------*/
219 lis r3, CFG_MONITOR_BASE@h
220 ori r3, r3, CFG_MONITOR_BASE@l
221 addi r3, r3, in_flash - _start + EXC_OFF_SYS_RESET
226 /* let the C-code set up the rest */
228 /* Be careful to keep code relocatable ! */
229 /*------------------------------------------------------*/
230 /* perform low-level init */
232 /* enable extended addressing */
239 #if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR)
244 /* Fix for SMP linux - Changing arbitration to round-robin */
245 lis r3, CFG_CCSRBAR@h
251 /* setup the law entries */
255 /* Don't use this feature due to bug in 8641D PD4 */
256 /* Disable ERD_DIS */
257 lis r3, CFG_CCSRBAR@h
264 #if (EMULATOR_RUN == 1)
265 /* On the emulator we want to adjust these ASAP */
266 /* otherwise things are sloooow */
267 /* Setup OR0 (LALE FIX)*/
268 lis r3, CFG_CCSRBAR@h
275 lis r3, CFG_CCSRBAR@h
283 /* make sure timer enabled in guts register too */
284 lis r3, CFG_CCSRBAR@h
294 * Cache must be enabled here for stack-in-cache trick.
295 * This means we need to enable the BATS.
296 * Cache should be turned on after BATs, since by default
297 * everything is write-through.
300 /* enable address translation */
304 /* enable and invalidate the data cache */
305 /* bl l1dcache_enable */
313 #ifdef CFG_INIT_RAM_LOCK
318 /* set up the stack pointer in our newly created
320 lis r1, (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET)@h
321 ori r1, r1, (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET)@l
323 li r0, 0 /* Make room for stack frame header and */
324 stwu r0, -4(r1) /* clear final stack frame so that */
325 stwu r0, -4(r1) /* stack backtraces terminate cleanly */
327 GET_GOT /* initialize GOT access */
329 /* run low-level CPU init code (from Flash) */
335 /* Sri: Code to run the diagnostic automatically */
337 /* Load PX_AUX register address in r4 */
340 /* Load contents of PX_AUX in r3 bits 24 to 31*/
343 /* Mask and obtain the bit in r3 */
344 rlwinm. r3, r3, 0, 24, 24
345 /* If not zero, jump and continue with u-boot */
348 /* Load back contents of PX_AUX in r3 bits 24 to 31 */
350 /* Set the MSB of the register value */
352 /* Write value in r3 back to PX_AUX */
355 /* Get the address to jump to in r3*/
356 lis r3, CFG_DIAG_ADDR@h
357 ori r3, r3, CFG_DIAG_ADDR@l
359 /* Load the LR with the branch address */
362 /* Branch to diagnostic */
368 /* bl l2cache_enable */
372 /* run 1st part of board init code (from Flash) */
378 .globl invalidate_bats
381 /* invalidate BATs */
406 /* setup_bats - set them up to some initial state */
413 addis r4, r0, CFG_IBAT0L@h
414 ori r4, r4, CFG_IBAT0L@l
415 addis r3, r0, CFG_IBAT0U@h
416 ori r3, r3, CFG_IBAT0U@l
422 addis r4, r0, CFG_DBAT0L@h
423 ori r4, r4, CFG_DBAT0L@l
424 addis r3, r0, CFG_DBAT0U@h
425 ori r3, r3, CFG_DBAT0U@l
431 addis r4, r0, CFG_IBAT1L@h
432 ori r4, r4, CFG_IBAT1L@l
433 addis r3, r0, CFG_IBAT1U@h
434 ori r3, r3, CFG_IBAT1U@l
440 addis r4, r0, CFG_DBAT1L@h
441 ori r4, r4, CFG_DBAT1L@l
442 addis r3, r0, CFG_DBAT1U@h
443 ori r3, r3, CFG_DBAT1U@l
449 addis r4, r0, CFG_IBAT2L@h
450 ori r4, r4, CFG_IBAT2L@l
451 addis r3, r0, CFG_IBAT2U@h
452 ori r3, r3, CFG_IBAT2U@l
458 addis r4, r0, CFG_DBAT2L@h
459 ori r4, r4, CFG_DBAT2L@l
460 addis r3, r0, CFG_DBAT2U@h
461 ori r3, r3, CFG_DBAT2U@l
467 addis r4, r0, CFG_IBAT3L@h
468 ori r4, r4, CFG_IBAT3L@l
469 addis r3, r0, CFG_IBAT3U@h
470 ori r3, r3, CFG_IBAT3U@l
476 addis r4, r0, CFG_DBAT3L@h
477 ori r4, r4, CFG_DBAT3L@l
478 addis r3, r0, CFG_DBAT3U@h
479 ori r3, r3, CFG_DBAT3U@l
485 addis r4, r0, CFG_IBAT4L@h
486 ori r4, r4, CFG_IBAT4L@l
487 addis r3, r0, CFG_IBAT4U@h
488 ori r3, r3, CFG_IBAT4U@l
494 addis r4, r0, CFG_DBAT4L@h
495 ori r4, r4, CFG_DBAT4L@l
496 addis r3, r0, CFG_DBAT4U@h
497 ori r3, r3, CFG_DBAT4U@l
503 addis r4, r0, CFG_IBAT5L@h
504 ori r4, r4, CFG_IBAT5L@l
505 addis r3, r0, CFG_IBAT5U@h
506 ori r3, r3, CFG_IBAT5U@l
512 addis r4, r0, CFG_DBAT5L@h
513 ori r4, r4, CFG_DBAT5L@l
514 addis r3, r0, CFG_DBAT5U@h
515 ori r3, r3, CFG_DBAT5U@l
521 addis r4, r0, CFG_IBAT6L@h
522 ori r4, r4, CFG_IBAT6L@l
523 addis r3, r0, CFG_IBAT6U@h
524 ori r3, r3, CFG_IBAT6U@l
530 addis r4, r0, CFG_DBAT6L@h
531 ori r4, r4, CFG_DBAT6L@l
532 addis r3, r0, CFG_DBAT6U@h
533 ori r3, r3, CFG_DBAT6U@l
539 addis r4, r0, CFG_IBAT7L@h
540 ori r4, r4, CFG_IBAT7L@l
541 addis r3, r0, CFG_IBAT7U@h
542 ori r3, r3, CFG_IBAT7U@l
548 addis r4, r0, CFG_DBAT7L@h
549 ori r4, r4, CFG_DBAT7L@l
550 addis r3, r0, CFG_DBAT7U@h
551 ori r3, r3, CFG_DBAT7U@l
558 addis r5, 0, 0x4 /* upper bound of 0x00040000 for 7400/750 */
570 .globl enable_addr_trans
572 /* enable address translation */
574 ori r5, r5, (MSR_IR | MSR_DR)
579 .globl disable_addr_trans
581 /* disable address translation */
584 andi. r0, r3, (MSR_IR | MSR_DR)
592 * This code finishes saving the registers to the exception frame
593 * and jumps to the appropriate handler for the exception.
594 * Register r21 is pointer into trap frame, r1 has new stack pointer.
596 .globl transfer_to_handler
607 andi. r24,r23,0x3f00 /* get vector offset */
611 mtspr SPRG2,r22 /* r1 is now kernel sp */
612 lwz r24,0(r23) /* virtual address of handler */
613 lwz r23,4(r23) /* where to go when done */
618 rfi /* jump to handler, enable MMU */
621 mfmsr r28 /* Disable interrupts */
625 SYNC /* Some chip revs need this... */
640 lwz r2,_NIP(r1) /* Restore environment */
667 * Description: Input 8 bits
676 * Description: Output 8 bits
685 * Description: Output 16 bits
694 * Description: Byte reverse and output 16 bits
703 * Description: Output 32 bits
712 * Description: Byte reverse and output 32 bits
721 * Description: Input 16 bits
730 * Description: Input 16 bits and byte reverse
739 * Description: Input 32 bits
748 * Description: Input 32 bits and byte reverse
757 * Description: Data Cache block flush
758 * Input: r3 = effective address
768 * Description: Data Cache block Invalidate
769 * Input: r3 = effective address
779 * Description: Data Cache block zero.
780 * Input: r3 = effective address
790 * Description: Processor Synchronize
800 * void relocate_code (addr_sp, gd, addr_moni)
802 * This "function" does not return, instead it continues in RAM
803 * after relocating the monitor code.
807 * r5 = length in bytes
813 mr r1, r3 /* Set new stack pointer */
814 mr r9, r4 /* Save copy of Global Data pointer */
815 mr r29, r9 /* Save for DECLARE_GLOBAL_DATA_PTR */
816 mr r10, r5 /* Save copy of Destination Address */
818 mr r3, r5 /* Destination Address */
819 lis r4, CFG_MONITOR_BASE@h /* Source Address */
820 ori r4, r4, CFG_MONITOR_BASE@l
821 lwz r5, GOT(__init_end)
823 li r6, CFG_CACHELINE_SIZE /* Cache Line Size */
828 * New GOT-PTR = (old GOT-PTR - CFG_MONITOR_BASE) + Destination Address
834 /* First our own GOT */
836 /* then the one used by the C code */
843 bl board_relocate_rom
845 mr r3, r10 /* Destination Address */
846 lis r4, CFG_MONITOR_BASE@h /* Source Address */
847 ori r4, r4, CFG_MONITOR_BASE@l
848 lwz r5, GOT(__init_end)
850 li r6, CFG_CACHELINE_SIZE /* Cache Line Size */
855 beq cr1,4f /* In place copy is not necessary */
856 beq 7f /* Protect against 0 count */
875 * Now flush the cache: note that we must start from a cache aligned
876 * address. Otherwise we might miss one cache line.
880 beq 7f /* Always flush prefetch queue in any case */
888 sync /* Wait for all dcbst to complete on bus */
894 7: sync /* Wait for all icbi to complete on bus */
898 * We are done. Do not return, instead branch to second part of board
899 * initialization, now running from RAM.
901 addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET
910 * Relocation Function, r14 point to got2+0x8000
912 * Adjust got2 pointers, no need to check for 0, this code
913 * already puts a few entries in the table.
915 li r0,__got2_entries@sectoff@l
916 la r3,GOT(_GOT2_TABLE_)
917 lwz r11,GOT(_GOT2_TABLE_)
927 * Now adjust the fixups and the pointers to the fixups
928 * in case we need to move ourselves again.
930 2: li r0,__fixup_entries@sectoff@l
931 lwz r3,GOT(_FIXUP_TABLE_)
945 * Now clear BSS segment
947 lwz r3,GOT(__bss_start)
960 mr r3, r9 /* Init Date pointer */
961 mr r4, r10 /* Destination Address */
964 /* not reached - end relocate_code */
965 /*-----------------------------------------------------------------------*/
968 * Copy exception vector code to low memory
971 * r7: source address, r8: end address, r9: target address
976 lwz r8, GOT(_end_of_vectors)
978 li r9, 0x100 /* reset vector always at 0x100 */
981 bgelr /* return if r7>=r8 - just in case */
983 mflr r4 /* save link register */
993 * relocate `hdlr' and `int_return' entries
995 li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET
996 li r8, Alignment - _start + EXC_OFF_SYS_RESET
999 addi r7, r7, 0x100 /* next exception vector */
1003 li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET
1006 li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET
1009 li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET
1010 li r8, SystemCall - _start + EXC_OFF_SYS_RESET
1013 addi r7, r7, 0x100 /* next exception vector */
1017 li r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET
1018 li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET
1021 addi r7, r7, 0x100 /* next exception vector */
1025 /* enable execptions from RAM vectors */
1031 mtlr r4 /* restore link register */
1035 * Function: relocate entries for one exception vector
1038 lwz r0, 0(r7) /* hdlr ... */
1039 add r0, r0, r3 /* ... += dest_addr */
1042 lwz r0, 4(r7) /* int_return ... */
1043 add r0, r0, r3 /* ... += dest_addr */
1051 .globl enable_ext_addr
1054 lis r0, (HID0_HIGH_BAT_EN | HID0_XBSEN | HID0_XAEN)@h
1055 ori r0, r0, (HID0_HIGH_BAT_EN | HID0_XBSEN | HID0_XAEN)@l
1061 #if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR)
1062 .globl setup_ccsrbar
1064 /* Special sequence needed to update CCSRBAR itself */
1065 lis r4, CFG_CCSRBAR_DEFAULT@h
1066 ori r4, r4, CFG_CCSRBAR_DEFAULT@l
1068 lis r5, CFG_CCSRBAR@h
1069 ori r5, r5, CFG_CCSRBAR@l
1079 lis r3, CFG_CCSRBAR@h
1080 lwz r5, CFG_CCSRBAR@l(r3)
1086 #ifdef CFG_INIT_RAM_LOCK
1088 /* Allocate Initial RAM in data cache.
1090 lis r3, (CFG_INIT_RAM_ADDR & ~31)@h
1091 ori r3, r3, (CFG_INIT_RAM_ADDR & ~31)@l
1092 li r2, ((CFG_INIT_RAM_END & ~31) + \
1093 (CFG_INIT_RAM_ADDR & 31) + 31) / 32
1100 /* Lock the data cache */
1109 /* Lock the first way of the data cache */
1112 #if defined(CONFIG_ALTIVEC)
1122 .globl unlock_ram_in_cache
1123 unlock_ram_in_cache:
1124 /* invalidate the INIT_RAM section */
1125 lis r3, (CFG_INIT_RAM_ADDR & ~31)@h
1126 ori r3, r3, (CFG_INIT_RAM_ADDR & ~31)@l
1127 li r2, ((CFG_INIT_RAM_END & ~31) + \
1128 (CFG_INIT_RAM_ADDR & 31) + 31) / 32
1133 sync /* Wait for all icbi to complete on bus */
1136 /* Unlock the data cache and invalidate it */
1148 /* Unlock the first way of the data cache */
1152 #ifdef CONFIG_ALTIVEC
1168 /* If this is a multi-cpu system then we need to handle the
1169 * 2nd cpu. The assumption is that the 2nd cpu is being
1170 * held in boot holdoff mode until the 1st cpu unlocks it
1171 * from Linux. We'll do some basic cpu init and then pass
1172 * it to the Linux Reset Vector.
1173 * Sri: Much of this initialization is not required. Linux
1174 * rewrites the bats, and the sprs and also enables the L1 cache.
1176 #if (CONFIG_NUM_CPUS > 1)
1177 .globl secondary_cpu_setup
1178 secondary_cpu_setup:
1179 /* Do only core setup on all cores except cpu0 */
1185 /* init the L2 cache */
1186 addis r3, r0, L2_INIT@h
1187 ori r3, r3, L2_INIT@l
1190 #ifdef CONFIG_ALTIVEC
1193 /* invalidate the L2 cache */
1194 bl l2cache_invalidate
1198 /* enable and invalidate the data cache */
1202 /* enable and invalidate the instruction cache*/
1213 /*SYNCBE|ABE in HID1*/
1220 lis r3, CONFIG_LINUX_RESET_VEC@h
1221 ori r3, r3, CONFIG_LINUX_RESET_VEC@l
1225 /* Never Returns, Running in Linux Now */