2 * Copyright 2004 Freescale Semiconductor.
3 * Srikanth Srinivasan <srikanth.srinivaan@freescale.com>
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 /* U-Boot - Startup Code for 86xx PowerPC based Embedded Boards
27 * The processor starts at 0xfff00100 and the code is executed
28 * from flash. The code is organized to be at an other address
29 * in memory, but as long we don't jump around before relocating.
30 * board_init lies at a quite high address and when the cpu has
31 * jumped there, everything is ok.
37 #include <ppc_asm.tmpl>
40 #include <asm/cache.h>
43 #ifndef CONFIG_IDENT_STRING
44 #define CONFIG_IDENT_STRING ""
47 /* We don't want the MMU yet.
50 /* Machine Check and Recoverable Interr. */
51 #define MSR_KERNEL ( MSR_ME | MSR_RI )
54 * Set up GOT: Global Offset Table
56 * Use r14 to access the GOT
59 GOT_ENTRY(_GOT2_TABLE_)
60 GOT_ENTRY(_FIXUP_TABLE_)
63 GOT_ENTRY(_start_of_vectors)
64 GOT_ENTRY(_end_of_vectors)
65 GOT_ENTRY(transfer_to_handler)
69 GOT_ENTRY(__bss_start)
73 * r3 - 1st arg to board_init(): IMMP pointer
74 * r4 - 2nd arg to board_init(): boot flag
77 .long 0x27051956 /* U-Boot Magic Number */
81 .ascii " (", __DATE__, " - ", __TIME__, ")"
82 .ascii CONFIG_IDENT_STRING, "\0"
87 li r21, BOOTFLAG_COLD /* Normal Power-On: Boot from FLASH */
91 . = EXC_OFF_SYS_RESET + 0x10
95 li r21, BOOTFLAG_WARM /* Software reboot */
99 /* the boot code is located below the exception table */
101 .globl _start_of_vectors
105 STD_EXCEPTION(0x200, MachineCheck, MachineCheckException)
107 /* Data Storage exception. */
108 STD_EXCEPTION(0x300, DataStorage, UnknownException)
110 /* Instruction Storage exception. */
111 STD_EXCEPTION(0x400, InstStorage, UnknownException)
113 /* External Interrupt exception. */
114 STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt)
116 /* Alignment exception. */
124 addi r3,r1,STACK_FRAME_OVERHEAD
126 rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */
127 lwz r6,GOT(transfer_to_handler)
131 .long AlignmentException - _start + EXC_OFF_SYS_RESET
132 .long int_return - _start + EXC_OFF_SYS_RESET
134 /* Program check exception */
138 addi r3,r1,STACK_FRAME_OVERHEAD
140 rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */
141 lwz r6,GOT(transfer_to_handler)
145 .long ProgramCheckException - _start + EXC_OFF_SYS_RESET
146 .long int_return - _start + EXC_OFF_SYS_RESET
148 STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
150 /* I guess we could implement decrementer, and may have
151 * to someday for timekeeping.
153 STD_EXCEPTION(0x900, Decrementer, timer_interrupt)
154 STD_EXCEPTION(0xa00, Trap_0a, UnknownException)
155 STD_EXCEPTION(0xb00, Trap_0b, UnknownException)
156 STD_EXCEPTION(0xc00, SystemCall, UnknownException)
157 STD_EXCEPTION(0xd00, SingleStep, UnknownException)
158 STD_EXCEPTION(0xe00, Trap_0e, UnknownException)
159 STD_EXCEPTION(0xf00, Trap_0f, UnknownException)
160 STD_EXCEPTION(0x1000, SoftEmu, SoftEmuException)
161 STD_EXCEPTION(0x1100, InstructionTLBMiss, UnknownException)
162 STD_EXCEPTION(0x1200, DataTLBMiss, UnknownException)
163 STD_EXCEPTION(0x1300, InstructionTLBError, UnknownException)
164 STD_EXCEPTION(0x1400, DataTLBError, UnknownException)
165 STD_EXCEPTION(0x1500, Reserved5, UnknownException)
166 STD_EXCEPTION(0x1600, Reserved6, UnknownException)
167 STD_EXCEPTION(0x1700, Reserved7, UnknownException)
168 STD_EXCEPTION(0x1800, Reserved8, UnknownException)
169 STD_EXCEPTION(0x1900, Reserved9, UnknownException)
170 STD_EXCEPTION(0x1a00, ReservedA, UnknownException)
171 STD_EXCEPTION(0x1b00, ReservedB, UnknownException)
172 STD_EXCEPTION(0x1c00, DataBreakpoint, UnknownException)
173 STD_EXCEPTION(0x1d00, InstructionBreakpoint, UnknownException)
174 STD_EXCEPTION(0x1e00, PeripheralBreakpoint, UnknownException)
175 STD_EXCEPTION(0x1f00, DevPortBreakpoint, UnknownException)
177 .globl _end_of_vectors
185 /* if this is a multi-core system we need to check which cpu
186 * this is, if it is not cpu 0 send the cpu to the linux reset
188 #if (CONFIG_NUM_CPUS > 1)
191 rlwinm r0,r0,27,31,31
195 bl secondary_cpu_setup
198 /* disable everything */
207 /* init the L2 cache */
208 addis r3, r0, L2_INIT@h
209 ori r3, r3, L2_INIT@l
211 /* invalidate the L2 cache */
212 bl l2cache_invalidate
217 * Calculate absolute address in FLASH and jump there
218 *------------------------------------------------------*/
219 lis r3, CFG_MONITOR_BASE@h
220 ori r3, r3, CFG_MONITOR_BASE@l
221 addi r3, r3, in_flash - _start + EXC_OFF_SYS_RESET
226 /* let the C-code set up the rest */
228 /* Be careful to keep code relocatable ! */
229 /*------------------------------------------------------*/
230 /* perform low-level init */
232 /* enable extended addressing */
239 #if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR)
245 /* -- MPC8641 Rev 1.0 MCM Errata fixups -- */
247 /* skip fixups if not Rev 1.0 */
254 lwz r4,MCM_ABCR@l(r3) /* ABCR -> r4 */
256 /* set ABCR[A_STRM_CNT] = 0 */
259 /* set ABCR[ARB_POLICY] to 0x1 (round-robin) */
261 rlwimi r4,r0,12,18,19
263 stw r4,MCM_ABCR@l(r3) /* r4 -> ABCR */
266 /* Set DBCR[ERD_DIS] */
268 lwz r4,MCM_DBCR@l(r3)
270 stw r4,MCM_DBCR@l(r3)
273 /* setup the law entries */
278 #if (EMULATOR_RUN == 1)
279 /* On the emulator we want to adjust these ASAP */
280 /* otherwise things are sloooow */
281 /* Setup OR0 (LALE FIX)*/
282 lis r3, CFG_CCSRBAR@h
289 lis r3, CFG_CCSRBAR@h
297 /* make sure timer enabled in guts register too */
298 lis r3, CFG_CCSRBAR@h
308 * Cache must be enabled here for stack-in-cache trick.
309 * This means we need to enable the BATS.
310 * Cache should be turned on after BATs, since by default
311 * everything is write-through.
314 /* enable address translation */
318 /* enable and invalidate the data cache */
319 /* bl l1dcache_enable */
327 #ifdef CFG_INIT_RAM_LOCK
332 /* set up the stack pointer in our newly created
334 lis r1, (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET)@h
335 ori r1, r1, (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET)@l
337 li r0, 0 /* Make room for stack frame header and */
338 stwu r0, -4(r1) /* clear final stack frame so that */
339 stwu r0, -4(r1) /* stack backtraces terminate cleanly */
341 GET_GOT /* initialize GOT access */
343 /* run low-level CPU init code (from Flash) */
349 /* Sri: Code to run the diagnostic automatically */
351 /* Load PX_AUX register address in r4 */
354 /* Load contents of PX_AUX in r3 bits 24 to 31*/
357 /* Mask and obtain the bit in r3 */
358 rlwinm. r3, r3, 0, 24, 24
359 /* If not zero, jump and continue with u-boot */
362 /* Load back contents of PX_AUX in r3 bits 24 to 31 */
364 /* Set the MSB of the register value */
366 /* Write value in r3 back to PX_AUX */
369 /* Get the address to jump to in r3*/
370 lis r3, CFG_DIAG_ADDR@h
371 ori r3, r3, CFG_DIAG_ADDR@l
373 /* Load the LR with the branch address */
376 /* Branch to diagnostic */
382 /* bl l2cache_enable */
386 /* run 1st part of board init code (from Flash) */
392 .globl invalidate_bats
395 /* invalidate BATs */
420 /* setup_bats - set them up to some initial state */
427 addis r4, r0, CFG_IBAT0L@h
428 ori r4, r4, CFG_IBAT0L@l
429 addis r3, r0, CFG_IBAT0U@h
430 ori r3, r3, CFG_IBAT0U@l
436 addis r4, r0, CFG_DBAT0L@h
437 ori r4, r4, CFG_DBAT0L@l
438 addis r3, r0, CFG_DBAT0U@h
439 ori r3, r3, CFG_DBAT0U@l
445 addis r4, r0, CFG_IBAT1L@h
446 ori r4, r4, CFG_IBAT1L@l
447 addis r3, r0, CFG_IBAT1U@h
448 ori r3, r3, CFG_IBAT1U@l
454 addis r4, r0, CFG_DBAT1L@h
455 ori r4, r4, CFG_DBAT1L@l
456 addis r3, r0, CFG_DBAT1U@h
457 ori r3, r3, CFG_DBAT1U@l
463 addis r4, r0, CFG_IBAT2L@h
464 ori r4, r4, CFG_IBAT2L@l
465 addis r3, r0, CFG_IBAT2U@h
466 ori r3, r3, CFG_IBAT2U@l
472 addis r4, r0, CFG_DBAT2L@h
473 ori r4, r4, CFG_DBAT2L@l
474 addis r3, r0, CFG_DBAT2U@h
475 ori r3, r3, CFG_DBAT2U@l
481 addis r4, r0, CFG_IBAT3L@h
482 ori r4, r4, CFG_IBAT3L@l
483 addis r3, r0, CFG_IBAT3U@h
484 ori r3, r3, CFG_IBAT3U@l
490 addis r4, r0, CFG_DBAT3L@h
491 ori r4, r4, CFG_DBAT3L@l
492 addis r3, r0, CFG_DBAT3U@h
493 ori r3, r3, CFG_DBAT3U@l
499 addis r4, r0, CFG_IBAT4L@h
500 ori r4, r4, CFG_IBAT4L@l
501 addis r3, r0, CFG_IBAT4U@h
502 ori r3, r3, CFG_IBAT4U@l
508 addis r4, r0, CFG_DBAT4L@h
509 ori r4, r4, CFG_DBAT4L@l
510 addis r3, r0, CFG_DBAT4U@h
511 ori r3, r3, CFG_DBAT4U@l
517 addis r4, r0, CFG_IBAT5L@h
518 ori r4, r4, CFG_IBAT5L@l
519 addis r3, r0, CFG_IBAT5U@h
520 ori r3, r3, CFG_IBAT5U@l
526 addis r4, r0, CFG_DBAT5L@h
527 ori r4, r4, CFG_DBAT5L@l
528 addis r3, r0, CFG_DBAT5U@h
529 ori r3, r3, CFG_DBAT5U@l
535 addis r4, r0, CFG_IBAT6L@h
536 ori r4, r4, CFG_IBAT6L@l
537 addis r3, r0, CFG_IBAT6U@h
538 ori r3, r3, CFG_IBAT6U@l
544 addis r4, r0, CFG_DBAT6L@h
545 ori r4, r4, CFG_DBAT6L@l
546 addis r3, r0, CFG_DBAT6U@h
547 ori r3, r3, CFG_DBAT6U@l
553 addis r4, r0, CFG_IBAT7L@h
554 ori r4, r4, CFG_IBAT7L@l
555 addis r3, r0, CFG_IBAT7U@h
556 ori r3, r3, CFG_IBAT7U@l
562 addis r4, r0, CFG_DBAT7L@h
563 ori r4, r4, CFG_DBAT7L@l
564 addis r3, r0, CFG_DBAT7U@h
565 ori r3, r3, CFG_DBAT7U@l
572 addis r5, 0, 0x4 /* upper bound of 0x00040000 for 7400/750 */
584 .globl enable_addr_trans
586 /* enable address translation */
588 ori r5, r5, (MSR_IR | MSR_DR)
593 .globl disable_addr_trans
595 /* disable address translation */
598 andi. r0, r3, (MSR_IR | MSR_DR)
606 * This code finishes saving the registers to the exception frame
607 * and jumps to the appropriate handler for the exception.
608 * Register r21 is pointer into trap frame, r1 has new stack pointer.
610 .globl transfer_to_handler
621 andi. r24,r23,0x3f00 /* get vector offset */
625 mtspr SPRG2,r22 /* r1 is now kernel sp */
626 lwz r24,0(r23) /* virtual address of handler */
627 lwz r23,4(r23) /* where to go when done */
632 rfi /* jump to handler, enable MMU */
635 mfmsr r28 /* Disable interrupts */
639 SYNC /* Some chip revs need this... */
654 lwz r2,_NIP(r1) /* Restore environment */
681 * Description: Input 8 bits
690 * Description: Output 8 bits
699 * Description: Output 16 bits
708 * Description: Byte reverse and output 16 bits
717 * Description: Output 32 bits
726 * Description: Byte reverse and output 32 bits
735 * Description: Input 16 bits
744 * Description: Input 16 bits and byte reverse
753 * Description: Input 32 bits
762 * Description: Input 32 bits and byte reverse
771 * Description: Data Cache block flush
772 * Input: r3 = effective address
782 * Description: Data Cache block Invalidate
783 * Input: r3 = effective address
793 * Description: Data Cache block zero.
794 * Input: r3 = effective address
804 * Description: Processor Synchronize
814 * void relocate_code (addr_sp, gd, addr_moni)
816 * This "function" does not return, instead it continues in RAM
817 * after relocating the monitor code.
821 * r5 = length in bytes
827 mr r1, r3 /* Set new stack pointer */
828 mr r9, r4 /* Save copy of Global Data pointer */
829 mr r29, r9 /* Save for DECLARE_GLOBAL_DATA_PTR */
830 mr r10, r5 /* Save copy of Destination Address */
832 mr r3, r5 /* Destination Address */
833 lis r4, CFG_MONITOR_BASE@h /* Source Address */
834 ori r4, r4, CFG_MONITOR_BASE@l
835 lwz r5, GOT(__init_end)
837 li r6, CFG_CACHELINE_SIZE /* Cache Line Size */
842 * New GOT-PTR = (old GOT-PTR - CFG_MONITOR_BASE) + Destination Address
848 /* First our own GOT */
850 /* then the one used by the C code */
857 bl board_relocate_rom
859 mr r3, r10 /* Destination Address */
860 lis r4, CFG_MONITOR_BASE@h /* Source Address */
861 ori r4, r4, CFG_MONITOR_BASE@l
862 lwz r5, GOT(__init_end)
864 li r6, CFG_CACHELINE_SIZE /* Cache Line Size */
869 beq cr1,4f /* In place copy is not necessary */
870 beq 7f /* Protect against 0 count */
889 * Now flush the cache: note that we must start from a cache aligned
890 * address. Otherwise we might miss one cache line.
894 beq 7f /* Always flush prefetch queue in any case */
902 sync /* Wait for all dcbst to complete on bus */
908 7: sync /* Wait for all icbi to complete on bus */
912 * We are done. Do not return, instead branch to second part of board
913 * initialization, now running from RAM.
915 addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET
924 * Relocation Function, r14 point to got2+0x8000
926 * Adjust got2 pointers, no need to check for 0, this code
927 * already puts a few entries in the table.
929 li r0,__got2_entries@sectoff@l
930 la r3,GOT(_GOT2_TABLE_)
931 lwz r11,GOT(_GOT2_TABLE_)
941 * Now adjust the fixups and the pointers to the fixups
942 * in case we need to move ourselves again.
944 2: li r0,__fixup_entries@sectoff@l
945 lwz r3,GOT(_FIXUP_TABLE_)
959 * Now clear BSS segment
961 lwz r3,GOT(__bss_start)
974 mr r3, r9 /* Init Date pointer */
975 mr r4, r10 /* Destination Address */
978 /* not reached - end relocate_code */
979 /*-----------------------------------------------------------------------*/
982 * Copy exception vector code to low memory
985 * r7: source address, r8: end address, r9: target address
990 lwz r8, GOT(_end_of_vectors)
992 li r9, 0x100 /* reset vector always at 0x100 */
995 bgelr /* return if r7>=r8 - just in case */
997 mflr r4 /* save link register */
1007 * relocate `hdlr' and `int_return' entries
1009 li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET
1010 li r8, Alignment - _start + EXC_OFF_SYS_RESET
1013 addi r7, r7, 0x100 /* next exception vector */
1017 li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET
1020 li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET
1023 li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET
1024 li r8, SystemCall - _start + EXC_OFF_SYS_RESET
1027 addi r7, r7, 0x100 /* next exception vector */
1031 li r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET
1032 li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET
1035 addi r7, r7, 0x100 /* next exception vector */
1039 /* enable execptions from RAM vectors */
1045 mtlr r4 /* restore link register */
1049 * Function: relocate entries for one exception vector
1052 lwz r0, 0(r7) /* hdlr ... */
1053 add r0, r0, r3 /* ... += dest_addr */
1056 lwz r0, 4(r7) /* int_return ... */
1057 add r0, r0, r3 /* ... += dest_addr */
1065 .globl enable_ext_addr
1068 lis r0, (HID0_HIGH_BAT_EN | HID0_XBSEN | HID0_XAEN)@h
1069 ori r0, r0, (HID0_HIGH_BAT_EN | HID0_XBSEN | HID0_XAEN)@l
1075 #if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR)
1076 .globl setup_ccsrbar
1078 /* Special sequence needed to update CCSRBAR itself */
1079 lis r4, CFG_CCSRBAR_DEFAULT@h
1080 ori r4, r4, CFG_CCSRBAR_DEFAULT@l
1082 lis r5, CFG_CCSRBAR@h
1083 ori r5, r5, CFG_CCSRBAR@l
1093 lis r3, CFG_CCSRBAR@h
1094 lwz r5, CFG_CCSRBAR@l(r3)
1100 #ifdef CFG_INIT_RAM_LOCK
1102 /* Allocate Initial RAM in data cache.
1104 lis r3, (CFG_INIT_RAM_ADDR & ~31)@h
1105 ori r3, r3, (CFG_INIT_RAM_ADDR & ~31)@l
1106 li r2, ((CFG_INIT_RAM_END & ~31) + \
1107 (CFG_INIT_RAM_ADDR & 31) + 31) / 32
1114 /* Lock the data cache */
1123 /* Lock the first way of the data cache */
1126 #if defined(CONFIG_ALTIVEC)
1136 .globl unlock_ram_in_cache
1137 unlock_ram_in_cache:
1138 /* invalidate the INIT_RAM section */
1139 lis r3, (CFG_INIT_RAM_ADDR & ~31)@h
1140 ori r3, r3, (CFG_INIT_RAM_ADDR & ~31)@l
1141 li r2, ((CFG_INIT_RAM_END & ~31) + \
1142 (CFG_INIT_RAM_ADDR & 31) + 31) / 32
1147 sync /* Wait for all icbi to complete on bus */
1150 /* Unlock the data cache and invalidate it */
1162 /* Unlock the first way of the data cache */
1166 #ifdef CONFIG_ALTIVEC
1182 /* If this is a multi-cpu system then we need to handle the
1183 * 2nd cpu. The assumption is that the 2nd cpu is being
1184 * held in boot holdoff mode until the 1st cpu unlocks it
1185 * from Linux. We'll do some basic cpu init and then pass
1186 * it to the Linux Reset Vector.
1187 * Sri: Much of this initialization is not required. Linux
1188 * rewrites the bats, and the sprs and also enables the L1 cache.
1190 #if (CONFIG_NUM_CPUS > 1)
1191 .globl secondary_cpu_setup
1192 secondary_cpu_setup:
1193 /* Do only core setup on all cores except cpu0 */
1199 /* init the L2 cache */
1200 addis r3, r0, L2_INIT@h
1201 ori r3, r3, L2_INIT@l
1204 #ifdef CONFIG_ALTIVEC
1207 /* invalidate the L2 cache */
1208 bl l2cache_invalidate
1212 /* enable and invalidate the data cache */
1216 /* enable and invalidate the instruction cache*/
1227 /*SYNCBE|ABE in HID1*/
1234 lis r3, CONFIG_LINUX_RESET_VEC@h
1235 ori r3, r3, CONFIG_LINUX_RESET_VEC@l
1239 /* Never Returns, Running in Linux Now */