2 * Copyright 2004, 2007 Freescale Semiconductor.
3 * Srikanth Srinivasan <srikanth.srinivaan@freescale.com>
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 /* U-Boot - Startup Code for 86xx PowerPC based Embedded Boards
27 * The processor starts at 0xfff00100 and the code is executed
28 * from flash. The code is organized to be at an other address
29 * in memory, but as long we don't jump around before relocating.
30 * board_init lies at a quite high address and when the cpu has
31 * jumped there, everything is ok.
37 #include <ppc_asm.tmpl>
40 #include <asm/cache.h>
43 #ifndef CONFIG_IDENT_STRING
44 #define CONFIG_IDENT_STRING ""
48 * Need MSR_DR | MSR_IR enabled to access I/O (printf) in exceptions
52 * Set up GOT: Global Offset Table
54 * Use r14 to access the GOT
57 GOT_ENTRY(_GOT2_TABLE_)
58 GOT_ENTRY(_FIXUP_TABLE_)
61 GOT_ENTRY(_start_of_vectors)
62 GOT_ENTRY(_end_of_vectors)
63 GOT_ENTRY(transfer_to_handler)
67 GOT_ENTRY(__bss_start)
71 * r3 - 1st arg to board_init(): IMMP pointer
72 * r4 - 2nd arg to board_init(): boot flag
75 .long 0x27051956 /* U-Boot Magic Number */
79 .ascii " (", __DATE__, " - ", __TIME__, ")"
80 .ascii CONFIG_IDENT_STRING, "\0"
85 li r21, BOOTFLAG_COLD /* Normal Power-On: Boot from FLASH */
89 . = EXC_OFF_SYS_RESET + 0x10
93 li r21, BOOTFLAG_WARM /* Software reboot */
97 /* the boot code is located below the exception table */
99 .globl _start_of_vectors
103 STD_EXCEPTION(0x200, MachineCheck, MachineCheckException)
105 /* Data Storage exception. */
106 STD_EXCEPTION(0x300, DataStorage, UnknownException)
108 /* Instruction Storage exception. */
109 STD_EXCEPTION(0x400, InstStorage, UnknownException)
111 /* External Interrupt exception. */
112 STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt)
114 /* Alignment exception. */
117 EXCEPTION_PROLOG(SRR0, SRR1)
122 addi r3,r1,STACK_FRAME_OVERHEAD
124 rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */
125 lwz r6,GOT(transfer_to_handler)
129 .long AlignmentException - _start + EXC_OFF_SYS_RESET
130 .long int_return - _start + EXC_OFF_SYS_RESET
132 /* Program check exception */
135 EXCEPTION_PROLOG(SRR0, SRR1)
136 addi r3,r1,STACK_FRAME_OVERHEAD
138 rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */
139 lwz r6,GOT(transfer_to_handler)
143 .long ProgramCheckException - _start + EXC_OFF_SYS_RESET
144 .long int_return - _start + EXC_OFF_SYS_RESET
146 STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
148 /* I guess we could implement decrementer, and may have
149 * to someday for timekeeping.
151 STD_EXCEPTION(0x900, Decrementer, timer_interrupt)
152 STD_EXCEPTION(0xa00, Trap_0a, UnknownException)
153 STD_EXCEPTION(0xb00, Trap_0b, UnknownException)
154 STD_EXCEPTION(0xc00, SystemCall, UnknownException)
155 STD_EXCEPTION(0xd00, SingleStep, UnknownException)
156 STD_EXCEPTION(0xe00, Trap_0e, UnknownException)
157 STD_EXCEPTION(0xf00, Trap_0f, UnknownException)
158 STD_EXCEPTION(0x1000, SoftEmu, SoftEmuException)
159 STD_EXCEPTION(0x1100, InstructionTLBMiss, UnknownException)
160 STD_EXCEPTION(0x1200, DataTLBMiss, UnknownException)
161 STD_EXCEPTION(0x1300, InstructionTLBError, UnknownException)
162 STD_EXCEPTION(0x1400, DataTLBError, UnknownException)
163 STD_EXCEPTION(0x1500, Reserved5, UnknownException)
164 STD_EXCEPTION(0x1600, Reserved6, UnknownException)
165 STD_EXCEPTION(0x1700, Reserved7, UnknownException)
166 STD_EXCEPTION(0x1800, Reserved8, UnknownException)
167 STD_EXCEPTION(0x1900, Reserved9, UnknownException)
168 STD_EXCEPTION(0x1a00, ReservedA, UnknownException)
169 STD_EXCEPTION(0x1b00, ReservedB, UnknownException)
170 STD_EXCEPTION(0x1c00, DataBreakpoint, UnknownException)
171 STD_EXCEPTION(0x1d00, InstructionBreakpoint, UnknownException)
172 STD_EXCEPTION(0x1e00, PeripheralBreakpoint, UnknownException)
173 STD_EXCEPTION(0x1f00, DevPortBreakpoint, UnknownException)
175 .globl _end_of_vectors
183 /* if this is a multi-core system we need to check which cpu
184 * this is, if it is not cpu 0 send the cpu to the linux reset
186 #if (CONFIG_NUM_CPUS > 1)
189 rlwinm r0,r0,27,31,31
193 bl secondary_cpu_setup
198 /* disable everything */
209 /* init the L2 cache */
211 ori r3, r3, L2_INIT@l
213 /* invalidate the L2 cache */
214 bl l2cache_invalidate
219 * Calculate absolute address in FLASH and jump there
220 *------------------------------------------------------*/
221 lis r3, CFG_MONITOR_BASE@h
222 ori r3, r3, CFG_MONITOR_BASE@l
223 addi r3, r3, in_flash - _start + EXC_OFF_SYS_RESET
228 /* let the C-code set up the rest */
230 /* Be careful to keep code relocatable ! */
231 /*------------------------------------------------------*/
232 /* perform low-level init */
234 /* enable extended addressing */
241 #if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR)
246 /* setup the law entries */
250 * Cache must be enabled here for stack-in-cache trick.
251 * This means we need to enable the BATS.
252 * Cache should be turned on after BATs, since by default
253 * everything is write-through.
256 /* enable address translation */
260 /* enable and invalidate the data cache */
261 /* bl l1dcache_enable */
269 #ifdef CFG_INIT_RAM_LOCK
274 /* set up the stack pointer in our newly created
276 lis r1, (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET)@h
277 ori r1, r1, (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET)@l
279 li r0, 0 /* Make room for stack frame header and */
280 stwu r0, -4(r1) /* clear final stack frame so that */
281 stwu r0, -4(r1) /* stack backtraces terminate cleanly */
283 GET_GOT /* initialize GOT access */
285 /* run low-level CPU init code (from Flash) */
291 /* Load PX_AUX register address in r4 */
294 /* Load contents of PX_AUX in r3 bits 24 to 31*/
297 /* Mask and obtain the bit in r3 */
298 rlwinm. r3, r3, 0, 24, 24
299 /* If not zero, jump and continue with u-boot */
302 /* Load back contents of PX_AUX in r3 bits 24 to 31 */
304 /* Set the MSB of the register value */
306 /* Write value in r3 back to PX_AUX */
309 /* Get the address to jump to in r3*/
310 lis r3, CFG_DIAG_ADDR@h
311 ori r3, r3, CFG_DIAG_ADDR@l
313 /* Load the LR with the branch address */
316 /* Branch to diagnostic */
322 /* bl l2cache_enable */
326 /* run 1st part of board init code (from Flash) */
332 .globl invalidate_bats
336 /* invalidate BATs */
361 /* setup_bats - set them up to some initial state */
368 addis r4, r0, CFG_IBAT0L@h
369 ori r4, r4, CFG_IBAT0L@l
370 addis r3, r0, CFG_IBAT0U@h
371 ori r3, r3, CFG_IBAT0U@l
377 addis r4, r0, CFG_DBAT0L@h
378 ori r4, r4, CFG_DBAT0L@l
379 addis r3, r0, CFG_DBAT0U@h
380 ori r3, r3, CFG_DBAT0U@l
386 addis r4, r0, CFG_IBAT1L@h
387 ori r4, r4, CFG_IBAT1L@l
388 addis r3, r0, CFG_IBAT1U@h
389 ori r3, r3, CFG_IBAT1U@l
395 addis r4, r0, CFG_DBAT1L@h
396 ori r4, r4, CFG_DBAT1L@l
397 addis r3, r0, CFG_DBAT1U@h
398 ori r3, r3, CFG_DBAT1U@l
404 addis r4, r0, CFG_IBAT2L@h
405 ori r4, r4, CFG_IBAT2L@l
406 addis r3, r0, CFG_IBAT2U@h
407 ori r3, r3, CFG_IBAT2U@l
413 addis r4, r0, CFG_DBAT2L@h
414 ori r4, r4, CFG_DBAT2L@l
415 addis r3, r0, CFG_DBAT2U@h
416 ori r3, r3, CFG_DBAT2U@l
422 addis r4, r0, CFG_IBAT3L@h
423 ori r4, r4, CFG_IBAT3L@l
424 addis r3, r0, CFG_IBAT3U@h
425 ori r3, r3, CFG_IBAT3U@l
431 addis r4, r0, CFG_DBAT3L@h
432 ori r4, r4, CFG_DBAT3L@l
433 addis r3, r0, CFG_DBAT3U@h
434 ori r3, r3, CFG_DBAT3U@l
440 addis r4, r0, CFG_IBAT4L@h
441 ori r4, r4, CFG_IBAT4L@l
442 addis r3, r0, CFG_IBAT4U@h
443 ori r3, r3, CFG_IBAT4U@l
449 addis r4, r0, CFG_DBAT4L@h
450 ori r4, r4, CFG_DBAT4L@l
451 addis r3, r0, CFG_DBAT4U@h
452 ori r3, r3, CFG_DBAT4U@l
458 addis r4, r0, CFG_IBAT5L@h
459 ori r4, r4, CFG_IBAT5L@l
460 addis r3, r0, CFG_IBAT5U@h
461 ori r3, r3, CFG_IBAT5U@l
467 addis r4, r0, CFG_DBAT5L@h
468 ori r4, r4, CFG_DBAT5L@l
469 addis r3, r0, CFG_DBAT5U@h
470 ori r3, r3, CFG_DBAT5U@l
476 addis r4, r0, CFG_IBAT6L@h
477 ori r4, r4, CFG_IBAT6L@l
478 addis r3, r0, CFG_IBAT6U@h
479 ori r3, r3, CFG_IBAT6U@l
485 addis r4, r0, CFG_DBAT6L@h
486 ori r4, r4, CFG_DBAT6L@l
487 addis r3, r0, CFG_DBAT6U@h
488 ori r3, r3, CFG_DBAT6U@l
494 addis r4, r0, CFG_IBAT7L@h
495 ori r4, r4, CFG_IBAT7L@l
496 addis r3, r0, CFG_IBAT7U@h
497 ori r3, r3, CFG_IBAT7U@l
503 addis r4, r0, CFG_DBAT7L@h
504 ori r4, r4, CFG_DBAT7L@l
505 addis r3, r0, CFG_DBAT7U@h
506 ori r3, r3, CFG_DBAT7U@l
513 addis r5, 0, 0x4 /* upper bound of 0x00040000 for 7400/750 */
525 .globl enable_addr_trans
527 /* enable address translation */
529 ori r5, r5, (MSR_IR | MSR_DR)
534 .globl disable_addr_trans
536 /* disable address translation */
539 andi. r0, r3, (MSR_IR | MSR_DR)
547 * This code finishes saving the registers to the exception frame
548 * and jumps to the appropriate handler for the exception.
549 * Register r21 is pointer into trap frame, r1 has new stack pointer.
551 .globl transfer_to_handler
562 andi. r24,r23,0x3f00 /* get vector offset */
566 mtspr SPRG2,r22 /* r1 is now kernel sp */
567 lwz r24,0(r23) /* virtual address of handler */
568 lwz r23,4(r23) /* where to go when done */
573 rfi /* jump to handler, enable MMU */
576 mfmsr r28 /* Disable interrupts */
580 SYNC /* Some chip revs need this... */
595 lwz r2,_NIP(r1) /* Restore environment */
622 * Description: Input 8 bits
631 * Description: Output 8 bits
640 * Description: Output 16 bits
649 * Description: Byte reverse and output 16 bits
658 * Description: Output 32 bits
667 * Description: Byte reverse and output 32 bits
676 * Description: Input 16 bits
685 * Description: Input 16 bits and byte reverse
694 * Description: Input 32 bits
703 * Description: Input 32 bits and byte reverse
712 * Description: Data Cache block flush
713 * Input: r3 = effective address
723 * Description: Data Cache block Invalidate
724 * Input: r3 = effective address
734 * Description: Data Cache block zero.
735 * Input: r3 = effective address
745 * Description: Processor Synchronize
755 * void relocate_code (addr_sp, gd, addr_moni)
757 * This "function" does not return, instead it continues in RAM
758 * after relocating the monitor code.
762 * r5 = length in bytes
768 mr r1, r3 /* Set new stack pointer */
769 mr r9, r4 /* Save copy of Global Data pointer */
770 mr r29, r9 /* Save for DECLARE_GLOBAL_DATA_PTR */
771 mr r10, r5 /* Save copy of Destination Address */
773 mr r3, r5 /* Destination Address */
774 lis r4, CFG_MONITOR_BASE@h /* Source Address */
775 ori r4, r4, CFG_MONITOR_BASE@l
776 lwz r5, GOT(__init_end)
778 li r6, CFG_CACHELINE_SIZE /* Cache Line Size */
783 * New GOT-PTR = (old GOT-PTR - CFG_MONITOR_BASE) + Destination Address
789 /* First our own GOT */
791 /* then the one used by the C code */
798 bl board_relocate_rom
800 mr r3, r10 /* Destination Address */
801 lis r4, CFG_MONITOR_BASE@h /* Source Address */
802 ori r4, r4, CFG_MONITOR_BASE@l
803 lwz r5, GOT(__init_end)
805 li r6, CFG_CACHELINE_SIZE /* Cache Line Size */
810 beq cr1,4f /* In place copy is not necessary */
811 beq 7f /* Protect against 0 count */
830 * Now flush the cache: note that we must start from a cache aligned
831 * address. Otherwise we might miss one cache line.
835 beq 7f /* Always flush prefetch queue in any case */
843 sync /* Wait for all dcbst to complete on bus */
849 7: sync /* Wait for all icbi to complete on bus */
853 * We are done. Do not return, instead branch to second part of board
854 * initialization, now running from RAM.
856 addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET
865 * Relocation Function, r14 point to got2+0x8000
867 * Adjust got2 pointers, no need to check for 0, this code
868 * already puts a few entries in the table.
870 li r0,__got2_entries@sectoff@l
871 la r3,GOT(_GOT2_TABLE_)
872 lwz r11,GOT(_GOT2_TABLE_)
882 * Now adjust the fixups and the pointers to the fixups
883 * in case we need to move ourselves again.
885 2: li r0,__fixup_entries@sectoff@l
886 lwz r3,GOT(_FIXUP_TABLE_)
900 * Now clear BSS segment
902 lwz r3,GOT(__bss_start)
915 mr r3, r9 /* Init Date pointer */
916 mr r4, r10 /* Destination Address */
919 /* not reached - end relocate_code */
920 /*-----------------------------------------------------------------------*/
923 * Copy exception vector code to low memory
926 * r7: source address, r8: end address, r9: target address
931 lwz r8, GOT(_end_of_vectors)
933 li r9, 0x100 /* reset vector always at 0x100 */
936 bgelr /* return if r7>=r8 - just in case */
938 mflr r4 /* save link register */
948 * relocate `hdlr' and `int_return' entries
950 li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET
951 li r8, Alignment - _start + EXC_OFF_SYS_RESET
954 addi r7, r7, 0x100 /* next exception vector */
958 li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET
961 li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET
964 li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET
965 li r8, SystemCall - _start + EXC_OFF_SYS_RESET
968 addi r7, r7, 0x100 /* next exception vector */
972 li r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET
973 li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET
976 addi r7, r7, 0x100 /* next exception vector */
980 /* enable execptions from RAM vectors */
984 ori r7,r7,MSR_ME /* Enable Machine Check */
987 mtlr r4 /* restore link register */
991 * Function: relocate entries for one exception vector
994 lwz r0, 0(r7) /* hdlr ... */
995 add r0, r0, r3 /* ... += dest_addr */
998 lwz r0, 4(r7) /* int_return ... */
999 add r0, r0, r3 /* ... += dest_addr */
1007 .globl enable_ext_addr
1010 lis r0, (HID0_HIGH_BAT_EN | HID0_XBSEN | HID0_XAEN)@h
1011 ori r0, r0, (HID0_HIGH_BAT_EN | HID0_XBSEN | HID0_XAEN)@l
1017 #if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR)
1018 .globl setup_ccsrbar
1020 /* Special sequence needed to update CCSRBAR itself */
1021 lis r4, CFG_CCSRBAR_DEFAULT@h
1022 ori r4, r4, CFG_CCSRBAR_DEFAULT@l
1024 lis r5, CFG_CCSRBAR@h
1025 ori r5, r5, CFG_CCSRBAR@l
1035 lis r3, CFG_CCSRBAR@h
1036 lwz r5, CFG_CCSRBAR@l(r3)
1042 #ifdef CFG_INIT_RAM_LOCK
1044 /* Allocate Initial RAM in data cache.
1046 lis r3, (CFG_INIT_RAM_ADDR & ~31)@h
1047 ori r3, r3, (CFG_INIT_RAM_ADDR & ~31)@l
1048 li r2, ((CFG_INIT_RAM_END & ~31) + \
1049 (CFG_INIT_RAM_ADDR & 31) + 31) / 32
1056 /* Lock the data cache */
1065 /* Lock the first way of the data cache */
1068 #if defined(CONFIG_ALTIVEC)
1078 .globl unlock_ram_in_cache
1079 unlock_ram_in_cache:
1080 /* invalidate the INIT_RAM section */
1081 lis r3, (CFG_INIT_RAM_ADDR & ~31)@h
1082 ori r3, r3, (CFG_INIT_RAM_ADDR & ~31)@l
1083 li r2, ((CFG_INIT_RAM_END & ~31) + \
1084 (CFG_INIT_RAM_ADDR & 31) + 31) / 32
1089 sync /* Wait for all icbi to complete on bus */
1092 /* Unlock the data cache and invalidate it */
1104 /* Unlock the first way of the data cache */
1108 #ifdef CONFIG_ALTIVEC
1124 /* If this is a multi-cpu system then we need to handle the
1125 * 2nd cpu. The assumption is that the 2nd cpu is being
1126 * held in boot holdoff mode until the 1st cpu unlocks it
1127 * from Linux. We'll do some basic cpu init and then pass
1128 * it to the Linux Reset Vector.
1129 * Sri: Much of this initialization is not required. Linux
1130 * rewrites the bats, and the sprs and also enables the L1 cache.
1132 #if (CONFIG_NUM_CPUS > 1)
1133 .globl secondary_cpu_setup
1134 secondary_cpu_setup:
1135 /* Do only core setup on all cores except cpu0 */
1141 /* init the L2 cache */
1142 addis r3, r0, L2_INIT@h
1143 ori r3, r3, L2_INIT@l
1146 #ifdef CONFIG_ALTIVEC
1149 /* invalidate the L2 cache */
1150 bl l2cache_invalidate
1154 /* enable and invalidate the data cache */
1158 /* enable and invalidate the instruction cache*/
1169 /* MCP|SYNCBE|ABE in HID1 */
1177 lis r3, CONFIG_LINUX_RESET_VEC@h
1178 ori r3, r3, CONFIG_LINUX_RESET_VEC@l
1182 /* Never Returns, Running in Linux Now */