2 * Copyright 2004 Freescale Semiconductor.
3 * (C) Copyright 2003 Motorola Inc.
4 * Xianghua Xiao (X.Xiao@motorola.com)
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <asm/processor.h>
32 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
33 extern void dma_init(void);
34 extern uint dma_check(void);
35 extern int dma_xfer(void *dest, uint count, void *src);
38 #ifdef CONFIG_SPD_EEPROM
41 #define CFG_READ_SPD i2c_read
45 * Only one of the following three should be 1; others should be 0
46 * By default the cache line interleaving is selected if
47 * the CONFIG_DDR_INTERLEAVE flag is defined
49 #define CFG_PAGE_INTERLEAVING 0
50 #define CFG_BANK_INTERLEAVING 0
51 #define CFG_SUPER_BANK_INTERLEAVING 0
54 * Convert picoseconds into clock cycles (rounding up if needed).
58 picos_to_clk(int picos)
62 clks = picos / (2000000000 / (get_bus_freq(0) / 1000));
63 if (picos % (2000000000 / (get_bus_freq(0) / 1000)) != 0) {
72 * Calculate the Density of each Physical Rank.
73 * Returned size is in bytes.
75 * Study these table from Byte 31 of JEDEC SPD Spec.
89 * Reorder Table to be linear by stripping the bottom
90 * 2 or 5 bits off and shifting them up to the top.
94 compute_banksize(unsigned int mem_type, unsigned char row_dens)
98 if (mem_type == SPD_MEMTYPE_DDR) {
99 /* Bottom 2 bits up to the top. */
100 bsize = ((row_dens >> 2) | ((row_dens & 3) << 6)) << 24;
101 debug("DDR: DDR I rank density = 0x%08x\n", bsize);
103 /* Bottom 5 bits up to the top. */
104 bsize = ((row_dens >> 5) | ((row_dens & 31) << 3)) << 27;
105 debug("DDR: DDR II rank density = 0x%08x\n", bsize);
112 * Convert a two-nibble BCD value into a cycle time.
113 * While the spec calls for nano-seconds, picos are returned.
115 * This implements the tables for bytes 9, 23 and 25 for both
116 * DDR I and II. No allowance for distinguishing the invalid
117 * fields absent for DDR I yet present in DDR II is made.
118 * (That is, cycle times of .25, .33, .66 and .75 ns are
119 * allowed for both DDR II and I.)
123 convert_bcd_tenths_to_cycle_time_ps(unsigned int spd_val)
126 * Table look up the lower nibble, allow DDR I & II.
128 unsigned int tenths_ps[16] = {
147 unsigned int whole_ns = (spd_val & 0xF0) >> 4;
148 unsigned int tenth_ns = spd_val & 0x0F;
149 unsigned int ps = whole_ns * 1000 + tenths_ps[tenth_ns];
156 * Determine Refresh Rate. Ignore self refresh bit on DDR I.
157 * Table from SPD Spec, Byte 12, converted to picoseconds and
158 * filled in with "default" normal values.
160 unsigned int determine_refresh_rate(unsigned int spd_refresh)
162 unsigned int refresh_time_ns[8] = {
163 15625000, /* 0 Normal 1.00x */
164 3900000, /* 1 Reduced .25x */
165 7800000, /* 2 Extended .50x */
166 31300000, /* 3 Extended 2.00x */
167 62500000, /* 4 Extended 4.00x */
168 125000000, /* 5 Extended 8.00x */
169 15625000, /* 6 Normal 1.00x filler */
170 15625000, /* 7 Normal 1.00x filler */
173 return picos_to_clk(refresh_time_ns[spd_refresh & 0x7]);
178 spd_init(unsigned char i2c_address, unsigned int ddr_num,
179 unsigned int dimm_num, unsigned int start_addr)
181 volatile immap_t *immap = (immap_t *)CFG_IMMR;
182 volatile ccsr_ddr_t *ddr;
183 volatile ccsr_gur_t *gur = &immap->im_gur;
185 unsigned int n_ranks;
186 unsigned int rank_density;
187 unsigned int odt_rd_cfg, odt_wr_cfg;
188 unsigned int odt_cfg, mode_odt_enable;
189 unsigned int refresh_clk;
190 #ifdef MPC86xx_DDR_SDRAM_CLK_CNTL
191 unsigned char clk_adjust;
193 unsigned int dqs_cfg;
194 unsigned char twr_clk, twtr_clk, twr_auto_clk;
195 unsigned int tCKmin_ps, tCKmax_ps;
196 unsigned int max_data_rate;
197 unsigned int busfreq;
198 unsigned sdram_cfg_1;
199 unsigned int memsize;
200 unsigned char caslat, caslat_ctrl;
201 unsigned int trfc, trfc_clk, trfc_low, trfc_high;
202 unsigned int trcd_clk;
203 unsigned int trtp_clk;
204 unsigned char cke_min_clk;
205 unsigned char add_lat;
206 unsigned char wr_lat;
207 unsigned char wr_data_delay;
208 unsigned char four_act;
210 unsigned char burst_len;
211 unsigned int mode_caslat;
212 unsigned char sdram_type;
213 unsigned char d_init;
214 unsigned int law_size;
215 volatile ccsr_local_mcm_t *mcm = &immap->im_local_mcm;
216 unsigned int tCycle_ps, modfreq;
219 ddr = &immap->im_ddr1;
221 ddr = &immap->im_ddr2;
224 * Read SPD information.
226 debug("Performing SPD read at I2C address 0x%02lx\n",i2c_address);
227 memset((void *)&spd, 0, sizeof(spd));
228 CFG_READ_SPD(i2c_address, 0, 1, (uchar *) &spd, sizeof(spd));
231 * Check for supported memory module types.
233 if (spd.mem_type != SPD_MEMTYPE_DDR &&
234 spd.mem_type != SPD_MEMTYPE_DDR2) {
235 debug("Warning: Unable to locate DDR I or DDR II module for DIMM %d of DDR controller %d.\n"
236 " Fundamental memory type is 0x%0x\n",
243 debug("\nFound memory of type 0x%02lx ", spd.mem_type);
244 if (spd.mem_type == SPD_MEMTYPE_DDR)
250 * These test gloss over DDR I and II differences in interpretation
251 * of bytes 3 and 4, but irrelevantly. Multiple asymmetric banks
252 * are not supported on DDR I; and not encoded on DDR II.
254 * Also note that the 8548 controller can support:
257 * 8 <= ncol <= 11 (still, for DDR)
258 * 6 <= ncol <= 9 (for FCRAM)
260 if (spd.nrow_addr < 12 || spd.nrow_addr > 14) {
261 printf("DDR: Unsupported number of Row Addr lines: %d.\n",
265 if (spd.ncol_addr < 8 || spd.ncol_addr > 11) {
266 printf("DDR: Unsupported number of Column Addr lines: %d.\n",
272 * Determine the number of physical banks controlled by
273 * different Chip Select signals. This is not quite the
274 * same as the number of DIMM modules on the board. Feh.
276 if (spd.mem_type == SPD_MEMTYPE_DDR) {
279 n_ranks = (spd.nrows & 0x7) + 1;
282 debug("DDR: number of ranks = %d\n", n_ranks);
285 printf("DDR: Only 2 chip selects are supported: %d\n",
291 * Adjust DDR II IO voltage biasing. It just makes it work.
293 if (spd.mem_type == SPD_MEMTYPE_DDR2) {
295 | 0x80000000 /* Enable */
296 | 0x10000000 /* VSEL to 1.8V */
301 * Determine the size of each Rank in bytes.
303 rank_density = compute_banksize(spd.mem_type, spd.row_dens);
305 debug("Start address for this controller is 0x%08lx\n", start_addr);
308 * ODT configuration recommendation from DDR Controller Chapter.
310 odt_rd_cfg = 0; /* Never assert ODT */
311 odt_wr_cfg = 0; /* Never assert ODT */
312 if (spd.mem_type == SPD_MEMTYPE_DDR2) {
313 odt_wr_cfg = 1; /* Assert ODT on writes to CS0 */
316 #ifdef CONFIG_DDR_INTERLEAVE
319 printf("For interleaving memory on HPCN, need to use DIMM 1 for DDR Controller %d !\n", ddr_num);
323 * Since interleaved memory only uses CS0, the
324 * memory sticks have to be identical in size and quantity
325 * of ranks. That essentially gives double the size on
326 * one rank, i.e on CS0 for both controllers put together.
332 * Eg: Bounds: 0x0000_0000 to 0x0f000_0000 first 256 Meg
335 ddr->cs0_bnds = (start_addr >> 8)
336 | (((start_addr + rank_density - 1) >> 24));
338 * Default interleaving mode to cache-line interleaving.
340 ddr->cs0_config = ( 1 << 31
341 #if (CFG_PAGE_INTERLEAVING == 1)
342 | (PAGE_INTERLEAVING)
343 #elif (CFG_BANK_INTERLEAVING == 1)
344 | (BANK_INTERLEAVING)
345 #elif (CFG_SUPER_BANK_INTERLEAVING == 1)
346 | (SUPER_BANK_INTERLEAVING)
348 | (CACHE_LINE_INTERLEAVING)
352 | (spd.nrow_addr - 12) << 8
353 | (spd.ncol_addr - 8) );
355 debug("DDR: cs0_bnds = 0x%08x\n", ddr->cs0_bnds);
356 debug("DDR: cs0_config = 0x%08x\n", ddr->cs0_config);
359 * Adjustment for dual rank memory to get correct memory
360 * size (return value of this function).
369 #else /* CONFIG_DDR_INTERLEAVE */
373 * Eg: Bounds: 0x0000_0000 to 0x0f000_0000 first 256 Meg
375 ddr->cs0_bnds = (start_addr >> 8)
376 | (((start_addr + rank_density - 1) >> 24));
378 ddr->cs0_config = ( 1 << 31
381 | (spd.nrow_addr - 12) << 8
382 | (spd.ncol_addr - 8) );
384 debug("DDR: cs0_bnds = 0x%08x\n", ddr->cs0_bnds);
385 debug("DDR: cs0_config = 0x%08x\n", ddr->cs0_config);
389 * Eg: Bounds: 0x1000_0000 to 0x1f00_0000,
392 ddr->cs1_bnds = (((start_addr + rank_density) >> 8)
393 | (( start_addr + 2*rank_density - 1)
395 ddr->cs1_config = ( 1<<31
398 | (spd.nrow_addr - 12) << 8
399 | (spd.ncol_addr - 8) );
400 debug("DDR: cs1_bnds = 0x%08x\n", ddr->cs1_bnds);
401 debug("DDR: cs1_config = 0x%08x\n", ddr->cs1_config);
406 * This is the 2nd DIMM slot for this controller
409 * Eg: Bounds: 0x0000_0000 to 0x0f000_0000 first 256 Meg
411 ddr->cs2_bnds = (start_addr >> 8)
412 | (((start_addr + rank_density - 1) >> 24));
414 ddr->cs2_config = ( 1 << 31
417 | (spd.nrow_addr - 12) << 8
418 | (spd.ncol_addr - 8) );
420 debug("DDR: cs2_bnds = 0x%08x\n", ddr->cs2_bnds);
421 debug("DDR: cs2_config = 0x%08x\n", ddr->cs2_config);
425 * Eg: Bounds: 0x1000_0000 to 0x1f00_0000,
428 ddr->cs3_bnds = (((start_addr + rank_density) >> 8)
429 | (( start_addr + 2*rank_density - 1)
431 ddr->cs3_config = ( 1<<31
434 | (spd.nrow_addr - 12) << 8
435 | (spd.ncol_addr - 8) );
436 debug("DDR: cs3_bnds = 0x%08x\n", ddr->cs3_bnds);
437 debug("DDR: cs3_config = 0x%08x\n", ddr->cs3_config);
440 #endif /* CONFIG_DDR_INTERLEAVE */
443 * Find the largest CAS by locating the highest 1 bit
444 * in the spd.cas_lat field. Translate it to a DDR
445 * controller field value:
447 * CAS Lat DDR I DDR II Ctrl
448 * Clocks SPD Bit SPD Bit Value
449 * ------- ------- ------- -----
460 caslat = __ilog2(spd.cas_lat);
461 if ((spd.mem_type == SPD_MEMTYPE_DDR)
463 printf("DDR I: Invalid SPD CAS Latency: 0x%x.\n", spd.cas_lat);
466 } else if (spd.mem_type == SPD_MEMTYPE_DDR2
467 && (caslat < 2 || caslat > 5)) {
468 printf("DDR II: Invalid SPD CAS Latency: 0x%x.\n",
472 debug("DDR: caslat SPD bit is %d\n", caslat);
475 * Calculate the Maximum Data Rate based on the Minimum Cycle time.
476 * The SPD clk_cycle field (tCKmin) is measured in tenths of
477 * nanoseconds and represented as BCD.
479 tCKmin_ps = convert_bcd_tenths_to_cycle_time_ps(spd.clk_cycle);
480 debug("DDR: tCKmin = %d ps\n", tCKmin_ps);
483 * Double-data rate, scaled 1000 to picoseconds, and back down to MHz.
485 max_data_rate = 2 * 1000 * 1000 / tCKmin_ps;
486 debug("DDR: Module max data rate = %d Mhz\n", max_data_rate);
490 * Adjust the CAS Latency to allow for bus speeds that
491 * are slower than the DDR module.
493 busfreq = get_bus_freq(0) / 1000000; /* MHz */
494 tCycle_ps = convert_bcd_tenths_to_cycle_time_ps(spd.clk_cycle3);
495 modfreq = 2 * 1000 * 1000 / tCycle_ps;
497 if ((spd.mem_type == SPD_MEMTYPE_DDR2) && (busfreq < 266)) {
498 printf("DDR: platform frequency too low for correct DDR2 controller operation\n");
500 } else if (busfreq < 90) {
501 printf("DDR: platform frequency too low for correct DDR1 operation\n");
505 if ((busfreq <= modfreq) && (spd.cas_lat & (1 << (caslat - 2)))) {
508 tCycle_ps = convert_bcd_tenths_to_cycle_time_ps(spd.clk_cycle2);
509 modfreq = 2 * 1000 * 1000 / tCycle_ps;
510 if ((busfreq <= modfreq) && (spd.cas_lat & (1 << (caslat - 1))))
512 else if (busfreq > max_data_rate) {
513 printf("DDR: Bus freq %d MHz is not fit for DDR rate %d MHz\n",
514 busfreq, max_data_rate);
520 * Empirically set ~MCAS-to-preamble override for DDR 2.
521 * Your milage will vary.
524 if (spd.mem_type == SPD_MEMTYPE_DDR2) {
525 if (busfreq <= 333) {
527 } else if (busfreq <= 400) {
535 * Convert caslat clocks to DDR controller value.
536 * Force caslat_ctrl to be DDR Controller field-sized.
538 if (spd.mem_type == SPD_MEMTYPE_DDR) {
539 caslat_ctrl = (caslat + 1) & 0x07;
541 caslat_ctrl = (2 * caslat - 1) & 0x0f;
544 debug("DDR: caslat SPD bit is %d, controller field is 0x%x\n",
545 caslat, caslat_ctrl);
549 * Avoid writing for DDR I. The new PQ38 DDR controller
550 * dreams up non-zero default values to be backwards compatible.
552 if (spd.mem_type == SPD_MEMTYPE_DDR2) {
553 unsigned char taxpd_clk = 8; /* By the book. */
554 unsigned char tmrd_clk = 2; /* By the book. */
555 unsigned char act_pd_exit = 2; /* Empirical? */
556 unsigned char pre_pd_exit = 6; /* Empirical? */
558 ddr->timing_cfg_0 = (0
559 | ((act_pd_exit & 0x7) << 20) /* ACT_PD_EXIT */
560 | ((pre_pd_exit & 0x7) << 16) /* PRE_PD_EXIT */
561 | ((taxpd_clk & 0xf) << 8) /* ODT_PD_EXIT */
562 | ((tmrd_clk & 0xf) << 0) /* MRS_CYC */
564 debug("DDR: timing_cfg_0 = 0x%08x\n", ddr->timing_cfg_0);
570 * Some Timing Config 1 values now.
571 * Sneak Extended Refresh Recovery in here too.
575 * For DDR I, WRREC(Twr) and WRTORD(Twtr) are not in SPD,
576 * use conservative value.
577 * For DDR II, they are bytes 36 and 37, in quarter nanos.
580 if (spd.mem_type == SPD_MEMTYPE_DDR) {
581 twr_clk = 3; /* Clocks */
582 twtr_clk = 1; /* Clocks */
584 twr_clk = picos_to_clk(spd.twr * 250);
585 twtr_clk = picos_to_clk(spd.twtr * 250);
589 * Calculate Trfc, in picos.
590 * DDR I: Byte 42 straight up in ns.
591 * DDR II: Byte 40 and 42 swizzled some, in ns.
593 if (spd.mem_type == SPD_MEMTYPE_DDR) {
594 trfc = spd.trfc * 1000; /* up to ps */
596 unsigned int byte40_table_ps[8] = {
607 trfc = (((spd.trctrfc_ext & 0x1) * 256) + spd.trfc) * 1000
608 + byte40_table_ps[(spd.trctrfc_ext >> 1) & 0x7];
610 trfc_clk = picos_to_clk(trfc);
613 * Trcd, Byte 29, from quarter nanos to ps and clocks.
615 trcd_clk = picos_to_clk(spd.trcd * 250) & 0x7;
618 * Convert trfc_clk to DDR controller fields. DDR I should
619 * fit in the REFREC field (16-19) of TIMING_CFG_1, but the
620 * 8548 controller has an extended REFREC field of three bits.
621 * The controller automatically adds 8 clocks to this value,
622 * so preadjust it down 8 first before splitting it up.
624 trfc_low = (trfc_clk - 8) & 0xf;
625 trfc_high = ((trfc_clk - 8) >> 4) & 0x3;
628 * Sneak in some Extended Refresh Recovery.
630 ddr->ext_refrec = (trfc_high << 16);
631 debug("DDR: ext_refrec = 0x%08x\n", ddr->ext_refrec);
635 | ((picos_to_clk(spd.trp * 250) & 0x07) << 28) /* PRETOACT */
636 | ((picos_to_clk(spd.tras * 1000) & 0x0f ) << 24) /* ACTTOPRE */
637 | (trcd_clk << 20) /* ACTTORW */
638 | (caslat_ctrl << 16) /* CASLAT */
639 | (trfc_low << 12) /* REFEC */
640 | ((twr_clk & 0x07) << 8) /* WRRREC */
641 | ((picos_to_clk(spd.trrd * 250) & 0x07) << 4) /* ACTTOACT */
642 | ((twtr_clk & 0x07) << 0) /* WRTORD */
645 debug("DDR: timing_cfg_1 = 0x%08x\n", ddr->timing_cfg_1);
656 * For DDR II, with ODT enabled, use "a value" less than ACTTORW,
657 * which comes from Trcd, and also note that:
658 * add_lat + caslat must be >= 4
661 if (spd.mem_type == SPD_MEMTYPE_DDR2
662 && (odt_wr_cfg || odt_rd_cfg)
664 add_lat = 4 - caslat;
665 if (add_lat >= trcd_clk) {
666 add_lat = trcd_clk - 1;
672 * Historically 0x2 == 4/8 clock delay.
673 * Empirically, 0x3 == 6/8 clock delay is suggested for DDR I 266.
680 * Minimum CKE Pulse Width.
681 * Four Activate Window
683 if (spd.mem_type == SPD_MEMTYPE_DDR) {
685 * This is a lie. It should really be 1, but if it is
686 * set to 1, bits overlap into the old controller's
687 * otherwise unused ACSM field. If we leave it 0, then
688 * the HW will magically treat it as 1 for DDR 1. Oh Yea.
692 trtp_clk = 2; /* By the book. */
693 cke_min_clk = 1; /* By the book. */
694 four_act = 1; /* By the book. */
699 /* Convert SPD value from quarter nanos to picos. */
700 trtp_clk = picos_to_clk(spd.trtp * 250);
702 cke_min_clk = 3; /* By the book. */
703 four_act = picos_to_clk(37500); /* By the book. 1k pages? */
706 ddr->timing_cfg_2 = (0
707 | ((add_lat & 0x7) << 28) /* ADD_LAT */
708 | ((cpo & 0x1f) << 23) /* CPO */
709 | ((wr_lat & 0x7) << 19) /* WR_LAT */
710 | ((trtp_clk & 0x7) << 13) /* RD_TO_PRE */
711 | ((wr_data_delay & 0x7) << 10) /* WR_DATA_DELAY */
712 | ((cke_min_clk & 0x7) << 6) /* CKE_PLS */
713 | ((four_act & 0x1f) << 0) /* FOUR_ACT */
716 debug("DDR: timing_cfg_2 = 0x%08x\n", ddr->timing_cfg_2);
720 * Determine the Mode Register Set.
722 * This is nominally part specific, but it appears to be
723 * consistent for all DDR I devices, and for all DDR II devices.
725 * caslat must be programmed
726 * burst length is always 4
727 * burst type is sequential
730 * operating mode is "normal"
739 * Table lookup from DDR I or II Device Operation Specs.
741 if (spd.mem_type == SPD_MEMTYPE_DDR) {
742 if (1 <= caslat && caslat <= 4) {
743 unsigned char mode_caslat_table[4] = {
744 0x5, /* 1.5 clocks */
745 0x2, /* 2.0 clocks */
746 0x6, /* 2.5 clocks */
749 mode_caslat = mode_caslat_table[caslat - 1];
751 puts("DDR I: Only CAS Latencies of 1.5, 2.0, "
752 "2.5 and 3.0 clocks are supported.\n");
757 if (2 <= caslat && caslat <= 5) {
758 mode_caslat = caslat;
760 puts("DDR II: Only CAS Latencies of 2.0, 3.0, "
761 "4.0 and 5.0 clocks are supported.\n");
767 * Encoded Burst Length of 4.
769 burst_len = 2; /* Fiat. */
771 if (spd.mem_type == SPD_MEMTYPE_DDR) {
772 twr_auto_clk = 0; /* Historical */
775 * Determine tCK max in picos. Grab tWR and convert to picos.
776 * Auto-precharge write recovery is:
777 * WR = roundup(tWR_ns/tCKmax_ns).
779 * Ponder: Is twr_auto_clk different than twr_clk?
781 tCKmax_ps = convert_bcd_tenths_to_cycle_time_ps(spd.tckmax);
782 twr_auto_clk = (spd.twr * 250 + tCKmax_ps - 1) / tCKmax_ps;
786 * Mode Reg in bits 16 ~ 31,
787 * Extended Mode Reg 1 in bits 0 ~ 15.
789 mode_odt_enable = 0x0; /* Default disabled */
790 if (odt_wr_cfg || odt_rd_cfg) {
792 * Bits 6 and 2 in Extended MRS(1)
793 * Bit 2 == 0x04 == 75 Ohm, with 2 DIMM modules.
794 * Bit 6 == 0x40 == 150 Ohm, with 1 DIMM module.
796 mode_odt_enable = 0x40; /* 150 Ohm */
801 | (add_lat << (16 + 3)) /* Additive Latency in EMRS1 */
802 | (mode_odt_enable << 16) /* ODT Enable in EMRS1 */
803 | (twr_auto_clk << 9) /* Write Recovery Autopre */
804 | (mode_caslat << 4) /* caslat */
805 | (burst_len << 0) /* Burst length */
808 debug("DDR: sdram_mode = 0x%08x\n", ddr->sdram_mode_1);
811 * Clear EMRS2 and EMRS3.
813 ddr->sdram_mode_2 = 0;
814 debug("DDR: sdram_mode_2 = 0x%08x\n", ddr->sdram_mode_2);
817 * Determine Refresh Rate.
819 refresh_clk = determine_refresh_rate(spd.refresh & 0x7);
822 * Set BSTOPRE to 0x100 for page mode
823 * If auto-charge is used, set BSTOPRE = 0
825 ddr->sdram_interval =
827 | (refresh_clk & 0x3fff) << 16
830 debug("DDR: sdram_interval = 0x%08x\n", ddr->sdram_interval);
834 * Is this an ECC DDR chip?
835 * But don't mess with it if the DDR controller will init mem.
837 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
838 if (spd.config == 0x02) {
839 ddr->err_disable = 0x0000000d;
840 ddr->err_sbe = 0x00ff0000;
842 debug("DDR: err_disable = 0x%08x\n", ddr->err_disable);
843 debug("DDR: err_sbe = 0x%08x\n", ddr->err_sbe);
846 asm volatile("sync;isync");
854 * When ODT is enabled, Chap 9 suggests asserting ODT to
855 * internal IOs only during reads.
858 if (odt_rd_cfg | odt_wr_cfg) {
859 odt_cfg = 0x2; /* ODT to IOs during reads */
863 * Try to use differential DQS with DDR II.
865 if (spd.mem_type == SPD_MEMTYPE_DDR) {
866 dqs_cfg = 0; /* No Differential DQS for DDR I */
868 dqs_cfg = 0x1; /* Differential DQS for DDR II */
871 #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
873 * Use the DDR controller to auto initialize memory.
876 ddr->sdram_data_init = CONFIG_MEM_INIT_VALUE;
877 debug("DDR: ddr_data_init = 0x%08x\n", ddr->sdram_data_init);
880 * Memory will be initialized via DMA, or not at all.
885 ddr->sdram_cfg_2 = (0
886 | (dqs_cfg << 26) /* Differential DQS */
887 | (odt_cfg << 21) /* ODT */
888 | (d_init << 4) /* D_INIT auto init DDR */
891 debug("DDR: sdram_cfg_2 = 0x%08x\n", ddr->sdram_cfg_2);
894 #ifdef MPC86xx_DDR_SDRAM_CLK_CNTL
896 * Setup the clock control.
897 * SDRAM_CLK_CNTL[0] = Source synchronous enable == 1
898 * SDRAM_CLK_CNTL[5-7] = Clock Adjust
899 * 0110 3/4 cycle late
900 * 0111 7/8 cycle late
902 if (spd.mem_type == SPD_MEMTYPE_DDR)
907 ddr->sdram_clk_cntl = (0
911 debug("DDR: sdram_clk_cntl = 0x%08x\n", ddr->sdram_clk_cntl);
915 * Figure out memory size in Megabytes.
917 debug("# ranks = %d, rank_density = 0x%08lx\n", n_ranks, rank_density);
918 memsize = n_ranks * rank_density / 0x100000;
923 unsigned int enable_ddr(unsigned int ddr_num)
925 volatile immap_t *immap = (immap_t *)CFG_IMMR;
926 spd_eeprom_t spd1,spd2;
927 volatile ccsr_ddr_t *ddr;
928 unsigned sdram_cfg_1;
929 unsigned char sdram_type, mem_type, config, mod_attr;
930 unsigned char d_init;
931 unsigned int no_dimm1=0, no_dimm2=0;
933 /* Set up pointer to enable the current ddr controller */
935 ddr = &immap->im_ddr1;
937 ddr = &immap->im_ddr2;
940 * Read both dimm slots and decide whether
941 * or not to enable this controller.
943 memset((void *)&spd1,0,sizeof(spd1));
944 memset((void *)&spd2,0,sizeof(spd2));
947 CFG_READ_SPD(SPD_EEPROM_ADDRESS1,
948 0, 1, (uchar *) &spd1, sizeof(spd1));
949 CFG_READ_SPD(SPD_EEPROM_ADDRESS2,
950 0, 1, (uchar *) &spd2, sizeof(spd2));
952 CFG_READ_SPD(SPD_EEPROM_ADDRESS3,
953 0, 1, (uchar *) &spd1, sizeof(spd1));
954 CFG_READ_SPD(SPD_EEPROM_ADDRESS4,
955 0, 1, (uchar *) &spd2, sizeof(spd2));
959 * Check for supported memory module types.
961 if (spd1.mem_type != SPD_MEMTYPE_DDR
962 && spd1.mem_type != SPD_MEMTYPE_DDR2) {
965 debug("\nFound memory of type 0x%02lx ",spd1.mem_type );
966 if (spd1.mem_type == SPD_MEMTYPE_DDR)
972 if (spd2.mem_type != SPD_MEMTYPE_DDR &&
973 spd2.mem_type != SPD_MEMTYPE_DDR2) {
976 debug("\nFound memory of type 0x%02lx ",spd2.mem_type );
977 if (spd2.mem_type == SPD_MEMTYPE_DDR)
983 #ifdef CONFIG_DDR_INTERLEAVE
985 printf("For interleaved operation memory modules need to be present in CS0 DIMM slots of both DDR controllers!\n");
991 * Memory is not present in DIMM1 and DIMM2 - so do not enable DDRn
993 if (no_dimm1 && no_dimm2) {
994 printf("No memory modules found for DDR controller %d!!\n", ddr_num);
997 mem_type = no_dimm2 ? spd1.mem_type : spd2.mem_type;
1000 * Figure out the settings for the sdram_cfg register.
1001 * Build up the entire register in 'sdram_cfg' before
1002 * writing since the write into the register will
1003 * actually enable the memory controller; all settings
1004 * must be done before enabling.
1006 * sdram_cfg[0] = 1 (ddr sdram logic enable)
1007 * sdram_cfg[1] = 1 (self-refresh-enable)
1008 * sdram_cfg[5:7] = (SDRAM type = DDR SDRAM)
1012 sdram_type = (mem_type == SPD_MEMTYPE_DDR) ? 2 : 3;
1014 | (1 << 31) /* Enable */
1015 | (1 << 30) /* Self refresh */
1016 | (sdram_type << 24) /* SDRAM type */
1020 * sdram_cfg[3] = RD_EN - registered DIMM enable
1021 * A value of 0x26 indicates micron registered
1022 * DIMMS (micron.com)
1024 mod_attr = no_dimm2 ? spd1.mod_attr : spd2.mod_attr;
1025 if (mem_type == SPD_MEMTYPE_DDR && mod_attr == 0x26) {
1026 sdram_cfg_1 |= 0x10000000; /* RD_EN */
1029 #if defined(CONFIG_DDR_ECC)
1031 config = no_dimm2 ? spd1.config : spd2.config;
1034 * If the user wanted ECC (enabled via sdram_cfg[2])
1036 if (config == 0x02) {
1037 ddr->err_disable = 0x00000000;
1038 asm volatile("sync;isync;");
1039 ddr->err_sbe = 0x00ff0000;
1040 ddr->err_int_en = 0x0000000d;
1041 sdram_cfg_1 |= 0x20000000; /* ECC_EN */
1046 * Set 1T or 2T timing based on 1 or 2 modules
1049 if (!(no_dimm1 || no_dimm2)) {
1051 * 2T timing,because both DIMMS are present.
1052 * Enable 2T timing by setting sdram_cfg[16].
1054 sdram_cfg_1 |= 0x8000; /* 2T_EN */
1059 * 200 painful micro-seconds must elapse between
1060 * the DDR clock setup and the DDR config enable.
1067 ddr->sdram_cfg_1 = sdram_cfg_1;
1069 asm volatile("sync;isync");
1072 debug("DDR: sdram_cfg = 0x%08x\n", ddr->sdram_cfg_1);
1075 #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
1077 debug("DDR: memory initializing\n");
1080 * Poll until memory is initialized.
1081 * 512 Meg at 400 might hit this 200 times or so.
1083 while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) {
1086 debug("DDR: memory initialized\n\n");
1089 debug("Enabled DDR Controller %d\n", ddr_num);
1098 int memsize_ddr1_dimm1 = 0;
1099 int memsize_ddr1_dimm2 = 0;
1100 int memsize_ddr2_dimm1 = 0;
1101 int memsize_ddr2_dimm2 = 0;
1102 int memsize_total = 0;
1103 int memsize_ddr1 = 0;
1104 int memsize_ddr2 = 0;
1105 unsigned int ddr1_enabled = 0;
1106 unsigned int ddr2_enabled = 0;
1107 unsigned int law_size_ddr1;
1108 unsigned int law_size_ddr2;
1109 volatile immap_t *immap = (immap_t *)CFG_IMMR;
1110 volatile ccsr_ddr_t *ddr1 = &immap->im_ddr1;
1111 volatile ccsr_ddr_t *ddr2 = &immap->im_ddr2;
1112 volatile ccsr_local_mcm_t *mcm = &immap->im_local_mcm;
1114 #ifdef CONFIG_DDR_INTERLEAVE
1115 unsigned int law_size_interleaved;
1117 memsize_ddr1_dimm1 = spd_init(SPD_EEPROM_ADDRESS1,
1119 (unsigned int)memsize_total * 1024*1024);
1120 memsize_total += memsize_ddr1_dimm1;
1122 memsize_ddr2_dimm1 = spd_init(SPD_EEPROM_ADDRESS3,
1124 (unsigned int)memsize_total * 1024*1024);
1125 memsize_total += memsize_ddr2_dimm1;
1127 if (memsize_ddr1_dimm1 != memsize_ddr2_dimm1) {
1128 if (memsize_ddr1_dimm1 < memsize_ddr2_dimm1)
1129 memsize_total -= memsize_ddr1_dimm1;
1131 memsize_total -= memsize_ddr2_dimm1;
1132 debug("Total memory available for interleaving 0x%08lx\n",
1133 memsize_total * 1024 * 1024);
1134 debug("Adjusting CS0_BNDS to account for unequal DIMM sizes in interleaved memory\n");
1135 ddr1->cs0_bnds = ((memsize_total * 1024 * 1024) - 1) >> 24;
1136 ddr2->cs0_bnds = ((memsize_total * 1024 * 1024) - 1) >> 24;
1137 debug("DDR1: cs0_bnds = 0x%08x\n", ddr1->cs0_bnds);
1138 debug("DDR2: cs0_bnds = 0x%08x\n", ddr2->cs0_bnds);
1141 ddr1_enabled = enable_ddr(1);
1142 ddr2_enabled = enable_ddr(2);
1145 * Both controllers need to be enabled for interleaving.
1147 if (ddr1_enabled && ddr2_enabled) {
1148 law_size_interleaved = 19 + __ilog2(memsize_total);
1151 * Set up LAWBAR for DDR 1 space.
1153 mcm->lawbar1 = ((CFG_DDR_SDRAM_BASE >> 12) & 0xfffff);
1154 mcm->lawar1 = (LAWAR_EN
1155 | LAWAR_TRGT_IF_DDR_INTERLEAVED
1156 | (LAWAR_SIZE & law_size_interleaved));
1157 debug("DDR: LAWBAR1=0x%08x\n", mcm->lawbar1);
1158 debug("DDR: LAWAR1=0x%08x\n", mcm->lawar1);
1159 debug("Interleaved memory size is 0x%08lx\n", memsize_total);
1161 #ifdef CONFIG_DDR_INTERLEAVE
1162 #if (CFG_PAGE_INTERLEAVING == 1)
1164 #elif (CFG_BANK_INTERLEAVING == 1)
1166 #elif (CFG_SUPER_BANK_INTERLEAVING == 1)
1167 printf("Super-bank ");
1169 printf("Cache-line ");
1172 printf("Interleaved");
1173 return memsize_total * 1024 * 1024;
1175 printf("Interleaved memory not enabled - check CS0 DIMM slots for both controllers.\n");
1181 * Call spd_sdram() routine to init ddr1 - pass I2c address,
1182 * controller number, dimm number, and starting address.
1184 memsize_ddr1_dimm1 = spd_init(SPD_EEPROM_ADDRESS1,
1186 (unsigned int)memsize_total * 1024*1024);
1187 memsize_total += memsize_ddr1_dimm1;
1189 memsize_ddr1_dimm2 = spd_init(SPD_EEPROM_ADDRESS2,
1191 (unsigned int)memsize_total * 1024*1024);
1192 memsize_total += memsize_ddr1_dimm2;
1195 * Enable the DDR controller - pass ddr controller number.
1197 ddr1_enabled = enable_ddr(1);
1199 /* Keep track of memory to be addressed by DDR1 */
1200 memsize_ddr1 = memsize_ddr1_dimm1 + memsize_ddr1_dimm2;
1203 * First supported LAW size is 16M, at LAWAR_SIZE_16M == 23. Fnord.
1206 law_size_ddr1 = 19 + __ilog2(memsize_ddr1);
1209 * Set up LAWBAR for DDR 1 space.
1211 mcm->lawbar1 = ((CFG_DDR_SDRAM_BASE >> 12) & 0xfffff);
1212 mcm->lawar1 = (LAWAR_EN
1213 | LAWAR_TRGT_IF_DDR1
1214 | (LAWAR_SIZE & law_size_ddr1));
1215 debug("DDR: LAWBAR1=0x%08x\n", mcm->lawbar1);
1216 debug("DDR: LAWAR1=0x%08x\n", mcm->lawar1);
1219 #if (CONFIG_NUM_DDR_CONTROLLERS > 1)
1220 memsize_ddr2_dimm1 = spd_init(SPD_EEPROM_ADDRESS3,
1222 (unsigned int)memsize_total * 1024*1024);
1223 memsize_total += memsize_ddr2_dimm1;
1225 memsize_ddr2_dimm2 = spd_init(SPD_EEPROM_ADDRESS4,
1227 (unsigned int)memsize_total * 1024*1024);
1228 memsize_total += memsize_ddr2_dimm2;
1230 ddr2_enabled = enable_ddr(2);
1232 /* Keep track of memory to be addressed by DDR2 */
1233 memsize_ddr2 = memsize_ddr2_dimm1 + memsize_ddr2_dimm2;
1236 law_size_ddr2 = 19 + __ilog2(memsize_ddr2);
1239 * Set up LAWBAR for DDR 2 space.
1242 mcm->lawbar8 = (((memsize_ddr1 * 1024 * 1024) >> 12)
1245 mcm->lawbar8 = ((CFG_DDR_SDRAM_BASE >> 12) & 0xfffff);
1247 mcm->lawar8 = (LAWAR_EN
1248 | LAWAR_TRGT_IF_DDR2
1249 | (LAWAR_SIZE & law_size_ddr2));
1250 debug("\nDDR: LAWBAR8=0x%08x\n", mcm->lawbar8);
1251 debug("DDR: LAWAR8=0x%08x\n", mcm->lawar8);
1253 #endif /* CONFIG_NUM_DDR_CONTROLLERS > 1 */
1255 debug("\nMemory sizes are DDR1 = 0x%08lx, DDR2 = 0x%08lx\n",
1256 memsize_ddr1, memsize_ddr2);
1259 * If neither DDR controller is enabled return 0.
1261 if (!ddr1_enabled && !ddr2_enabled)
1264 printf("Non-interleaved");
1265 return memsize_total * 1024 * 1024;
1267 #endif /* CONFIG_DDR_INTERLEAVE */
1271 #endif /* CONFIG_SPD_EEPROM */
1274 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
1277 * Initialize all of memory for ECC, then enable errors.
1281 ddr_enable_ecc(unsigned int dram_size)
1285 volatile immap_t *immap = (immap_t *)CFG_IMMR;
1286 volatile ccsr_ddr_t *ddr1= &immap->im_ddr1;
1290 for (*p = 0; p < (uint *)(8 * 1024); p++) {
1291 if (((unsigned int)p & 0x1f) == 0) {
1292 ppcDcbz((unsigned long) p);
1294 *p = (unsigned int)CONFIG_MEM_INIT_VALUE;
1295 if (((unsigned int)p & 0x1c) == 0x1c) {
1296 ppcDcbf((unsigned long) p);
1300 dma_xfer((uint *)0x002000, 0x002000, (uint *)0); /* 8K */
1301 dma_xfer((uint *)0x004000, 0x004000, (uint *)0); /* 16K */
1302 dma_xfer((uint *)0x008000, 0x008000, (uint *)0); /* 32K */
1303 dma_xfer((uint *)0x010000, 0x010000, (uint *)0); /* 64K */
1304 dma_xfer((uint *)0x020000, 0x020000, (uint *)0); /* 128k */
1305 dma_xfer((uint *)0x040000, 0x040000, (uint *)0); /* 256k */
1306 dma_xfer((uint *)0x080000, 0x080000, (uint *)0); /* 512k */
1307 dma_xfer((uint *)0x100000, 0x100000, (uint *)0); /* 1M */
1308 dma_xfer((uint *)0x200000, 0x200000, (uint *)0); /* 2M */
1309 dma_xfer((uint *)0x400000, 0x400000, (uint *)0); /* 4M */
1311 for (i = 1; i < dram_size / 0x800000; i++) {
1312 dma_xfer((uint *)(0x800000*i), 0x800000, (uint *)0);
1316 * Enable errors for ECC.
1318 debug("DMA DDR: err_disable = 0x%08x\n", ddr1->err_disable);
1319 ddr1->err_disable = 0x00000000;
1320 asm volatile("sync;isync");
1321 debug("DMA DDR: err_disable = 0x%08x\n", ddr1->err_disable);
1324 #endif /* CONFIG_DDR_ECC && ! CONFIG_ECC_INIT_VIA_DDRCONTROLLER */