2 * Copyright 2004 Freescale Semiconductor.
3 * (C) Copyright 2003 Motorola Inc.
4 * Xianghua Xiao (X.Xiao@motorola.com)
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <asm/processor.h>
32 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
33 extern void dma_init(void);
34 extern uint dma_check(void);
35 extern int dma_xfer(void *dest, uint count, void *src);
38 #ifdef CONFIG_SPD_EEPROM
41 #define CFG_READ_SPD i2c_read
45 * Only one of the following three should be 1; others should be 0
46 * By default the cache line interleaving is selected if
47 * the CONFIG_DDR_INTERLEAVE flag is defined
49 #define CFG_PAGE_INTERLEAVING 0
50 #define CFG_BANK_INTERLEAVING 0
51 #define CFG_SUPER_BANK_INTERLEAVING 0
54 * Convert picoseconds into clock cycles (rounding up if needed).
58 picos_to_clk(int picos)
62 clks = picos / (2000000000 / (get_bus_freq(0) / 1000));
63 if (picos % (2000000000 / (get_bus_freq(0) / 1000)) != 0) {
72 * Calculate the Density of each Physical Rank.
73 * Returned size is in bytes.
75 * Study these table from Byte 31 of JEDEC SPD Spec.
89 * Reorder Table to be linear by stripping the bottom
90 * 2 or 5 bits off and shifting them up to the top.
94 compute_banksize(unsigned int mem_type, unsigned char row_dens)
98 if (mem_type == SPD_MEMTYPE_DDR) {
99 /* Bottom 2 bits up to the top. */
100 bsize = ((row_dens >> 2) | ((row_dens & 3) << 6)) << 24;
101 debug("DDR: DDR I rank density = 0x%08x\n", bsize);
103 /* Bottom 5 bits up to the top. */
104 bsize = ((row_dens >> 5) | ((row_dens & 31) << 3)) << 27;
105 debug("DDR: DDR II rank density = 0x%08x\n", bsize);
112 * Convert a two-nibble BCD value into a cycle time.
113 * While the spec calls for nano-seconds, picos are returned.
115 * This implements the tables for bytes 9, 23 and 25 for both
116 * DDR I and II. No allowance for distinguishing the invalid
117 * fields absent for DDR I yet present in DDR II is made.
118 * (That is, cycle times of .25, .33, .66 and .75 ns are
119 * allowed for both DDR II and I.)
123 convert_bcd_tenths_to_cycle_time_ps(unsigned int spd_val)
126 * Table look up the lower nibble, allow DDR I & II.
128 unsigned int tenths_ps[16] = {
147 unsigned int whole_ns = (spd_val & 0xF0) >> 4;
148 unsigned int tenth_ns = spd_val & 0x0F;
149 unsigned int ps = whole_ns * 1000 + tenths_ps[tenth_ns];
156 spd_init(unsigned char i2c_address, unsigned int ddr_num,
157 unsigned int dimm_num, unsigned int start_addr)
159 volatile immap_t *immap = (immap_t *)CFG_IMMR;
160 volatile ccsr_ddr_t *ddr;
161 volatile ccsr_gur_t *gur = &immap->im_gur;
163 unsigned int n_ranks;
164 unsigned int rank_density;
165 unsigned int odt_rd_cfg, odt_wr_cfg;
166 unsigned int odt_cfg, mode_odt_enable;
167 unsigned int dqs_cfg;
168 unsigned char twr_clk, twtr_clk, twr_auto_clk;
169 unsigned int tCKmin_ps, tCKmax_ps;
170 unsigned int max_data_rate;
171 unsigned int busfreq;
172 unsigned sdram_cfg_1;
173 unsigned int memsize;
174 unsigned char caslat, caslat_ctrl;
175 unsigned int trfc, trfc_clk, trfc_low, trfc_high;
176 unsigned int trcd_clk;
177 unsigned int trtp_clk;
178 unsigned char cke_min_clk;
179 unsigned char add_lat;
180 unsigned char wr_lat;
181 unsigned char wr_data_delay;
182 unsigned char four_act;
184 unsigned char burst_len;
185 unsigned int mode_caslat;
186 unsigned char sdram_type;
187 unsigned char d_init;
188 unsigned int law_size;
189 volatile ccsr_local_mcm_t *mcm = &immap->im_local_mcm;
190 unsigned int tCycle_ps, modfreq;
193 ddr = &immap->im_ddr1;
195 ddr = &immap->im_ddr2;
198 * Read SPD information.
201 debug("Performing SPD read at I2C address 0x%02lx\n",i2c_address);
202 memset((void *)&spd, 0, sizeof(spd));
203 CFG_READ_SPD(i2c_address, 0, 1, (uchar *) &spd, sizeof(spd));
206 * Check for supported memory module types.
208 if (spd.mem_type != SPD_MEMTYPE_DDR &&
209 spd.mem_type != SPD_MEMTYPE_DDR2) {
210 debug("Warning: Unable to locate DDR I or DDR II module for DIMM %d of DDR controller %d.\n"
211 " Fundamental memory type is 0x%0x\n",
218 debug("\nFound memory of type 0x%02lx ", spd.mem_type);
219 if (spd.mem_type == SPD_MEMTYPE_DDR)
225 * These test gloss over DDR I and II differences in interpretation
226 * of bytes 3 and 4, but irrelevantly. Multiple asymmetric banks
227 * are not supported on DDR I; and not encoded on DDR II.
229 * Also note that the 8548 controller can support:
232 * 8 <= ncol <= 11 (still, for DDR)
233 * 6 <= ncol <= 9 (for FCRAM)
235 if (spd.nrow_addr < 12 || spd.nrow_addr > 14) {
236 printf("DDR: Unsupported number of Row Addr lines: %d.\n",
240 if (spd.ncol_addr < 8 || spd.ncol_addr > 11) {
241 printf("DDR: Unsupported number of Column Addr lines: %d.\n",
247 * Determine the number of physical banks controlled by
248 * different Chip Select signals. This is not quite the
249 * same as the number of DIMM modules on the board. Feh.
251 if (spd.mem_type == SPD_MEMTYPE_DDR) {
254 n_ranks = (spd.nrows & 0x7) + 1;
257 debug("DDR: number of ranks = %d\n", n_ranks);
260 printf("DDR: Only 2 chip selects are supported: %d\n",
266 * Adjust DDR II IO voltage biasing. It just makes it work.
268 if (spd.mem_type == SPD_MEMTYPE_DDR2) {
270 | 0x80000000 /* Enable */
271 | 0x10000000 /* VSEL to 1.8V */
276 * Determine the size of each Rank in bytes.
278 rank_density = compute_banksize(spd.mem_type, spd.row_dens);
280 debug("Start address for this controller is 0x%08lx\n", start_addr);
283 * ODT configuration recommendation from DDR Controller Chapter.
285 odt_rd_cfg = 0; /* Never assert ODT */
286 odt_wr_cfg = 0; /* Never assert ODT */
287 if (spd.mem_type == SPD_MEMTYPE_DDR2) {
288 odt_wr_cfg = 1; /* Assert ODT on writes to CS0 */
291 #ifdef CONFIG_DDR_INTERLEAVE
294 printf("For interleaving memory on HPCN, need to use DIMM 1 for DDR Controller %d !\n", ddr_num);
298 * Since interleaved memory only uses CS0, the
299 * memory sticks have to be identical in size and quantity
300 * of ranks. That essentially gives double the size on
301 * one rank, i.e on CS0 for both controllers put together.
307 * Eg: Bounds: 0x0000_0000 to 0x0f000_0000 first 256 Meg
310 ddr->cs0_bnds = (start_addr >> 8)
311 | (((start_addr + rank_density - 1) >> 24));
313 * Default interleaving mode to cache-line interleaving.
315 ddr->cs0_config = ( 1 << 31
316 #if (CFG_PAGE_INTERLEAVING == 1)
317 | (PAGE_INTERLEAVING)
318 #elif (CFG_BANK_INTERLEAVING == 1)
319 | (BANK_INTERLEAVING)
320 #elif (CFG_SUPER_BANK_INTERLEAVING == 1)
321 | (SUPER_BANK_INTERLEAVING)
323 | (CACHE_LINE_INTERLEAVING)
327 | (spd.nrow_addr - 12) << 8
328 | (spd.ncol_addr - 8) );
330 debug("DDR: cs0_bnds = 0x%08x\n", ddr->cs0_bnds);
331 debug("DDR: cs0_config = 0x%08x\n", ddr->cs0_config);
334 * Adjustment for dual rank memory to get correct memory
335 * size (return value of this function).
344 #else /* CONFIG_DDR_INTERLEAVE */
348 * Eg: Bounds: 0x0000_0000 to 0x0f000_0000 first 256 Meg
350 ddr->cs0_bnds = (start_addr >> 8)
351 | (((start_addr + rank_density - 1) >> 24));
353 ddr->cs0_config = ( 1 << 31
356 | (spd.nrow_addr - 12) << 8
357 | (spd.ncol_addr - 8) );
359 debug("DDR: cs0_bnds = 0x%08x\n", ddr->cs0_bnds);
360 debug("DDR: cs0_config = 0x%08x\n", ddr->cs0_config);
364 * Eg: Bounds: 0x1000_0000 to 0x1f00_0000,
367 ddr->cs1_bnds = (((start_addr + rank_density) >> 8)
368 | (( start_addr + 2*rank_density - 1)
370 ddr->cs1_config = ( 1<<31
373 | (spd.nrow_addr - 12) << 8
374 | (spd.ncol_addr - 8) );
375 debug("DDR: cs1_bnds = 0x%08x\n", ddr->cs1_bnds);
376 debug("DDR: cs1_config = 0x%08x\n", ddr->cs1_config);
381 * This is the 2nd DIMM slot for this controller
384 * Eg: Bounds: 0x0000_0000 to 0x0f000_0000 first 256 Meg
386 ddr->cs2_bnds = (start_addr >> 8)
387 | (((start_addr + rank_density - 1) >> 24));
389 ddr->cs2_config = ( 1 << 31
392 | (spd.nrow_addr - 12) << 8
393 | (spd.ncol_addr - 8) );
395 debug("DDR: cs2_bnds = 0x%08x\n", ddr->cs2_bnds);
396 debug("DDR: cs2_config = 0x%08x\n", ddr->cs2_config);
400 * Eg: Bounds: 0x1000_0000 to 0x1f00_0000,
403 ddr->cs3_bnds = (((start_addr + rank_density) >> 8)
404 | (( start_addr + 2*rank_density - 1)
406 ddr->cs3_config = ( 1<<31
409 | (spd.nrow_addr - 12) << 8
410 | (spd.ncol_addr - 8) );
411 debug("DDR: cs3_bnds = 0x%08x\n", ddr->cs3_bnds);
412 debug("DDR: cs3_config = 0x%08x\n", ddr->cs3_config);
415 #endif /* CONFIG_DDR_INTERLEAVE */
418 * Find the largest CAS by locating the highest 1 bit
419 * in the spd.cas_lat field. Translate it to a DDR
420 * controller field value:
422 * CAS Lat DDR I DDR II Ctrl
423 * Clocks SPD Bit SPD Bit Value
424 * ------- ------- ------- -----
435 caslat = __ilog2(spd.cas_lat);
436 if ((spd.mem_type == SPD_MEMTYPE_DDR)
438 printf("DDR I: Invalid SPD CAS Latency: 0x%x.\n", spd.cas_lat);
441 } else if (spd.mem_type == SPD_MEMTYPE_DDR2
442 && (caslat < 2 || caslat > 5)) {
443 printf("DDR II: Invalid SPD CAS Latency: 0x%x.\n",
447 debug("DDR: caslat SPD bit is %d\n", caslat);
450 * Calculate the Maximum Data Rate based on the Minimum Cycle time.
451 * The SPD clk_cycle field (tCKmin) is measured in tenths of
452 * nanoseconds and represented as BCD.
454 tCKmin_ps = convert_bcd_tenths_to_cycle_time_ps(spd.clk_cycle);
455 debug("DDR: tCKmin = %d ps\n", tCKmin_ps);
458 * Double-data rate, scaled 1000 to picoseconds, and back down to MHz.
460 max_data_rate = 2 * 1000 * 1000 / tCKmin_ps;
461 debug("DDR: Module max data rate = %d Mhz\n", max_data_rate);
465 * Adjust the CAS Latency to allow for bus speeds that
466 * are slower than the DDR module.
468 busfreq = get_bus_freq(0) / 1000000; /* MHz */
469 tCycle_ps = convert_bcd_tenths_to_cycle_time_ps(spd.clk_cycle3);
470 modfreq = 2 * 1000 * 1000 / tCycle_ps;
472 if ((spd.mem_type == SPD_MEMTYPE_DDR2) && (busfreq < 266)) {
473 printf("DDR: platform frequency too low for correct DDR2 controller operation\n");
475 } else if (busfreq < 90) {
476 printf("DDR: platform frequency too low for correct DDR1 operation\n");
480 if ((busfreq <= modfreq) && (spd.cas_lat & (1 << (caslat - 2)))) {
483 tCycle_ps = convert_bcd_tenths_to_cycle_time_ps(spd.clk_cycle2);
484 modfreq = 2 * 1000 * 1000 / tCycle_ps;
485 if ((busfreq <= modfreq) && (spd.cas_lat & (1 << (caslat - 1))))
487 else if (busfreq > max_data_rate) {
488 printf("DDR: Bus freq %d MHz is not fit for DDR rate %d MHz\n",
489 busfreq, max_data_rate);
495 * Empirically set ~MCAS-to-preamble override for DDR 2.
496 * Your milage will vary.
499 if (spd.mem_type == SPD_MEMTYPE_DDR2) {
500 if (busfreq <= 333) {
502 } else if (busfreq <= 400) {
510 * Convert caslat clocks to DDR controller value.
511 * Force caslat_ctrl to be DDR Controller field-sized.
513 if (spd.mem_type == SPD_MEMTYPE_DDR) {
514 caslat_ctrl = (caslat + 1) & 0x07;
516 caslat_ctrl = (2 * caslat - 1) & 0x0f;
519 debug("DDR: caslat SPD bit is %d, controller field is 0x%x\n",
520 caslat, caslat_ctrl);
524 * Avoid writing for DDR I. The new PQ38 DDR controller
525 * dreams up non-zero default values to be backwards compatible.
527 if (spd.mem_type == SPD_MEMTYPE_DDR2) {
528 unsigned char taxpd_clk = 8; /* By the book. */
529 unsigned char tmrd_clk = 2; /* By the book. */
530 unsigned char act_pd_exit = 2; /* Empirical? */
531 unsigned char pre_pd_exit = 6; /* Empirical? */
533 ddr->timing_cfg_0 = (0
534 | ((act_pd_exit & 0x7) << 20) /* ACT_PD_EXIT */
535 | ((pre_pd_exit & 0x7) << 16) /* PRE_PD_EXIT */
536 | ((taxpd_clk & 0xf) << 8) /* ODT_PD_EXIT */
537 | ((tmrd_clk & 0xf) << 0) /* MRS_CYC */
539 debug("DDR: timing_cfg_0 = 0x%08x\n", ddr->timing_cfg_0);
545 * Some Timing Config 1 values now.
546 * Sneak Extended Refresh Recovery in here too.
550 * For DDR I, WRREC(Twr) and WRTORD(Twtr) are not in SPD,
551 * use conservative value.
552 * For DDR II, they are bytes 36 and 37, in quarter nanos.
555 if (spd.mem_type == SPD_MEMTYPE_DDR) {
556 twr_clk = 3; /* Clocks */
557 twtr_clk = 1; /* Clocks */
559 twr_clk = picos_to_clk(spd.twr * 250);
560 twtr_clk = picos_to_clk(spd.twtr * 250);
564 * Calculate Trfc, in picos.
565 * DDR I: Byte 42 straight up in ns.
566 * DDR II: Byte 40 and 42 swizzled some, in ns.
568 if (spd.mem_type == SPD_MEMTYPE_DDR) {
569 trfc = spd.trfc * 1000; /* up to ps */
571 unsigned int byte40_table_ps[8] = {
582 trfc = (((spd.trctrfc_ext & 0x1) * 256) + spd.trfc) * 1000
583 + byte40_table_ps[(spd.trctrfc_ext >> 1) & 0x7];
585 trfc_clk = picos_to_clk(trfc);
588 * Trcd, Byte 29, from quarter nanos to ps and clocks.
590 trcd_clk = picos_to_clk(spd.trcd * 250) & 0x7;
593 * Convert trfc_clk to DDR controller fields. DDR I should
594 * fit in the REFREC field (16-19) of TIMING_CFG_1, but the
595 * 8548 controller has an extended REFREC field of three bits.
596 * The controller automatically adds 8 clocks to this value,
597 * so preadjust it down 8 first before splitting it up.
599 trfc_low = (trfc_clk - 8) & 0xf;
600 trfc_high = ((trfc_clk - 8) >> 4) & 0x3;
603 * Sneak in some Extended Refresh Recovery.
605 ddr->ext_refrec = (trfc_high << 16);
606 debug("DDR: ext_refrec = 0x%08x\n", ddr->ext_refrec);
610 | ((picos_to_clk(spd.trp * 250) & 0x07) << 28) /* PRETOACT */
611 | ((picos_to_clk(spd.tras * 1000) & 0x0f ) << 24) /* ACTTOPRE */
612 | (trcd_clk << 20) /* ACTTORW */
613 | (caslat_ctrl << 16) /* CASLAT */
614 | (trfc_low << 12) /* REFEC */
615 | ((twr_clk & 0x07) << 8) /* WRRREC */
616 | ((picos_to_clk(spd.trrd * 250) & 0x07) << 4) /* ACTTOACT */
617 | ((twtr_clk & 0x07) << 0) /* WRTORD */
620 debug("DDR: timing_cfg_1 = 0x%08x\n", ddr->timing_cfg_1);
631 * For DDR II, with ODT enabled, use "a value" less than ACTTORW,
632 * which comes from Trcd, and also note that:
633 * add_lat + caslat must be >= 4
636 if (spd.mem_type == SPD_MEMTYPE_DDR2
637 && (odt_wr_cfg || odt_rd_cfg)
639 add_lat = 4 - caslat;
640 if (add_lat >= trcd_clk) {
641 add_lat = trcd_clk - 1;
647 * Historically 0x2 == 4/8 clock delay.
648 * Empirically, 0x3 == 6/8 clock delay is suggested for DDR I 266.
655 * Minimum CKE Pulse Width.
656 * Four Activate Window
658 if (spd.mem_type == SPD_MEMTYPE_DDR) {
660 * This is a lie. It should really be 1, but if it is
661 * set to 1, bits overlap into the old controller's
662 * otherwise unused ACSM field. If we leave it 0, then
663 * the HW will magically treat it as 1 for DDR 1. Oh Yea.
667 trtp_clk = 2; /* By the book. */
668 cke_min_clk = 1; /* By the book. */
669 four_act = 1; /* By the book. */
674 /* Convert SPD value from quarter nanos to picos. */
675 trtp_clk = picos_to_clk(spd.trtp * 250);
677 cke_min_clk = 3; /* By the book. */
678 four_act = picos_to_clk(37500); /* By the book. 1k pages? */
681 ddr->timing_cfg_2 = (0
682 | ((add_lat & 0x7) << 28) /* ADD_LAT */
683 | ((cpo & 0x1f) << 23) /* CPO */
684 | ((wr_lat & 0x7) << 19) /* WR_LAT */
685 | ((trtp_clk & 0x7) << 13) /* RD_TO_PRE */
686 | ((wr_data_delay & 0x7) << 10) /* WR_DATA_DELAY */
687 | ((cke_min_clk & 0x7) << 6) /* CKE_PLS */
688 | ((four_act & 0x1f) << 0) /* FOUR_ACT */
691 debug("DDR: timing_cfg_2 = 0x%08x\n", ddr->timing_cfg_2);
695 * Determine the Mode Register Set.
697 * This is nominally part specific, but it appears to be
698 * consistent for all DDR I devices, and for all DDR II devices.
700 * caslat must be programmed
701 * burst length is always 4
702 * burst type is sequential
705 * operating mode is "normal"
714 * Table lookup from DDR I or II Device Operation Specs.
716 if (spd.mem_type == SPD_MEMTYPE_DDR) {
717 if (1 <= caslat && caslat <= 4) {
718 unsigned char mode_caslat_table[4] = {
719 0x5, /* 1.5 clocks */
720 0x2, /* 2.0 clocks */
721 0x6, /* 2.5 clocks */
724 mode_caslat = mode_caslat_table[caslat - 1];
726 puts("DDR I: Only CAS Latencies of 1.5, 2.0, "
727 "2.5 and 3.0 clocks are supported.\n");
732 if (2 <= caslat && caslat <= 5) {
733 mode_caslat = caslat;
735 puts("DDR II: Only CAS Latencies of 2.0, 3.0, "
736 "4.0 and 5.0 clocks are supported.\n");
742 * Encoded Burst Length of 4.
744 burst_len = 2; /* Fiat. */
746 if (spd.mem_type == SPD_MEMTYPE_DDR) {
747 twr_auto_clk = 0; /* Historical */
750 * Determine tCK max in picos. Grab tWR and convert to picos.
751 * Auto-precharge write recovery is:
752 * WR = roundup(tWR_ns/tCKmax_ns).
754 * Ponder: Is twr_auto_clk different than twr_clk?
756 tCKmax_ps = convert_bcd_tenths_to_cycle_time_ps(spd.tckmax);
757 twr_auto_clk = (spd.twr * 250 + tCKmax_ps - 1) / tCKmax_ps;
762 * Mode Reg in bits 16 ~ 31,
763 * Extended Mode Reg 1 in bits 0 ~ 15.
765 mode_odt_enable = 0x0; /* Default disabled */
766 if (odt_wr_cfg || odt_rd_cfg) {
768 * Bits 6 and 2 in Extended MRS(1)
769 * Bit 2 == 0x04 == 75 Ohm, with 2 DIMM modules.
770 * Bit 6 == 0x40 == 150 Ohm, with 1 DIMM module.
772 mode_odt_enable = 0x40; /* 150 Ohm */
777 | (add_lat << (16 + 3)) /* Additive Latency in EMRS1 */
778 | (mode_odt_enable << 16) /* ODT Enable in EMRS1 */
779 | (twr_auto_clk << 9) /* Write Recovery Autopre */
780 | (mode_caslat << 4) /* caslat */
781 | (burst_len << 0) /* Burst length */
784 debug("DDR: sdram_mode = 0x%08x\n", ddr->sdram_mode_1);
788 * Clear EMRS2 and EMRS3.
790 ddr->sdram_mode_2 = 0;
791 debug("DDR: sdram_mode_2 = 0x%08x\n", ddr->sdram_mode_2);
795 * Determine Refresh Rate. Ignore self refresh bit on DDR I.
796 * Table from SPD Spec, Byte 12, converted to picoseconds and
797 * filled in with "default" normal values.
800 unsigned int refresh_clk;
801 unsigned int refresh_time_ns[8] = {
802 15625000, /* 0 Normal 1.00x */
803 3900000, /* 1 Reduced .25x */
804 7800000, /* 2 Extended .50x */
805 31300000, /* 3 Extended 2.00x */
806 62500000, /* 4 Extended 4.00x */
807 125000000, /* 5 Extended 8.00x */
808 15625000, /* 6 Normal 1.00x filler */
809 15625000, /* 7 Normal 1.00x filler */
812 refresh_clk = picos_to_clk(refresh_time_ns[spd.refresh & 0x7]);
815 * Set BSTOPRE to 0x100 for page mode
816 * If auto-charge is used, set BSTOPRE = 0
818 ddr->sdram_interval =
820 | (refresh_clk & 0x3fff) << 16
823 debug("DDR: sdram_interval = 0x%08x\n", ddr->sdram_interval);
827 * Is this an ECC DDR chip?
828 * But don't mess with it if the DDR controller will init mem.
830 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
831 if (spd.config == 0x02) {
832 ddr->err_disable = 0x0000000d;
833 ddr->err_sbe = 0x00ff0000;
835 debug("DDR: err_disable = 0x%08x\n", ddr->err_disable);
836 debug("DDR: err_sbe = 0x%08x\n", ddr->err_sbe);
839 asm volatile("sync;isync");
847 * When ODT is enabled, Chap 9 suggests asserting ODT to
848 * internal IOs only during reads.
851 if (odt_rd_cfg | odt_wr_cfg) {
852 odt_cfg = 0x2; /* ODT to IOs during reads */
856 * Try to use differential DQS with DDR II.
858 if (spd.mem_type == SPD_MEMTYPE_DDR) {
859 dqs_cfg = 0; /* No Differential DQS for DDR I */
861 dqs_cfg = 0x1; /* Differential DQS for DDR II */
864 #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
866 * Use the DDR controller to auto initialize memory.
869 ddr->sdram_data_init = CONFIG_MEM_INIT_VALUE;
870 debug("DDR: ddr_data_init = 0x%08x\n", ddr->sdram_data_init);
873 * Memory will be initialized via DMA, or not at all.
878 ddr->sdram_cfg_2 = (0
879 | (dqs_cfg << 26) /* Differential DQS */
880 | (odt_cfg << 21) /* ODT */
881 | (d_init << 4) /* D_INIT auto init DDR */
884 debug("DDR: sdram_cfg_2 = 0x%08x\n", ddr->sdram_cfg_2);
887 #ifdef MPC86xx_DDR_SDRAM_CLK_CNTL
889 unsigned char clk_adjust;
892 * Setup the clock control.
893 * SDRAM_CLK_CNTL[0] = Source synchronous enable == 1
894 * SDRAM_CLK_CNTL[5-7] = Clock Adjust
895 * 0110 3/4 cycle late
896 * 0111 7/8 cycle late
898 if (spd.mem_type == SPD_MEMTYPE_DDR) {
904 ddr->sdram_clk_cntl = (0
908 debug("DDR: sdram_clk_cntl = 0x%08x\n", ddr->sdram_clk_cntl);
914 * Figure out memory size in Megabytes.
916 debug("# ranks = %d, rank_density = 0x%08lx\n", n_ranks, rank_density);
917 memsize = n_ranks * rank_density / 0x100000;
922 unsigned int enable_ddr(unsigned int ddr_num)
924 volatile immap_t *immap = (immap_t *)CFG_IMMR;
925 spd_eeprom_t spd1,spd2;
926 volatile ccsr_ddr_t *ddr;
927 unsigned sdram_cfg_1;
928 unsigned char sdram_type, mem_type, config, mod_attr;
929 unsigned char d_init;
930 unsigned int no_dimm1=0, no_dimm2=0;
932 /* Set up pointer to enable the current ddr controller */
934 ddr = &immap->im_ddr1;
936 ddr = &immap->im_ddr2;
939 * Read both dimm slots and decide whether
940 * or not to enable this controller.
942 memset((void *)&spd1,0,sizeof(spd1));
943 memset((void *)&spd2,0,sizeof(spd2));
946 CFG_READ_SPD(SPD_EEPROM_ADDRESS1,
947 0, 1, (uchar *) &spd1, sizeof(spd1));
948 CFG_READ_SPD(SPD_EEPROM_ADDRESS2,
949 0, 1, (uchar *) &spd2, sizeof(spd2));
951 CFG_READ_SPD(SPD_EEPROM_ADDRESS3,
952 0, 1, (uchar *) &spd1, sizeof(spd1));
953 CFG_READ_SPD(SPD_EEPROM_ADDRESS4,
954 0, 1, (uchar *) &spd2, sizeof(spd2));
958 * Check for supported memory module types.
960 if (spd1.mem_type != SPD_MEMTYPE_DDR
961 && spd1.mem_type != SPD_MEMTYPE_DDR2) {
964 debug("\nFound memory of type 0x%02lx ",spd1.mem_type );
965 if (spd1.mem_type == SPD_MEMTYPE_DDR)
971 if (spd2.mem_type != SPD_MEMTYPE_DDR &&
972 spd2.mem_type != SPD_MEMTYPE_DDR2) {
975 debug("\nFound memory of type 0x%02lx ",spd2.mem_type );
976 if (spd2.mem_type == SPD_MEMTYPE_DDR)
982 #ifdef CONFIG_DDR_INTERLEAVE
984 printf("For interleaved operation memory modules need to be present in CS0 DIMM slots of both DDR controllers!\n");
990 * Memory is not present in DIMM1 and DIMM2 - so do not enable DDRn
992 if (no_dimm1 && no_dimm2) {
993 printf("No memory modules found for DDR controller %d!!\n", ddr_num);
996 mem_type = no_dimm2 ? spd1.mem_type : spd2.mem_type;
999 * Figure out the settings for the sdram_cfg register.
1000 * Build up the entire register in 'sdram_cfg' before
1001 * writing since the write into the register will
1002 * actually enable the memory controller; all settings
1003 * must be done before enabling.
1005 * sdram_cfg[0] = 1 (ddr sdram logic enable)
1006 * sdram_cfg[1] = 1 (self-refresh-enable)
1007 * sdram_cfg[5:7] = (SDRAM type = DDR SDRAM)
1011 sdram_type = (mem_type == SPD_MEMTYPE_DDR) ? 2 : 3;
1013 | (1 << 31) /* Enable */
1014 | (1 << 30) /* Self refresh */
1015 | (sdram_type << 24) /* SDRAM type */
1019 * sdram_cfg[3] = RD_EN - registered DIMM enable
1020 * A value of 0x26 indicates micron registered
1021 * DIMMS (micron.com)
1023 mod_attr = no_dimm2 ? spd1.mod_attr : spd2.mod_attr;
1024 if (mem_type == SPD_MEMTYPE_DDR && mod_attr == 0x26) {
1025 sdram_cfg_1 |= 0x10000000; /* RD_EN */
1028 #if defined(CONFIG_DDR_ECC)
1030 config = no_dimm2 ? spd1.config : spd2.config;
1033 * If the user wanted ECC (enabled via sdram_cfg[2])
1035 if (config == 0x02) {
1036 ddr->err_disable = 0x00000000;
1037 asm volatile("sync;isync;");
1038 ddr->err_sbe = 0x00ff0000;
1039 ddr->err_int_en = 0x0000000d;
1040 sdram_cfg_1 |= 0x20000000; /* ECC_EN */
1045 * Set 1T or 2T timing based on 1 or 2 modules
1048 if (!(no_dimm1 || no_dimm2)) {
1050 * 2T timing,because both DIMMS are present.
1051 * Enable 2T timing by setting sdram_cfg[16].
1053 sdram_cfg_1 |= 0x8000; /* 2T_EN */
1058 * 200 painful micro-seconds must elapse between
1059 * the DDR clock setup and the DDR config enable.
1066 ddr->sdram_cfg_1 = sdram_cfg_1;
1068 asm volatile("sync;isync");
1071 debug("DDR: sdram_cfg = 0x%08x\n", ddr->sdram_cfg_1);
1074 #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
1076 debug("DDR: memory initializing\n");
1079 * Poll until memory is initialized.
1080 * 512 Meg at 400 might hit this 200 times or so.
1082 while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) {
1085 debug("DDR: memory initialized\n\n");
1088 debug("Enabled DDR Controller %d\n", ddr_num);
1097 int memsize_ddr1_dimm1 = 0;
1098 int memsize_ddr1_dimm2 = 0;
1099 int memsize_ddr2_dimm1 = 0;
1100 int memsize_ddr2_dimm2 = 0;
1101 int memsize_total = 0;
1102 int memsize_ddr1 = 0;
1103 int memsize_ddr2 = 0;
1104 unsigned int ddr1_enabled = 0;
1105 unsigned int ddr2_enabled = 0;
1106 unsigned int law_size_ddr1;
1107 unsigned int law_size_ddr2;
1108 volatile immap_t *immap = (immap_t *)CFG_IMMR;
1109 volatile ccsr_ddr_t *ddr1 = &immap->im_ddr1;
1110 volatile ccsr_ddr_t *ddr2 = &immap->im_ddr2;
1111 volatile ccsr_local_mcm_t *mcm = &immap->im_local_mcm;
1113 #ifdef CONFIG_DDR_INTERLEAVE
1114 unsigned int law_size_interleaved;
1116 memsize_ddr1_dimm1 = spd_init(SPD_EEPROM_ADDRESS1,
1118 (unsigned int)memsize_total * 1024*1024);
1119 memsize_total += memsize_ddr1_dimm1;
1121 memsize_ddr2_dimm1 = spd_init(SPD_EEPROM_ADDRESS3,
1123 (unsigned int)memsize_total * 1024*1024);
1124 memsize_total += memsize_ddr2_dimm1;
1126 if (memsize_ddr1_dimm1 != memsize_ddr2_dimm1) {
1127 if (memsize_ddr1_dimm1 < memsize_ddr2_dimm1)
1128 memsize_total -= memsize_ddr1_dimm1;
1130 memsize_total -= memsize_ddr2_dimm1;
1131 debug("Total memory available for interleaving 0x%08lx\n",
1132 memsize_total * 1024 * 1024);
1133 debug("Adjusting CS0_BNDS to account for unequal DIMM sizes in interleaved memory\n");
1134 ddr1->cs0_bnds = ((memsize_total * 1024 * 1024) - 1) >> 24;
1135 ddr2->cs0_bnds = ((memsize_total * 1024 * 1024) - 1) >> 24;
1136 debug("DDR1: cs0_bnds = 0x%08x\n", ddr1->cs0_bnds);
1137 debug("DDR2: cs0_bnds = 0x%08x\n", ddr2->cs0_bnds);
1140 ddr1_enabled = enable_ddr(1);
1141 ddr2_enabled = enable_ddr(2);
1144 * Both controllers need to be enabled for interleaving.
1146 if (ddr1_enabled && ddr2_enabled) {
1147 law_size_interleaved = 19 + __ilog2(memsize_total);
1150 * Set up LAWBAR for DDR 1 space.
1152 mcm->lawbar1 = ((CFG_DDR_SDRAM_BASE >> 12) & 0xfffff);
1153 mcm->lawar1 = (LAWAR_EN
1154 | LAWAR_TRGT_IF_DDR_INTERLEAVED
1155 | (LAWAR_SIZE & law_size_interleaved));
1156 debug("DDR: LAWBAR1=0x%08x\n", mcm->lawbar1);
1157 debug("DDR: LAWAR1=0x%08x\n", mcm->lawar1);
1158 debug("Interleaved memory size is 0x%08lx\n", memsize_total);
1160 #ifdef CONFIG_DDR_INTERLEAVE
1161 #if (CFG_PAGE_INTERLEAVING == 1)
1163 #elif (CFG_BANK_INTERLEAVING == 1)
1165 #elif (CFG_SUPER_BANK_INTERLEAVING == 1)
1166 printf("Super-bank ");
1168 printf("Cache-line ");
1171 printf("Interleaved");
1172 return memsize_total * 1024 * 1024;
1174 printf("Interleaved memory not enabled - check CS0 DIMM slots for both controllers.\n");
1180 * Call spd_sdram() routine to init ddr1 - pass I2c address,
1181 * controller number, dimm number, and starting address.
1183 memsize_ddr1_dimm1 = spd_init(SPD_EEPROM_ADDRESS1,
1185 (unsigned int)memsize_total * 1024*1024);
1186 memsize_total += memsize_ddr1_dimm1;
1188 memsize_ddr1_dimm2 = spd_init(SPD_EEPROM_ADDRESS2,
1190 (unsigned int)memsize_total * 1024*1024);
1191 memsize_total += memsize_ddr1_dimm2;
1194 * Enable the DDR controller - pass ddr controller number.
1196 ddr1_enabled = enable_ddr(1);
1198 /* Keep track of memory to be addressed by DDR1 */
1199 memsize_ddr1 = memsize_ddr1_dimm1 + memsize_ddr1_dimm2;
1202 * First supported LAW size is 16M, at LAWAR_SIZE_16M == 23. Fnord.
1205 law_size_ddr1 = 19 + __ilog2(memsize_ddr1);
1208 * Set up LAWBAR for DDR 1 space.
1210 mcm->lawbar1 = ((CFG_DDR_SDRAM_BASE >> 12) & 0xfffff);
1211 mcm->lawar1 = (LAWAR_EN
1212 | LAWAR_TRGT_IF_DDR1
1213 | (LAWAR_SIZE & law_size_ddr1));
1214 debug("DDR: LAWBAR1=0x%08x\n", mcm->lawbar1);
1215 debug("DDR: LAWAR1=0x%08x\n", mcm->lawar1);
1218 #if (CONFIG_NUM_DDR_CONTROLLERS > 1)
1219 memsize_ddr2_dimm1 = spd_init(SPD_EEPROM_ADDRESS3,
1221 (unsigned int)memsize_total * 1024*1024);
1222 memsize_total += memsize_ddr2_dimm1;
1224 memsize_ddr2_dimm2 = spd_init(SPD_EEPROM_ADDRESS4,
1226 (unsigned int)memsize_total * 1024*1024);
1227 memsize_total += memsize_ddr2_dimm2;
1229 ddr2_enabled = enable_ddr(2);
1231 /* Keep track of memory to be addressed by DDR2 */
1232 memsize_ddr2 = memsize_ddr2_dimm1 + memsize_ddr2_dimm2;
1235 law_size_ddr2 = 19 + __ilog2(memsize_ddr2);
1238 * Set up LAWBAR for DDR 2 space.
1241 mcm->lawbar8 = (((memsize_ddr1 * 1024 * 1024) >> 12)
1244 mcm->lawbar8 = ((CFG_DDR_SDRAM_BASE >> 12) & 0xfffff);
1246 mcm->lawar8 = (LAWAR_EN
1247 | LAWAR_TRGT_IF_DDR2
1248 | (LAWAR_SIZE & law_size_ddr2));
1249 debug("\nDDR: LAWBAR8=0x%08x\n", mcm->lawbar8);
1250 debug("DDR: LAWAR8=0x%08x\n", mcm->lawar8);
1252 #endif /* CONFIG_NUM_DDR_CONTROLLERS > 1 */
1254 debug("\nMemory sizes are DDR1 = 0x%08lx, DDR2 = 0x%08lx\n",
1255 memsize_ddr1, memsize_ddr2);
1258 * If neither DDR controller is enabled return 0.
1260 if (!ddr1_enabled && !ddr2_enabled)
1263 printf("Non-interleaved");
1264 return memsize_total * 1024 * 1024;
1267 #endif /* CONFIG_DDR_INTERLEAVE */
1271 #endif /* CONFIG_SPD_EEPROM */
1274 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
1277 * Initialize all of memory for ECC, then enable errors.
1281 ddr_enable_ecc(unsigned int dram_size)
1285 volatile immap_t *immap = (immap_t *)CFG_IMMR;
1286 volatile ccsr_ddr_t *ddr1= &immap->im_ddr1;
1290 for (*p = 0; p < (uint *)(8 * 1024); p++) {
1291 if (((unsigned int)p & 0x1f) == 0) {
1292 ppcDcbz((unsigned long) p);
1294 *p = (unsigned int)CONFIG_MEM_INIT_VALUE;
1295 if (((unsigned int)p & 0x1c) == 0x1c) {
1296 ppcDcbf((unsigned long) p);
1301 dma_xfer((uint *)0x2000, 0x2000, (uint *)0);
1303 dma_xfer((uint *)0x4000, 0x4000, (uint *)0);
1305 dma_xfer((uint *)0x8000, 0x8000, (uint *)0);
1307 dma_xfer((uint *)0x10000, 0x10000, (uint *)0);
1309 dma_xfer((uint *)0x20000, 0x20000, (uint *)0);
1311 dma_xfer((uint *)0x40000, 0x40000, (uint *)0);
1313 dma_xfer((uint *)0x80000, 0x80000, (uint *)0);
1315 dma_xfer((uint *)0x100000, 0x100000, (uint *)0);
1317 dma_xfer((uint *)0x200000, 0x200000, (uint *)0);
1319 dma_xfer((uint *)0x400000, 0x400000, (uint *)0);
1321 for (i = 1; i < dram_size / 0x800000; i++) {
1322 dma_xfer((uint *)(0x800000*i), 0x800000, (uint *)0);
1326 * Enable errors for ECC.
1328 debug("DMA DDR: err_disable = 0x%08x\n", ddr1->err_disable);
1329 ddr1->err_disable = 0x00000000;
1330 asm volatile("sync;isync");
1331 debug("DMA DDR: err_disable = 0x%08x\n", ddr1->err_disable);
1334 #endif /* CONFIG_DDR_ECC && ! CONFIG_ECC_INIT_VIA_DDRCONTROLLER */