2 * Support for indirect PCI bridges.
4 * Copyright (c) Freescale Semiconductor, Inc.
5 * 2006. All rights reserved.
7 * Jason Jin <Jason.jin@freescale.com>
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version
12 * 2 of the License, or (at your option) any later version.
15 * arch/powerpc/platforms/86xx/mpc86xx_pcie.c
22 #include <asm/processor.h>
26 #define PCI_CFG_OUT out_be32
27 #define PEX_FIX out_be32(hose->cfg_addr+0x4, 0x0400ffff)
30 indirect_read_config_pcie(struct pci_controller *hose,
31 pci_dev_t dev, int offset,
34 int bus = PCI_BUS(dev);
36 volatile unsigned char *cfg_data;
41 PCI_CFG_OUT(hose->cfg_addr, dev | (offset & 0xfc) | 0x80000001);
43 PCI_CFG_OUT(hose->cfg_addr, dev | (offset & 0xfc) | 0x80000000);
46 * Note: the caller has already checked that offset is
47 * suitably aligned and that len is 1, 2 or 4.
49 /* ERRATA PCI-Ex 12 - Configuration Address/Data Alignment */
50 cfg_data = hose->cfg_data;
52 temp = in_le32((u32 *)cfg_data);
55 *val = (temp >> (((offset & 3))*8)) & 0xff;
58 *val = (temp >> (((offset & 3))*8)) & 0xffff;
69 indirect_write_config_pcie(struct pci_controller *hose,
75 int bus = PCI_BUS(dev);
76 volatile unsigned char *cfg_data;
81 PCI_CFG_OUT(hose->cfg_addr, dev | (offset & 0xfc) | 0x80000001);
83 PCI_CFG_OUT(hose->cfg_addr, dev | (offset & 0xfc) | 0x80000000);
87 * Note: the caller has already checked that offset is
88 * suitably aligned and that len is 1, 2 or 4.
90 /* ERRATA PCI-Ex 12 - Configuration Address/Data Alignment */
91 cfg_data = hose->cfg_data;
95 temp = in_le32((u32 *)cfg_data);
96 temp = (temp & ~(0xff << ((offset & 3) * 8))) |
97 (val << ((offset & 3) * 8));
99 out_le32((u32 *)cfg_data, temp);
103 temp = in_le32((u32 *)cfg_data);
104 temp = (temp & ~(0xffff << ((offset & 3) * 8)));
105 temp |= (val << ((offset & 3) * 8)) ;
107 out_le32((u32 *)cfg_data, temp);
111 out_le32((u32 *)cfg_data, val);
119 indirect_read_config_byte_pcie(struct pci_controller *hose,
125 indirect_read_config_pcie(hose,dev,offset,1,&val32);
131 indirect_read_config_word_pcie(struct pci_controller *hose,
137 indirect_read_config_pcie(hose,dev,offset,2,&val32);
143 indirect_read_config_dword_pcie(struct pci_controller *hose,
148 return indirect_read_config_pcie(hose,dev, offset,4,val);
152 indirect_write_config_byte_pcie(struct pci_controller *hose,
157 return indirect_write_config_pcie(hose,dev, offset,1,(u32)val);
161 indirect_write_config_word_pcie(struct pci_controller *hose,
166 return indirect_write_config_pcie(hose,dev, offset,2,(u32)val);
170 indirect_write_config_dword_pcie(struct pci_controller *hose,
175 return indirect_write_config_pcie(hose,dev, offset,4,val);
179 pcie_setup_indirect(struct pci_controller* hose,
184 indirect_read_config_byte_pcie,
185 indirect_read_config_word_pcie,
186 indirect_read_config_dword_pcie,
187 indirect_write_config_byte_pcie,
188 indirect_write_config_word_pcie,
189 indirect_write_config_dword_pcie);
191 hose->cfg_addr = (unsigned int *) cfg_addr;
192 hose->cfg_data = (unsigned char *) cfg_data;
195 #endif /* CONFIG_PCI */