2 * Support for indirect PCI bridges.
4 * Copyright (c) Freescale Semiconductor, Inc.
5 * 2006. All rights reserved.
7 * Jason Jin <Jason.jin@freescale.com>
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version
12 * 2 of the License, or (at your option) any later version.
15 * arch/powerpc/platforms/86xx/mpc86xx_pcie.c
22 #include <asm/processor.h>
26 #define PCI_CFG_OUT out_be32
27 #define PEX_FIX out_be32(hose->cfg_addr+0x4, 0x0400ffff)
30 indirect_read_config_pcie(struct pci_controller *hose,
36 int bus = PCI_BUS(dev);
38 volatile unsigned char *cfg_data;
43 PCI_CFG_OUT(hose->cfg_addr,
44 dev | (offset & 0xfc) | 0x80000001);
46 PCI_CFG_OUT(hose->cfg_addr,
47 dev | (offset & 0xfc) | 0x80000000);
50 * Note: the caller has already checked that offset is
51 * suitably aligned and that len is 1, 2 or 4.
53 /* ERRATA PCI-Ex 12 - Configuration Address/Data Alignment */
54 cfg_data = hose->cfg_data;
56 temp = in_le32((u32 *) cfg_data);
59 *val = (temp >> (((offset & 3)) * 8)) & 0xff;
62 *val = (temp >> (((offset & 3)) * 8)) & 0xffff;
73 indirect_write_config_pcie(struct pci_controller *hose,
79 int bus = PCI_BUS(dev);
80 volatile unsigned char *cfg_data;
85 PCI_CFG_OUT(hose->cfg_addr,
86 dev | (offset & 0xfc) | 0x80000001);
88 PCI_CFG_OUT(hose->cfg_addr,
89 dev | (offset & 0xfc) | 0x80000000);
93 * Note: the caller has already checked that offset is
94 * suitably aligned and that len is 1, 2 or 4.
96 /* ERRATA PCI-Ex 12 - Configuration Address/Data Alignment */
97 cfg_data = hose->cfg_data;
101 temp = in_le32((u32 *) cfg_data);
102 temp = (temp & ~(0xff << ((offset & 3) * 8))) |
103 (val << ((offset & 3) * 8));
105 out_le32((u32 *) cfg_data, temp);
109 temp = in_le32((u32 *) cfg_data);
110 temp = (temp & ~(0xffff << ((offset & 3) * 8)));
111 temp |= (val << ((offset & 3) * 8));
113 out_le32((u32 *) cfg_data, temp);
117 out_le32((u32 *) cfg_data, val);
125 indirect_read_config_byte_pcie(struct pci_controller *hose,
131 indirect_read_config_pcie(hose, dev, offset, 1, &val32);
137 indirect_read_config_word_pcie(struct pci_controller *hose,
143 indirect_read_config_pcie(hose, dev, offset, 2, &val32);
149 indirect_read_config_dword_pcie(struct pci_controller *hose,
154 return indirect_read_config_pcie(hose, dev, offset, 4, val);
158 indirect_write_config_byte_pcie(struct pci_controller *hose,
163 return indirect_write_config_pcie(hose, dev, offset, 1, (u32) val);
167 indirect_write_config_word_pcie(struct pci_controller *hose,
172 return indirect_write_config_pcie(hose, dev, offset, 2, (u32) val);
176 indirect_write_config_dword_pcie(struct pci_controller *hose,
181 return indirect_write_config_pcie(hose, dev, offset, 4, val);
185 pcie_setup_indirect(struct pci_controller *hose, u32 cfg_addr, u32 cfg_data)
188 indirect_read_config_byte_pcie,
189 indirect_read_config_word_pcie,
190 indirect_read_config_dword_pcie,
191 indirect_write_config_byte_pcie,
192 indirect_write_config_word_pcie,
193 indirect_write_config_dword_pcie);
195 hose->cfg_addr = (unsigned int *)cfg_addr;
196 hose->cfg_data = (unsigned char *)cfg_data;
199 #endif /* CONFIG_PCI */