2 * Copyright 2005 Freescale Semiconductor.
3 * Ed Swarthout (ed.swarthout@freescale.com)
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * PEX Configuration space access support for MPC85xx PEX Bridge
31 #if defined(CONFIG_PCI)
34 pci_mpc86xx_init(struct pci_controller *hose)
36 volatile immap_t *immap = (immap_t *)CFG_CCSRBAR;
37 volatile ccsr_pex_t *pex1 = &immap->im_pex1;
38 volatile ccsr_gur_t *gur = &immap->im_gur;
39 uint host1_agent = (gur->porbmsr & MPC86xx_PORBMSR_HA) >> 17;
40 uint pex1_host = (host1_agent == 2) || (host1_agent == 3);
42 u16 reg16, reg16_1, reg16_2, reg16_3;
48 uint pex1_agent = (host1_agent == 0) || (host1_agent == 1);
49 uint devdisr = gur->devdisr;
50 uint io_sel = (gur->pordevsr & MPC86xx_PORDEVSR_IO_SEL) >> 16;
52 if ((io_sel==2 || io_sel==3 || io_sel==5 || io_sel==6 || io_sel==7 || io_sel==0xF ) && !(devdisr & MPC86xx_DEVDISR_PCIEX1)){
53 printf ("PCI-EXPRESS 1: Configured as %s \n",
54 pex1_agent ? "Agent" : "Host");
55 printf (" Scanning PCI bus");
56 debug("0x%08x=0x%08x ", &pex1->pme_msg_det,pex1->pme_msg_det);
57 if (pex1->pme_msg_det) {
58 pex1->pme_msg_det = 0xffffffff;
59 debug (" with errors. Clearing. Now 0x%08x",pex1->pme_msg_det);
65 hose->first_busno = 0;
66 hose->last_busno = 0x7f;
68 pci_set_region(hose->regions + 0,
74 pci_set_region(hose->regions + 1,
80 hose->region_count = 2;
82 pci_setup_indirect(hose,
89 pci_register_hose(hose);
91 //#define MPC8548_REV1_PEX12_ERRATA
92 #ifdef MPC8548_REV1_PEX12_ERRATA
93 /* can only read/write 4 bytes */
94 pci_read_config_dword (PCI_BDF(0,0,0), PCI_VENDOR_ID, ®32);
95 printf("pex_mpc85xx_init: pex cr %2x %8x\n",PCI_VENDOR_ID, reg32);
97 pci_read_config_word (PCI_BDF(0,0,0), PCI_COMMAND, ®32);
98 reg32 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
99 pci_write_config_word(PCI_BDF(0,0,0), PCI_COMMAND, reg32);
101 pci_read_config_word (PCI_BDF(0,0,0), PCI_VENDOR_ID, ®16);
102 debug("pex_mpc86xx_init: read %2x %4x\n",PCI_VENDOR_ID, reg16);
103 pci_read_config_word (PCI_BDF(0,0,0), PCI_DEVICE_ID, ®16);
104 debug("pex_mpc86xx_init: read %2x %4x\n",PCI_DEVICE_ID, reg16);
106 pci_read_config_word (PCI_BDF(0,0,0), PCI_COMMAND, ®16);
107 reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
108 pci_write_config_word(PCI_BDF(0,0,0), PCI_COMMAND, reg16);
110 pci_read_config_word (PCI_BDF(0,0,0), PCI_COMMAND, ®16);
111 debug("pex_mpc86xx_init: read %2x %4x\n",PCI_COMMAND, reg16);
117 * Clear non-reserved bits in status register.
119 // pci_write_config_word(PCI_BDF(0,0,0), PCI_STATUS, 0xffff);
120 // pci_write_config_byte(PCI_BDF(0,0,0), PCI_LATENCY_TIMER,0x80);
122 pex1->powbar1 = (CFG_PCI1_MEM_BASE >> 12) & 0x000fffff;
123 pex1->powar1 = 0x8004401c; /* 512M MEM space */
124 pex1->potar1 = (CFG_PCI1_MEM_BASE >> 12) & 0x000fffff;
125 pex1->potear1 = 0x00000000;
127 pex1->powbar2 = (CFG_PCI1_IO_BASE >> 12) & 0x000fffff;
128 pex1->powar2 = 0x80088017; /* 16M IO space */
129 pex1->potar2 = 0x00000000;
130 pex1->potear2 = 0x00000000;
134 pex1->pitar1 = 0x00000000;
135 pex1->piwbar1 = (0x80000000 >> 12 ) & 0x000fffff;
136 pex1->piwar1 = 0xa0f5501e; /* Enable, Prefetch, Local Mem,
140 pex1->pitar2 = 0x00000000;
141 pex1->piwbar2 = (0xe2000000 >> 12 ) & 0x000fffff;
142 pex1->piwar2 = 0xa0f5501e; /* Enable, Prefetch, Local Mem,
146 /* if (pex1_host) { */
147 /* #ifdef MPC8548_REV1_PEX12_ERRATA */
148 /* pci_write_config_dword (PCI_BDF(0,0,0), 0x18, 0x00ff0100); */
153 *(u32 *)(0xf8008000)= 0x80000000;
154 debug("Received data for addr 0x%08lx is 0x%08lx\n", *(u32*)(0xf8008000), *(u32*)(0xf8008004));
157 pci_write_config_byte(PCI_BDF(0,0,0), PCI_PRIMARY_BUS,0x20);
158 pci_write_config_byte(PCI_BDF(0,0,0), PCI_SECONDARY_BUS,0x00);
159 pci_write_config_byte(PCI_BDF(0,0,0), PCI_SUBORDINATE_BUS,0x1F);
163 *(u32 *)(0xf8008000)= 0x80200000;
164 debug("Received data for addr 0x%08lx is 0x%08lx\n", *(u32*)(0xf8008000), *(u32*)(0xf8008004));
166 *(u32 *)(0xf8008000)= 0x80200000;
167 debug("Received data for addr 0x%08lx is 0x%08lx\n", *(u32*)(0xf8008000), *(u32*)(0xf8008004));
169 *(u32 *)(0xf8008000)= 0x80200000;
170 debug("Received data for addr 0x%08lx is 0x%08lx\n", *(u32*)(0xf8008000), *(u32*)(0xf8008004));
174 hose->last_busno = pci_hose_scan(hose);
175 hose->last_busno = 0x21;
176 debug("pex_mpc86xx_init: last_busno %x\n",hose->last_busno);
177 debug("pex_mpc86xx init: current_busno %x\n ",hose->current_busno);
180 printf("....PCI scan & enumeration done\n");
182 /* *(u32 *)(0xf8008000)= 0x80000000 | (0x12 << 11); */
183 /* printf("Received data for addr 0x%08lx is 0x%08lx\n", *(u32*)(0xf8008000), *(u32*)(0xf8008004)); */
185 /* if (hose->last_busno < 1) { */
186 /* hose->last_busno=1; /\*Hack*\/ */
188 /* hose->last_busno = 0; */
191 /* pci_read_config_dword (PCI_BDF(1,0,0), 0x18, ®32); */
192 /* printf("pex_mpc86xx_init: pex cr %2x %8x\n",0x18, reg32); */
196 #endif /* CONFIG_PCI */