Merge branch 'mpc86xx'
[oweals/u-boot.git] / cpu / mpc86xx / pci.c
1 /*
2  * Copyright 2005 Freescale Semiconductor.
3  * Ed Swarthout (ed.swarthout@freescale.com)
4  *
5  * See file CREDITS for list of people who contributed to this
6  * project.
7  *
8  * This program is free software; you can redistribute it and/or
9  * modify it under the terms of the GNU General Public License as
10  * published by the Free Software Foundation; either version 2 of
11  * the License, or (at your option) any later version.
12  *
13  * This program is distributed in the hope that it will be useful,
14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16  * GNU General Public License for more details.
17  *
18  * You should have received a copy of the GNU General Public License
19  * along with this program; if not, write to the Free Software
20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21  * MA 02111-1307 USA
22  */
23
24 /*
25  * PEX Configuration space access support for PEX Bridge
26  */
27 #include <common.h>
28 #include <pci.h>
29
30
31 #if defined(CONFIG_PCI)
32
33 void
34 pci_mpc86xx_init(struct pci_controller *hose)
35 {
36         volatile immap_t    *immap = (immap_t *)CFG_CCSRBAR;
37         volatile ccsr_pex_t *pex1 = &immap->im_pex1;
38         volatile ccsr_gur_t *gur = &immap->im_gur;
39         uint host1_agent = (gur->porbmsr & MPC86xx_PORBMSR_HA) >> 17;
40         uint pex1_host =   (host1_agent == 2) || (host1_agent == 3);
41
42         u16 reg16, reg16_1, reg16_2, reg16_3;
43         u32 reg32, i;
44
45         ulong addr, data;
46
47         uint pex1_agent =  (host1_agent == 0) || (host1_agent == 1);
48         uint devdisr = gur->devdisr;
49         uint io_sel = (gur->pordevsr & MPC86xx_PORDEVSR_IO_SEL) >> 16;
50
51         if ((io_sel==2 || io_sel==3 || io_sel==5
52              || io_sel==6 || io_sel==7 || io_sel==0xF )
53             && !(devdisr & MPC86xx_DEVDISR_PCIEX1)){
54                 printf ("PCI-EXPRESS 1: Configured as %s \n",
55                         pex1_agent ? "Agent" : "Host");
56                 printf ("               Scanning PCI bus");
57                 debug("0x%08x=0x%08x ", &pex1->pme_msg_det,pex1->pme_msg_det);
58                 if (pex1->pme_msg_det) {
59                         pex1->pme_msg_det = 0xffffffff;
60                         debug (" with errors.  Clearing.  Now 0x%08x",
61                                pex1->pme_msg_det);
62                 }
63                 debug ("\n");
64         }
65
66         hose->first_busno = 0;
67         hose->last_busno = 0x7f;
68
69         pci_set_region(hose->regions + 0,
70                        CFG_PCI1_MEM_BASE,
71                        CFG_PCI1_MEM_PHYS,
72                        CFG_PCI1_MEM_SIZE,
73                        PCI_REGION_MEM);
74
75         pci_set_region(hose->regions + 1,
76                        CFG_PCI1_IO_BASE,
77                        CFG_PCI1_IO_PHYS,
78                        CFG_PCI1_IO_SIZE,
79                        PCI_REGION_IO);
80
81         hose->region_count = 2;
82
83         pci_setup_indirect(hose,
84                            (CFG_IMMR+0x8000),
85                            (CFG_IMMR+0x8004));
86
87         /*
88          * Hose scan.
89          */
90         pci_register_hose(hose);
91
92         pci_read_config_word (PCI_BDF(0,0,0), PCI_VENDOR_ID, &reg16);
93         debug("pex_mpc86xx_init: read %2x %4x\n",PCI_VENDOR_ID, reg16);
94         pci_read_config_word (PCI_BDF(0,0,0), PCI_DEVICE_ID, &reg16);
95         debug("pex_mpc86xx_init: read %2x %4x\n",PCI_DEVICE_ID, reg16);
96
97         pci_read_config_word (PCI_BDF(0,0,0), PCI_COMMAND, &reg16);
98         reg16 |= PCI_COMMAND_SERR |  PCI_COMMAND_PARITY \
99                 | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
100         pci_write_config_word(PCI_BDF(0,0,0), PCI_COMMAND, reg16);
101
102         pci_read_config_word (PCI_BDF(0,0,0), PCI_COMMAND, &reg16);
103         debug("pex_mpc86xx_init: read %2x %4x\n",PCI_COMMAND, reg16);
104
105         /*
106          * Clear non-reserved bits in status register.
107          */
108         /*
109          * pci_write_config_word(PCI_BDF(0,0,0), PCI_STATUS, 0xffff);
110          * pci_write_config_byte(PCI_BDF(0,0,0), PCI_LATENCY_TIMER,0x80);
111          */
112
113         pex1->powbar1  = (CFG_PCI1_MEM_BASE >> 12) & 0x000fffff;
114         pex1->powar1   = 0x8004401c;    /* 512M MEM space */
115         pex1->potar1   = (CFG_PCI1_MEM_BASE >> 12) & 0x000fffff;
116         pex1->potear1  = 0x00000000;
117
118         pex1->powbar2  = (CFG_PCI1_IO_BASE >> 12) & 0x000fffff;
119         pex1->powar2   = 0x80088017;    /* 16M IO space */
120         pex1->potar2   = 0x00000000;
121         pex1->potear2  = 0x00000000;
122
123         if (!pex1->piwar1) {
124                 pex1->pitar1 = 0x00000000;
125                 pex1->piwbar1 = (0x80000000 >> 12 ) & 0x000fffff;
126                 pex1->piwar1 = 0xa0f5501e;      /* Enable, Prefetch, Local Mem,
127                                                  * Snoop R/W, 2G */
128         }
129
130         pex1->pitar2 = 0x00000000;
131         pex1->piwbar2 = (0xe2000000 >> 12 ) & 0x000fffff;
132         pex1->piwar2 = 0xa0f5501e;      /* Enable, Prefetch, Local Mem,
133                                                  * Snoop R/W, 2G */
134
135         *(u32 *)(0xf8008000)= 0x80000000;
136         debug("Received data for addr 0x%08lx is 0x%08lx\n",
137               *(u32*)(0xf8008000), *(u32*)(0xf8008004));
138
139         pci_write_config_byte(PCI_BDF(0,0,0), PCI_PRIMARY_BUS,0x20);
140         pci_write_config_byte(PCI_BDF(0,0,0), PCI_SECONDARY_BUS,0x00);
141         pci_write_config_byte(PCI_BDF(0,0,0), PCI_SUBORDINATE_BUS,0x1F);
142
143         *(u32 *)(0xf8008000)= 0x80200000;
144         debug("Received data for addr 0x%08lx is 0x%08lx\n",
145               *(u32*)(0xf8008000), *(u32*)(0xf8008004));
146
147         *(u32 *)(0xf8008000)= 0x80200000;
148         debug("Received data for addr 0x%08lx is 0x%08lx\n",
149               *(u32*)(0xf8008000), *(u32*)(0xf8008004));
150
151         *(u32 *)(0xf8008000)= 0x80200000;
152         debug("Received data for addr 0x%08lx is 0x%08lx\n",
153               *(u32*)(0xf8008000), *(u32*)(0xf8008004));
154
155         hose->last_busno = pci_hose_scan(hose);
156         hose->last_busno = 0x21;
157         debug("pex_mpc86xx_init: last_busno %x\n",hose->last_busno);
158         debug("pex_mpc86xx init: current_busno %x\n ",hose->current_busno);
159
160         printf("....PCI scan & enumeration done\n");
161 }
162
163 #endif /* CONFIG_PCI */