2 * Copyright 2006 Freescale Semiconductor
4 * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 #include <asm/cache.h>
31 #if defined(CONFIG_OF_FLAT_TREE)
35 #ifdef CONFIG_MPC8641HPCN
36 extern void mpc8641_reset_board(cmd_tbl_t *cmdtp, int flag,
37 int argc, char *argv[]);
48 uint lcrr; /* local bus clock ratio register */
49 uint clkdiv; /* clock divider portion of lcrr */
51 puts("Freescale PowerPC\n");
62 case PVR_VER(PVR_86xx):
69 printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr);
79 if (SVR_SUBVER(svr) == 1) {
89 printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr);
91 get_sys_info(&sysinfo);
94 printf("CPU:%4lu MHz, ", sysinfo.freqProcessor / 1000000);
95 printf("MPX:%4lu MHz, ", sysinfo.freqSystemBus / 1000000);
96 printf("DDR:%4lu MHz, ", sysinfo.freqSystemBus / 2000000);
98 #if defined(CFG_LBC_LCRR)
102 volatile immap_t *immap = (immap_t *) CFG_IMMR;
103 volatile ccsr_lbc_t *lbc = &immap->im_lbc;
108 clkdiv = lcrr & 0x0f;
109 if (clkdiv == 2 || clkdiv == 4 || clkdiv == 8) {
110 printf("LBC:%4lu MHz\n",
111 sysinfo.freqSystemBus / 1000000 / clkdiv);
113 printf(" LBC: unknown (lcrr: 0x%08x)\n", lcrr);
117 if (get_l2cr() & 0x80000000)
127 soft_restart(unsigned long addr)
129 #ifndef CONFIG_MPC8641HPCN
132 * SRR0 has system reset vector, SRR1 has default MSR value
133 * rfi restores MSR from SRR1 and sets the PC to the SRR0 value
136 __asm__ __volatile__ ("mtspr 26, %0" :: "r" (addr));
137 __asm__ __volatile__ ("li 4, (1 << 6)" ::: "r4");
138 __asm__ __volatile__ ("mtspr 27, 4");
139 __asm__ __volatile__ ("rfi");
141 #else /* CONFIG_MPC8641HPCN */
143 out8(PIXIS_BASE + PIXIS_RST, 0);
145 #endif /* !CONFIG_MPC8641HPCN */
147 while (1) ; /* not reached */
152 * No generic way to do board reset. Simply call soft_reset.
155 do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
157 #ifndef CONFIG_MPC8641HPCN
159 #ifdef CFG_RESET_ADDRESS
160 ulong addr = CFG_RESET_ADDRESS;
163 * note: when CFG_MONITOR_BASE points to a RAM address,
164 * CFG_MONITOR_BASE - sizeof (ulong) is usually a valid
165 * address. Better pick an address known to be invalid on your
166 * system and assign it to CFG_RESET_ADDRESS.
168 ulong addr = CFG_MONITOR_BASE - sizeof(ulong);
171 /* flush and disable I/D cache */
172 __asm__ __volatile__ ("mfspr 3, 1008" ::: "r3");
173 __asm__ __volatile__ ("ori 5, 5, 0xcc00" ::: "r5");
174 __asm__ __volatile__ ("ori 4, 3, 0xc00" ::: "r4");
175 __asm__ __volatile__ ("andc 5, 3, 5" ::: "r5");
176 __asm__ __volatile__ ("sync");
177 __asm__ __volatile__ ("mtspr 1008, 4");
178 __asm__ __volatile__ ("isync");
179 __asm__ __volatile__ ("sync");
180 __asm__ __volatile__ ("mtspr 1008, 5");
181 __asm__ __volatile__ ("isync");
182 __asm__ __volatile__ ("sync");
186 #else /* CONFIG_MPC8641HPCN */
188 mpc8641_reset_board(cmdtp, flag, argc, argv);
190 #endif /* !CONFIG_MPC8641HPCN */
192 while (1) ; /* not reached */
197 * Get timebase clock frequency
204 get_sys_info(&sys_info);
205 return (sys_info.freqSystemBus + 3L) / 4L;
209 #if defined(CONFIG_WATCHDOG)
214 #endif /* CONFIG_WATCHDOG */
217 #if defined(CONFIG_DDR_ECC)
221 volatile immap_t *immap = (immap_t *) CFG_IMMR;
222 volatile ccsr_dma_t *dma = &immap->im_dma;
224 dma->satr0 = 0x00040000;
225 dma->datr0 = 0x00040000;
232 volatile immap_t *immap = (immap_t *) CFG_IMMR;
233 volatile ccsr_dma_t *dma = &immap->im_dma;
234 volatile uint status = dma->sr0;
236 /* While the channel is busy, spin */
237 while ((status & 4) == 4) {
242 printf("DMA Error: status = %x\n", status);
248 dma_xfer(void *dest, uint count, void *src)
250 volatile immap_t *immap = (immap_t *) CFG_IMMR;
251 volatile ccsr_dma_t *dma = &immap->im_dma;
253 dma->dar0 = (uint) dest;
254 dma->sar0 = (uint) src;
256 dma->mr0 = 0xf000004;
258 dma->mr0 = 0xf000005;
263 #endif /* CONFIG_DDR_ECC */
266 #ifdef CONFIG_OF_FLAT_TREE
268 ft_cpu_setup(void *blob, bd_t *bd)
274 clock = bd->bi_busfreq;
275 p = ft_get_prop(blob, "/cpus/" OF_CPU "/bus-frequency", &len);
277 *p = cpu_to_be32(clock);
279 p = ft_get_prop(blob, "/" OF_SOC "/serial@4500/clock-frequency", &len);
281 *p = cpu_to_be32(clock);
283 p = ft_get_prop(blob, "/" OF_SOC "/serial@4600/clock-frequency", &len);
285 *p = cpu_to_be32(clock);
287 #if defined(CONFIG_MPC86XX_TSEC1)
288 p = ft_get_prop(blob, "/" OF_SOC "/ethernet@24000/mac-address", &len);
289 memcpy(p, bd->bi_enetaddr, 6);
292 #if defined(CONFIG_MPC86XX_TSEC2)
293 p = ft_get_prop(blob, "/" OF_SOC "/ethernet@25000/mac-address", &len);
294 memcpy(p, bd->bi_enet1addr, 6);
297 #if defined(CONFIG_MPC86XX_TSEC3)
298 p = ft_get_prop(blob, "/" OF_SOC "/ethernet@26000/mac-address", &len);
299 memcpy(p, bd->bi_enet2addr, 6);
302 #if defined(CONFIG_MPC86XX_TSEC4)
303 p = ft_get_prop(blob, "/" OF_SOC "/ethernet@27000/mac-address", &len);
304 memcpy(p, bd->bi_enet3addr, 6);