2 * Copyright 2006 Freescale Semiconductor
4 * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 #include <asm/cache.h>
31 #if defined(CONFIG_OF_FLAT_TREE)
35 #ifdef CONFIG_MPC8641HPCN
36 extern void mpc8641_reset_board(cmd_tbl_t *cmdtp, int flag,
37 int argc, char *argv[]);
47 uint lcrr; /* local bus clock ratio register */
48 uint clkdiv; /* clock divider portion of lcrr */
50 puts("Freescale PowerPC\n");
61 case PVR_VER(PVR_86xx):
68 printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr);
87 printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr);
89 get_sys_info(&sysinfo);
92 printf("CPU:%4lu MHz, ", sysinfo.freqProcessor / 1000000);
93 printf("MPX:%4lu MHz, ", sysinfo.freqSystemBus / 1000000);
94 printf("DDR:%4lu MHz, ", sysinfo.freqSystemBus / 2000000);
96 #if defined(CFG_LBC_LCRR)
100 volatile immap_t *immap = (immap_t *)CFG_IMMR;
101 volatile ccsr_lbc_t *lbc= &immap->im_lbc;
106 clkdiv = lcrr & 0x0f;
107 if (clkdiv == 2 || clkdiv == 4 || clkdiv == 8) {
108 printf("LBC:%4lu MHz\n",
109 sysinfo.freqSystemBus / 1000000 / clkdiv);
111 printf(" LBC: unknown (lcrr: 0x%08x)\n", lcrr);
115 if (get_l2cr() & 0x80000000)
125 soft_restart(unsigned long addr)
127 #ifndef CONFIG_MPC8641HPCN
129 /* SRR0 has system reset vector, SRR1 has default MSR value */
130 /* rfi restores MSR from SRR1 and sets the PC to the SRR0 value */
132 __asm__ __volatile__ ("mtspr 26, %0" :: "r" (addr));
133 __asm__ __volatile__ ("li 4, (1 << 6)" ::: "r4");
134 __asm__ __volatile__ ("mtspr 27, 4");
135 __asm__ __volatile__ ("rfi");
137 #else /* CONFIG_MPC8641HPCN */
139 out8(PIXIS_BASE + PIXIS_RST, 0);
141 #endif /* !CONFIG_MPC8641HPCN */
143 while(1); /* not reached */
148 * No generic way to do board reset. Simply call soft_reset.
151 do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
153 #ifndef CONFIG_MPC8641HPCN
155 #ifdef CFG_RESET_ADDRESS
156 ulong addr = CFG_RESET_ADDRESS;
159 * note: when CFG_MONITOR_BASE points to a RAM address,
160 * CFG_MONITOR_BASE - sizeof (ulong) is usually a valid
161 * address. Better pick an address known to be invalid on your
162 * system and assign it to CFG_RESET_ADDRESS.
164 ulong addr = CFG_MONITOR_BASE - sizeof(ulong);
167 /* flush and disable I/D cache */
168 __asm__ __volatile__ ("mfspr 3, 1008" ::: "r3");
169 __asm__ __volatile__ ("ori 5, 5, 0xcc00" ::: "r5");
170 __asm__ __volatile__ ("ori 4, 3, 0xc00" ::: "r4");
171 __asm__ __volatile__ ("andc 5, 3, 5" ::: "r5");
172 __asm__ __volatile__ ("sync");
173 __asm__ __volatile__ ("mtspr 1008, 4");
174 __asm__ __volatile__ ("isync");
175 __asm__ __volatile__ ("sync");
176 __asm__ __volatile__ ("mtspr 1008, 5");
177 __asm__ __volatile__ ("isync");
178 __asm__ __volatile__ ("sync");
182 #else /* CONFIG_MPC8641HPCN */
184 mpc8641_reset_board(cmdtp, flag, argc, argv);
186 #endif /* !CONFIG_MPC8641HPCN */
188 while(1); /* not reached */
193 * Get timebase clock frequency
195 unsigned long get_tbclk(void)
199 get_sys_info(&sys_info);
200 return (sys_info.freqSystemBus + 3L) / 4L;
204 #if defined(CONFIG_WATCHDOG)
209 #endif /* CONFIG_WATCHDOG */
212 #if defined(CONFIG_DDR_ECC)
215 volatile immap_t *immap = (immap_t *)CFG_IMMR;
216 volatile ccsr_dma_t *dma = &immap->im_dma;
218 dma->satr0 = 0x00040000;
219 dma->datr0 = 0x00040000;
225 volatile immap_t *immap = (immap_t *)CFG_IMMR;
226 volatile ccsr_dma_t *dma = &immap->im_dma;
227 volatile uint status = dma->sr0;
229 /* While the channel is busy, spin */
230 while((status & 4) == 4) {
235 printf ("DMA Error: status = %x\n", status);
240 int dma_xfer(void *dest, uint count, void *src)
242 volatile immap_t *immap = (immap_t *)CFG_IMMR;
243 volatile ccsr_dma_t *dma = &immap->im_dma;
245 dma->dar0 = (uint) dest;
246 dma->sar0 = (uint) src;
248 dma->mr0 = 0xf000004;
250 dma->mr0 = 0xf000005;
255 #endif /* CONFIG_DDR_ECC */
258 #ifdef CONFIG_OF_FLAT_TREE
259 void ft_cpu_setup(void *blob, bd_t *bd)
265 clock = bd->bi_busfreq;
266 p = ft_get_prop(blob, "/cpus/" OF_CPU "/bus-frequency", &len);
268 *p = cpu_to_be32(clock);
270 p = ft_get_prop(blob, "/" OF_SOC "/serial@4500/clock-frequency", &len);
272 *p = cpu_to_be32(clock);
274 p = ft_get_prop(blob, "/" OF_SOC "/serial@4600/clock-frequency", &len);
276 *p = cpu_to_be32(clock);
278 #if defined(CONFIG_MPC86XX_TSEC1)
279 p = ft_get_prop(blob, "/" OF_SOC "/ethernet@24000/mac-address", &len);
280 memcpy(p, bd->bi_enetaddr, 6);
283 #if defined(CONFIG_MPC86XX_TSEC2)
284 p = ft_get_prop(blob, "/" OF_SOC "/ethernet@25000/mac-address", &len);
285 memcpy(p, bd->bi_enet1addr, 6);
288 #if defined(CONFIG_MPC86XX_TSEC3)
289 p = ft_get_prop(blob, "/" OF_SOC "/ethernet@26000/mac-address", &len);
290 memcpy(p, bd->bi_enet2addr, 6);
293 #if defined(CONFIG_MPC86XX_TSEC4)
294 p = ft_get_prop(blob, "/" OF_SOC "/ethernet@27000/mac-address", &len);
295 memcpy(p, bd->bi_enet3addr, 6);