2 * Copyright 2006 Freescale Semiconductor
4 * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 #include <asm/cache.h>
32 #include <asm/fsl_law.h>
34 struct cpu_type cpu_type_list [] = {
35 CPU_TYPE_ENTRY(8610, 8610),
36 CPU_TYPE_ENTRY(8641, 8641),
37 CPU_TYPE_ENTRY(8641D, 8641D),
40 struct cpu_type *identify_cpu(u32 ver)
43 for (i = 0; i < ARRAY_SIZE(cpu_type_list); i++)
44 if (cpu_type_list[i].soc_ver == ver)
45 return &cpu_type_list[i];
51 * Default board reset function
58 void board_reset(void) __attribute__((weak, alias("__board_reset")));
68 char buf1[32], buf2[32];
69 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
70 volatile ccsr_gur_t *gur = &immap->im_gur;
72 uint msscr0 = mfspr(MSSCR0);
75 ver = SVR_SOC_VER(svr);
81 cpu = identify_cpu(ver);
88 printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr);
92 ver = PVR_E600_VER(pvr);
93 major = PVR_E600_MAJ(pvr);
94 minor = PVR_E600_MIN(pvr);
96 printf("E600 Core %d", (msscr0 & 0x20) ? 1 : 0 );
97 if (gur->pordevsr & MPC86xx_PORDEVSR_CORE1TE)
98 puts("\n Core1Translation Enabled");
99 debug(" (MSSCR0=%x, PORDEVSR=%x)", msscr0, gur->pordevsr);
101 printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr);
103 get_sys_info(&sysinfo);
105 puts("Clock Configuration:\n");
106 printf(" CPU:%-4s MHz, ", strmhz(buf1, sysinfo.freqProcessor));
107 printf("MPX:%-4s MHz\n", strmhz(buf1, sysinfo.freqSystemBus));
108 printf(" DDR:%-4s MHz (%s MT/s data rate), ",
109 strmhz(buf1, sysinfo.freqSystemBus / 2),
110 strmhz(buf2, sysinfo.freqSystemBus));
112 if (sysinfo.freqLocalBus > LCRR_CLKDIV) {
113 printf("LBC:%-4s MHz\n", strmhz(buf1, sysinfo.freqLocalBus));
115 printf("LBC: unknown (LCRR[CLKDIV] = 0x%02lx)\n",
116 sysinfo.freqLocalBus);
119 puts("L1: D-cache 32 KB enabled\n");
120 puts(" I-cache 32 KB enabled\n");
123 if (get_l2cr() & 0x80000000) {
124 #if defined(CONFIG_MPC8610)
126 #elif defined(CONFIG_MPC8641)
129 puts(" KB enabled\n");
139 do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
141 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
142 volatile ccsr_gur_t *gur = &immap->im_gur;
144 /* Attempt board-specific reset */
147 /* Next try asserting HRESET_REQ */
148 out_be32(&gur->rstcr, MPC86xx_RSTCR_HRST_REQ);
156 * Get timebase clock frequency
163 get_sys_info(&sys_info);
164 return (sys_info.freqSystemBus + 3L) / 4L;
168 #if defined(CONFIG_WATCHDOG)
172 #if defined(CONFIG_MPC8610)
174 * This actually feed the hard enabled watchdog.
176 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
177 volatile ccsr_wdt_t *wdt = &immap->im_wdt;
178 volatile ccsr_gur_t *gur = &immap->im_gur;
179 u32 tmp = gur->pordevsr;
187 #endif /* CONFIG_WATCHDOG */
190 #if defined(CONFIG_DDR_ECC)
194 volatile ccsr_dma_t *dma_base = (void *)(CONFIG_SYS_MPC86xx_DMA_ADDR);
195 volatile fsl_dma_t *dma = &dma_base->dma[0];
197 dma->satr = 0x00040000;
198 dma->datr = 0x00040000;
199 dma->sr = 0xffffffff; /* clear any errors */
206 volatile ccsr_dma_t *dma_base = (void *)(CONFIG_SYS_MPC86xx_DMA_ADDR);
207 volatile fsl_dma_t *dma = &dma_base->dma[0];
208 volatile uint status = dma->sr;
210 /* While the channel is busy, spin */
211 while ((status & 4) == 4) {
215 /* clear MR[CS] channel start bit */
216 dma->mr &= 0x00000001;
220 printf("DMA Error: status = %x\n", status);
226 dma_xfer(void *dest, uint count, void *src)
228 volatile ccsr_dma_t *dma_base = (void *)(CONFIG_SYS_MPC86xx_DMA_ADDR);
229 volatile fsl_dma_t *dma = &dma_base->dma[0];
231 dma->dar = (uint) dest;
232 dma->sar = (uint) src;
241 #endif /* CONFIG_DDR_ECC */
245 * Print out the state of various machine registers.
246 * Currently prints out LAWs, BR0/OR0, and BATs
248 void mpc86xx_reginfo(void)
250 immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
251 ccsr_lbc_t *lbc = &immap->im_lbc;
256 printf ("Local Bus Controller Registers\n"
257 "\tBR0\t0x%08X\tOR0\t0x%08X \n", in_be32(&lbc->br0), in_be32(&lbc->or0));
258 printf("\tBR1\t0x%08X\tOR1\t0x%08X \n", in_be32(&lbc->br1), in_be32(&lbc->or1));
259 printf("\tBR2\t0x%08X\tOR2\t0x%08X \n", in_be32(&lbc->br2), in_be32(&lbc->or2));
260 printf("\tBR3\t0x%08X\tOR3\t0x%08X \n", in_be32(&lbc->br3), in_be32(&lbc->or3));
261 printf("\tBR4\t0x%08X\tOR4\t0x%08X \n", in_be32(&lbc->br4), in_be32(&lbc->or4));
262 printf("\tBR5\t0x%08X\tOR5\t0x%08X \n", in_be32(&lbc->br5), in_be32(&lbc->or5));
263 printf("\tBR6\t0x%08X\tOR6\t0x%08X \n", in_be32(&lbc->br6), in_be32(&lbc->or6));
264 printf("\tBR7\t0x%08X\tOR7\t0x%08X \n", in_be32(&lbc->br7), in_be32(&lbc->or7));
269 * Initializes on-chip ethernet controllers.
270 * to override, implement board_eth_init()
272 int cpu_eth_init(bd_t *bis)
274 #if defined(CONFIG_TSEC_ENET)
275 tsec_standard_init(bis);